From patchwork Thu Mar 11 20:04:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 88964 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2992CA0564; Thu, 11 Mar 2021 21:05:12 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C40EA160822; Thu, 11 Mar 2021 21:05:07 +0100 (CET) Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) by mails.dpdk.org (Postfix) with ESMTP id 93215160812 for ; Thu, 11 Mar 2021 21:05:05 +0100 (CET) Received: by mail-pl1-f172.google.com with SMTP id u18so10751269plc.12 for ; Thu, 11 Mar 2021 12:05:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=9AS9rSY9pcNTxBOac84kP7RLfylx1qhy2WXoSKV/Ybg=; b=Sg70A8ky9cTX7mosLSRmlfYvQLIcxhJQNYSv0HItJytscch34lEFtljKdFQlNVHmKS 2GdOtFqk5obpcUoJ5EVykHi+dleRu3i7BCG+iOKMcGz2nV9syN6YwNRYmYytd7NkAJbb r8j65tqW4zEtRTHUe7oUoQCSFnOExPO76XZ44= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=9AS9rSY9pcNTxBOac84kP7RLfylx1qhy2WXoSKV/Ybg=; b=LEGQ546MIHLuRgDnsv/P4zoIES1dv6JNUddwh3J9Nfu4khDRVXfiNJYLyTYM50lVVr 211wu5NLFGCewEGpg+0549K5pcz3UP4kYaJdK+MSIJV2GLqH9s2rGFoqyM+MBTPb0OKf IDlj/I00uLLJQug/MBzzRe5xDofl1ZFLGhuQam/UoL39ZA4jskvWcHH5P7WXN5CMlCvC o/ckAgyPliRQ7p1gDxmbqyZknnibDORZqhMqxSaIRReIxM3sDHWmvpiC3ZS7zXVJzw+U r8L0UOiCT7rfTWIB++L6FuD/zOWhBr5aJ8M6Z6uPpyW9SD6v84a5lKV5WKU8zh1pl/Vn DjJg== X-Gm-Message-State: AOAM531mLYFotAq+du2RIds1EZP3gpPWtu3cqY8z3cC0NpSlNPgtqj57 l9wqMfu/wFObTYUkYrD+ws744w== X-Google-Smtp-Source: ABdhPJxx+R+8PB5dxRVXGJzrNmNNwrGIFdFkh71nn2dU1RcWV5QFi+iFAMQUaNu+cFd6AkpZe+OHEg== X-Received: by 2002:a17:90b:1044:: with SMTP id gq4mr10265642pjb.232.1615493104537; Thu, 11 Mar 2021 12:05:04 -0800 (PST) Received: from localhost.localdomain ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id c16sm3115360pfc.112.2021.03.11.12.05.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Mar 2021 12:05:03 -0800 (PST) From: Ajit Khaparde To: lance.richardson@broadcom.com Cc: ajit.khaparde@broadcom.com, dev@dpdk.org, gospo@broadcom.com, stable@dpdk.org Date: Thu, 11 Mar 2021 12:04:58 -0800 Message-Id: <20210311200458.40432-1-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20210311182819.27126-1-ajit.khaparde@broadcom.com> References: <20210311182819.27126-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-dev] [PATCH v3] net/bnxt: fix Rx descriptor status X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Lance Richardson Fix a number of issues in the bnxt receive descriptor status function, including: - Provide status of receive descriptor instead of completion descriptor. - Remove invalid comparison of raw ring index with masked ring index. - Correct misinterpretation of offset parameter as ring index. - Correct misuse of completion ring index for mbuf ring (the two rings have different sizes). Fixes: 0fe613bb87b2 ("net/bnxt: support Rx descriptor status") Cc: stable@dpdk.org Signed-off-by: Lance Richardson Reviewed-by: Andy Gospodarek Reviewed-by: Ajit Khaparde --- v1->v2: rebase against latest tree. v2->v3: fix compilation on PPC. Compile tested only. --- drivers/net/bnxt/bnxt_ethdev.c | 110 ++++++++++++++++++++++++++------- 1 file changed, 88 insertions(+), 22 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index c55a2d8197..cefd6915d7 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -3076,42 +3076,108 @@ bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) static int bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) { - struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; - struct bnxt_rx_ring_info *rxr; + struct bnxt_rx_queue *rxq = rx_queue; struct bnxt_cp_ring_info *cpr; - struct rte_mbuf *rx_buf; + struct bnxt_rx_ring_info *rxr; + uint32_t desc, cons, raw_cons; + struct bnxt *bp = rxq->bp; struct rx_pkt_cmpl *rxcmp; - uint32_t cons, cp_cons; int rc; - if (!rxq) - return -EINVAL; - - rc = is_bnxt_in_error(rxq->bp); + rc = is_bnxt_in_error(bp); if (rc) return rc; - cpr = rxq->cp_ring; - rxr = rxq->rx_ring; - if (offset >= rxq->nb_rx_desc) return -EINVAL; - cons = RING_CMP(cpr->cp_ring_struct, offset); - cp_cons = cpr->cp_raw_cons; - rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + rxr = rxq->rx_ring; + cpr = rxq->cp_ring; - if (cons > cp_cons) { - if (CMPL_VALID(rxcmp, cpr->valid)) - return RTE_ETH_RX_DESC_DONE; - } else { - if (CMPL_VALID(rxcmp, !cpr->valid)) + /* + * For the vector receive case, the completion at the requested + * offset can be indexed directly. + */ +#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) + if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { + struct rx_pkt_cmpl *rxcmp; + + /* Check status of completion descriptor. */ + raw_cons = cpr->cp_raw_cons + + offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); + rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + + if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) return RTE_ETH_RX_DESC_DONE; + + /* Check whether rx desc has an mbuf attached. */ + cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); + if (cons >= rxq->rxrearm_start && + cons < rxq->rxrearm_start + rxq->rxrearm_nb) { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + return RTE_ETH_RX_DESC_AVAIL; } - rx_buf = rxr->rx_buf_ring[cons]; - if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf) - return RTE_ETH_RX_DESC_UNAVAIL; +#endif + + /* + * For the non-vector receive case, scan the completion ring to + * locate the completion descriptor for the requested offset. + */ + raw_cons = cpr->cp_raw_cons; + desc = 0; + while (1) { + uint32_t agg_cnt, cons, cmpl_type; + + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); + rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) + break; + + cmpl_type = CMP_TYPE(rxcmp); + + switch (cmpl_type) { + case CMPL_BASE_TYPE_RX_L2: + case CMPL_BASE_TYPE_RX_L2_V2: + if (desc == offset) { + cons = rxcmp->opaque; + if (rxr->rx_buf_ring[cons]) + return RTE_ETH_RX_DESC_DONE; + else + return RTE_ETH_RX_DESC_UNAVAIL; + } + agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + case CMPL_BASE_TYPE_RX_TPA_END: + if (desc == offset) + return RTE_ETH_RX_DESC_DONE; + + if (BNXT_CHIP_P5(rxq->bp)) { + struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; + + p5_tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); + } else { + struct rx_tpa_end_cmpl *tpa_end; + + tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); + } + + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + default: + raw_cons += CMP_LEN(cmpl_type); + } + } return RTE_ETH_RX_DESC_AVAIL; }