From patchwork Wed Mar 10 21:26:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 88909 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50190A056A; Wed, 10 Mar 2021 22:28:03 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CD3A622A5F4; Wed, 10 Mar 2021 22:27:08 +0100 (CET) Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) by mails.dpdk.org (Postfix) with ESMTP id 7650D22A5E6 for ; Wed, 10 Mar 2021 22:27:04 +0100 (CET) Received: by mail-pg1-f176.google.com with SMTP id w34so11189880pga.8 for ; Wed, 10 Mar 2021 13:27:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=0RRYAtRtHvL0UWHjhk76taagKXaZqgJhzoCqkEBPIXY=; b=Tv1gLXMtiADKtH0O7D+cf3EN72LjVvokSEs4qVo0lIfrKKftgPTlSonOY64jyVdW0m HCNg5scBrEMSMPbRdcy3PU62h6AGF5zOFzS1aSP9U0kVWO28qdPwljOGnMAg3sUlAYJ9 CAef6e4HTaok7GWa1sAfCkft0hGww80fvvqCI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=0RRYAtRtHvL0UWHjhk76taagKXaZqgJhzoCqkEBPIXY=; b=N1Pj6bPNHmAk/qz4ZmRHA6xhl1r4KR/ljjVep2ISFd7YUJ4SoDZlIZSNY8hF34k/rN T+y2p1890ZCd+QeJQQBveFlPR/JOfalEfsN+5AiBRxg7EKBwl+LpHSvWBvGmNAvB8/K3 8yaQbFn1rS+37uIIWkoIH2LV71camsHw5SPjlMiDz1ndeB+Tw324JWrV6lhEYyRMryLB zgv4IUhUC2vjoQbcrvxWIpuAqUP1JX1NtVkOBlsua5GtUGiK73esjnThPx+ffzkoMjWf WBT3Of8FeSXBpR+J4j4JE9w7uHyDiOEjupCLbMbiXRKwSUF0JI5kuUHndKgOEHeWsJx1 88FA== X-Gm-Message-State: AOAM533WEBMLM0hzpcCsOeJ8XqFcqjnFXDNpEM0LRCutQqigvF72eZST Q5BoHj75+76vx7WY7GMc1B+P3g== X-Google-Smtp-Source: ABdhPJzmz3f8Q+Ez2/akF9WwC1JVNt6Wa8vZv51ZBzZI1xhYuOBp67l9JMWwNTUI9pQCl1pvpezfRw== X-Received: by 2002:aa7:91d1:0:b029:1fe:2a02:73b9 with SMTP id z17-20020aa791d10000b02901fe2a0273b9mr2237263pfa.2.1615411623616; Wed, 10 Mar 2021 13:27:03 -0800 (PST) Received: from localhost.localdomain ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id f2sm265059pju.46.2021.03.10.13.27.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Mar 2021 13:27:02 -0800 (PST) From: Ajit Khaparde To: ferruh.yigit@intel.com Cc: ajit.khaparde@broadcom.com, dev@dpdk.org, kalesh-anakkur.purayil@broadcom.com, stable@dpdk.org, Somnath Kotur Date: Wed, 10 Mar 2021 13:26:35 -0800 Message-Id: <20210310212637.72205-11-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20210310212637.72205-1-ajit.khaparde@broadcom.com> References: <20210310212637.72205-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-dev] [PATCH v2 10/12] net/bnxt: fix firmware fatal error handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP During some fatal firmware error conditions, the PCI config space register 0x2e which normally contains the subsystem ID will become 0xffff. This register will revert back to the normal value after the chip has completed core reset. If we detect this condition, we can poll this config register immediately for the value to revert. Because we use config read cycles to poll this register, there is no possibility of Master Abort if we happen to read it during core reset. This speeds up recovery significantly as we don't have to wait for the conservative min_time before polling to see if the firmware has come out of reset. As soon as this register changes value we can proceed to re-initialize the device. Fixes: df6cd7c1f73a ("net/bnxt: handle reset notify async event from FW") Cc: stable@dpdk.org Signed-off-by: Kalesh AP Reviewed-by: Somnath Kotur Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt_ethdev.c | 56 ++++++++++++++++++++++++++++++++-- drivers/net/bnxt/bnxt_util.h | 2 ++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 9e0ec46403..67ff800da5 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -3743,6 +3743,32 @@ static void bnxt_dev_cleanup(struct bnxt *bp) bnxt_uninit_resources(bp, true); } +static int +bnxt_check_fw_reset_done(struct bnxt *bp) +{ + int timeout = bp->fw_reset_max_msecs; + uint16_t val = 0; + int rc; + + do { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return rc; + } + if (val != 0xffff) + break; + rte_delay_ms(1); + } while (timeout--); + + if (val == 0xffff) { + PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); + return -1; + } + + return 0; +} + static int bnxt_restore_vlan_filters(struct bnxt *bp) { struct rte_eth_dev *dev = bp->eth_dev; @@ -3840,6 +3866,13 @@ static void bnxt_dev_recover(void *arg) int rc = 0; pthread_mutex_lock(&bp->err_recovery_lock); + + if (!bp->fw_reset_min_msecs) { + rc = bnxt_check_fw_reset_done(bp); + if (rc) + goto err; + } + /* Clear Error flag so that device re-init should happen */ bp->flags &= ~BNXT_FLAG_FATAL_ERROR; @@ -3891,14 +3924,33 @@ static void bnxt_dev_recover(void *arg) void bnxt_dev_reset_and_resume(void *arg) { struct bnxt *bp = arg; + uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; + uint16_t val = 0; int rc; bnxt_dev_cleanup(bp); bnxt_wait_for_device_shutdown(bp); - rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, - bnxt_dev_recover, (void *)bp); + /* During some fatal firmware error conditions, the PCI config space + * register 0x2e which normally contains the subsystem ID will become + * 0xffff. This register will revert back to the normal value after + * the chip has completed core reset. If we detect this condition, + * we can poll this config register immediately for the value to revert. + */ + if (bp->flags & BNXT_FLAG_FATAL_ERROR) { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return; + } + if (val == 0xffff) { + bp->fw_reset_min_msecs = 0; + us = 1; + } + } + + rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); if (rc) PMD_DRV_LOG(ERR, "Error setting recovery alarm"); } diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h index 8de55e1038..64e97eed15 100644 --- a/drivers/net/bnxt/bnxt_util.h +++ b/drivers/net/bnxt/bnxt_util.h @@ -10,6 +10,8 @@ #define BIT(n) (1UL << (n)) #endif /* BIT */ +#define PCI_SUBSYSTEM_ID_OFFSET 0x2e + int bnxt_check_zero_bytes(const uint8_t *bytes, int len); void bnxt_eth_hw_addr_random(uint8_t *mac_addr);