From patchwork Fri Mar 5 16:21:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 88586 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DB76BA054F; Fri, 5 Mar 2021 19:13:45 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A2AA822A430; Fri, 5 Mar 2021 19:13:28 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 128AE22A3EA for ; Fri, 5 Mar 2021 17:22:06 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 125GEtta024240 for ; Fri, 5 Mar 2021 08:22:06 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=GpMY5QDCWzIgx+j6PBJ6nU97aWdbUqq1Q/BPu2Vwq74=; b=RiVmZz6zaDb/S6S1KNj/2DJrlfFY/aKY2MWzGGsZ5B//9xlqh4ptWtk222VgOh8o2d1N fOT+sZ3bOpqaFJyWpBTU4Cw5vpvi8ekjX+VsNuhguqDEinmdHQRPF3JBH001WuwnrRL1 wm2VTIkrDelXQ6iOnwdg1RKi+mquG3YTOjVQ58AW6nVC8E+L4u9bFvwr3lkhmkYnaw6+ jR+s+C9kBvI1CCIJ0SOh5Bt84DedOCsW8oM8YwyZUyoI+Gl8fvhf7z0q9TAnka/lGyMA YIUsMLj53EDtCCoKsX5fneLew9mV78xDId+GSWBP1uYlty2Do9DFhB5oDZ/FBP1nOC9e 2w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 372s2un6gb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 05 Mar 2021 08:22:06 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 5 Mar 2021 08:22:04 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 5 Mar 2021 08:22:04 -0800 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 1D6383F7041; Fri, 5 Mar 2021 08:22:01 -0800 (PST) From: Ashwin Sekhar T K To: CC: , , , , , , Date: Fri, 5 Mar 2021 21:51:46 +0530 Message-ID: <20210305162149.2196166-4-asekhar@marvell.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210305162149.2196166-1-asekhar@marvell.com> References: <20210305162149.2196166-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-05_10:2021-03-03, 2021-03-05 signatures=0 X-Mailman-Approved-At: Fri, 05 Mar 2021 19:13:23 +0100 Subject: [dpdk-dev] [PATCH 3/6] mempool/cnxk: add cn9k mempool ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add mempool ops specific to cn9k. Signed-off-by: Ashwin Sekhar T K --- drivers/mempool/cnxk/cn9k_mempool_ops.c | 90 +++++++++++++++++++++++++ drivers/mempool/cnxk/meson.build | 3 +- 2 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 drivers/mempool/cnxk/cn9k_mempool_ops.c diff --git a/drivers/mempool/cnxk/cn9k_mempool_ops.c b/drivers/mempool/cnxk/cn9k_mempool_ops.c new file mode 100644 index 0000000000..3a7de39db2 --- /dev/null +++ b/drivers/mempool/cnxk/cn9k_mempool_ops.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include + +#include "roc_api.h" +#include "cnxk_mempool.h" + +static int __rte_hot +cn9k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, unsigned int n) +{ + /* Ensure mbuf init changes are written before the free pointers + * are enqueued to the stack. + */ + rte_io_wmb(); + roc_npa_aura_op_bulk_free(mp->pool_id, (const uint64_t *)obj_table, n, + 0); + + return 0; +} + +static inline int __rte_hot +cn9k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) +{ + unsigned int count; + + count = roc_npa_aura_op_bulk_alloc(mp->pool_id, (uint64_t *)obj_table, + n, 0, 1); + + if (unlikely(count != n)) { + /* If bulk alloc failed to allocate all pointers, try + * allocating remaining pointers with the default alloc + * with retry scheme. + */ + if (cnxk_mempool_deq(mp, &obj_table[count], n - count)) { + cn9k_mempool_enq(mp, obj_table, count); + return -ENOENT; + } + } + + return 0; +} + +static int +cn9k_mempool_alloc(struct rte_mempool *mp) +{ + size_t block_size, padding; + + block_size = mp->elt_size + mp->header_size + mp->trailer_size; + /* Align header size to ROC_ALIGN */ + if (mp->header_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(mp->header_size, ROC_ALIGN) - + mp->header_size; + mp->header_size += padding; + block_size += padding; + } + + /* Align block size to ROC_ALIGN */ + if (block_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(block_size, ROC_ALIGN) - block_size; + mp->trailer_size += padding; + block_size += padding; + } + + /* + * OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate + * the set selection. + * Add additional padding to ensure that the element size always + * occupies odd number of cachelines to ensure even distribution + * of elements among L1D cache sets. + */ + padding = ((block_size / ROC_ALIGN) % 2) ? 0 : ROC_ALIGN; + mp->trailer_size += padding; + + return cnxk_mempool_alloc(mp); +} + +static struct rte_mempool_ops cn9k_mempool_ops = { + .name = "cn9k_mempool_ops", + .alloc = cn9k_mempool_alloc, + .free = cnxk_mempool_free, + .enqueue = cn9k_mempool_enq, + .dequeue = cn9k_mempool_deq, + .get_count = cnxk_mempool_get_count, + .calc_mem_size = cnxk_mempool_calc_mem_size, + .populate = cnxk_mempool_populate, +}; + +MEMPOOL_REGISTER_OPS(cn9k_mempool_ops); diff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build index b9a810e021..4ce865e18b 100644 --- a/drivers/mempool/cnxk/meson.build +++ b/drivers/mempool/cnxk/meson.build @@ -14,7 +14,8 @@ if not dpdk_conf.get('RTE_ARCH_64') endif sources = files('cnxk_mempool.c', - 'cnxk_mempool_ops.c') + 'cnxk_mempool_ops.c', + 'cn9k_mempool_ops.c') deps += ['eal', 'mbuf', 'kvargs', 'bus_pci', 'common_cnxk', 'mempool']