diff mbox series

[4/4] net/txgbe: fix the process of adding crypto SA

Message ID 20210304100700.17888-5-jiawenwu@trustnetic.com (mailing list archive)
State Changes Requested, archived
Delegated to: Ferruh Yigit
Headers
Series bug fixes for txgbe |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Functional success Functional Testing PASS
ci/travis-robot success travis build: passed
ci/github-robot success github build: passed
ci/iol-abi-testing success Testing PASS
ci/iol-testing success Testing PASS

Commit Message

Jiawen Wu March 4, 2021, 10:07 a.m. UTC 
  By register definition, Ipsec Rx IPv4 address should to be written
in the reg(0).

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/txgbe/txgbe_ipsec.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/txgbe/txgbe_ipsec.c b/drivers/net/txgbe/txgbe_ipsec.c
index 9f4eee408..a43b95aa2 100644
--- a/drivers/net/txgbe/txgbe_ipsec.c
+++ b/drivers/net/txgbe/txgbe_ipsec.c
@@ -145,11 +145,11 @@  txgbe_crypto_add_sa(struct txgbe_crypto_session *ic_session)
 		reg_val = TXGBE_IPSRXIDX_ENA | TXGBE_IPSRXIDX_WRITE |
 				TXGBE_IPSRXIDX_TB_IP | (ip_index << 3);
 		if (priv->rx_ip_tbl[ip_index].ip.type == IPv4) {
-			wr32(hw, TXGBE_IPSRXADDR(0), 0);
+			uint32_t ipv4 = priv->rx_ip_tbl[ip_index].ip.ipv4;
+			wr32(hw, TXGBE_IPSRXADDR(0), rte_cpu_to_be_32(ipv4));
 			wr32(hw, TXGBE_IPSRXADDR(1), 0);
 			wr32(hw, TXGBE_IPSRXADDR(2), 0);
-			wr32(hw, TXGBE_IPSRXADDR(3),
-					priv->rx_ip_tbl[ip_index].ip.ipv4);
+			wr32(hw, TXGBE_IPSRXADDR(3), 0);
 		} else {
 			wr32(hw, TXGBE_IPSRXADDR(0),
 					priv->rx_ip_tbl[ip_index].ip.ipv6[0]);