From patchwork Tue Mar 2 07:23:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 88351 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 04551A054F; Tue, 2 Mar 2021 08:20:31 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 597B31CC504; Tue, 2 Mar 2021 08:20:22 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 6672B1CC502 for ; Tue, 2 Mar 2021 08:20:20 +0100 (CET) IronPort-SDR: cxg9TGms6lKK8KCgKfcR8VdkwB9iuskyzSYn5TVhL11JbjyOv5yG4aNI2meFeBbTpcR4DujOb/ cf48lieMQkgA== X-IronPort-AV: E=McAfee;i="6000,8403,9910"; a="186775230" X-IronPort-AV: E=Sophos;i="5.81,216,1610438400"; d="scan'208";a="186775230" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2021 23:20:19 -0800 IronPort-SDR: zgu/RshWUSDjamAcYnVZr9FMeUavCYev15bJV3rp24+k1ttzL86a2hbLUD0uswg1mQVLjY95ic lNvclVsd2BVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,216,1610438400"; d="scan'208";a="506230274" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga001.fm.intel.com with ESMTP; 01 Mar 2021 23:20:16 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, haiyue.wang@intel.com, junfeng.guo@intel.com, Qi Zhang , Amir Shay Date: Tue, 2 Mar 2021 15:23:46 +0800 Message-Id: <20210302072357.1657556-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302072357.1657556-1-qi.z.zhang@intel.com> References: <20210302072357.1657556-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 03/14] net/ice/base: post update double reset solution restriction X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add capability which indicates double reset solution restriction. Added "Post-update EMPR enabled" field to "Response Flags" field (byte 19 in the response structure). Signed-off-by: Amir Shay Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 3f2b4cd54b..a31c27a633 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -111,6 +111,7 @@ struct ice_aqc_list_caps_elem { #define ICE_AQC_CAPS_MAX_MTU 0x0047 #define ICE_AQC_CAPS_IWARP 0x0051 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 +#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 u8 major_ver; @@ -1765,6 +1766,7 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ #define ICE_AQC_NVM_PERST_FLAG 1 #define ICE_AQC_NVM_EMPR_FLAG 2 +#define ICE_AQC_NVM_EMPR_ENA BIT(0) __le16 module_typeid; __le16 length; #define ICE_AQC_NVM_ERASE_LEN 0xFFFF