diff mbox series

[v5,08/17] bus/pci: support I/O port operations with musl

Message ID 20210225182250.1149592-9-thomas@monjalon.net (mailing list archive)
State Superseded
Headers show
Series Alpine/musl build support | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Thomas Monjalon Feb. 25, 2021, 6:22 p.m. UTC
From: Natanael Copa <ncopa@alpinelinux.org>

Add a fallback for non-GNU libc systems like musl libc for the
non-standard functions outl_p, outw_p and outb_p.

This solves the following buildtime errors when building with musl libc:
pci_uio.c:(.text+0xaa1): undefined reference to `outw_p'
pci_uio.c:(.text+0xac5): undefined reference to `outl_p'
pci_uio.c:(.text+0xadf): undefined reference to `outb_p'

The non-x86 case are handled with macros to factor out various ifdefs.

Bugzilla ID: 35
Fixes: 756ce64b1ecd ("eal: introduce PCI ioport API")
Cc: stable@dpdk.org

Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
---
 drivers/bus/pci/linux/pci_uio.c | 91 ++++++++++++++++++++++-----------
 1 file changed, 61 insertions(+), 30 deletions(-)
diff mbox series

Patch

diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c
index f3305a2f28..1294f505be 100644
--- a/drivers/bus/pci/linux/pci_uio.c
+++ b/drivers/bus/pci/linux/pci_uio.c
@@ -489,6 +489,16 @@  pci_uio_ioport_map(struct rte_pci_device *dev, int bar,
 }
 #endif
 
+#ifdef RTE_ARCH_X86
+#define pci_uio_inl(reg) inl(reg)
+#define pci_uio_inw(reg) inw(reg)
+#define pci_uio_inb(reg) inb(reg)
+#else /* !RTE_ARCH_X86 */
+#define pci_uio_inl(reg) (*(volatile uint32_t *)(reg))
+#define pci_uio_inw(reg) (*(volatile uint16_t *)(reg))
+#define pci_uio_inb(reg) (*(volatile uint8_t *)(reg))
+#endif
+
 void
 pci_uio_ioport_read(struct rte_pci_ioport *p,
 		    void *data, size_t len, off_t offset)
@@ -500,29 +510,62 @@  pci_uio_ioport_read(struct rte_pci_ioport *p,
 	for (d = data; len > 0; d += size, reg += size, len -= size) {
 		if (len >= 4) {
 			size = 4;
-#if defined(RTE_ARCH_X86)
-			*(uint32_t *)d = inl(reg);
-#else
-			*(uint32_t *)d = *(volatile uint32_t *)reg;
-#endif
+			*(uint32_t *)d = pci_uio_inl(reg);
 		} else if (len >= 2) {
 			size = 2;
-#if defined(RTE_ARCH_X86)
-			*(uint16_t *)d = inw(reg);
-#else
-			*(uint16_t *)d = *(volatile uint16_t *)reg;
-#endif
+			*(uint16_t *)d = pci_uio_inw(reg);
 		} else {
 			size = 1;
-#if defined(RTE_ARCH_X86)
-			*d = inb(reg);
-#else
-			*d = *(volatile uint8_t *)reg;
-#endif
+			*d = pci_uio_inb(reg);
 		}
 	}
 }
 
+#ifdef RTE_ARCH_X86
+static inline void
+pci_uio_outl_p(unsigned int value, unsigned short int port)
+{
+#ifdef __GLIBC__
+	outl_p(value, port);
+#else
+	__asm__ __volatile__ ("outl %0,%w1\noutb %%al,$0x80" : : "a" (value),
+			      "Nd" (port));
+#endif
+}
+#else /* !RTE_ARCH_X86 */
+#define pci_uio_outl_p(value, reg) (*(volatile uint32_t *)(reg) = (value))
+#endif
+
+#ifdef RTE_ARCH_X86
+static inline void
+pci_uio_outw_p(unsigned short int value, unsigned short int port)
+{
+#ifdef __GLIBC__
+	outw_p(value, port);
+#else
+	__asm__ __volatile__ ("outw %w0,%w1\noutb %%al,$0x80" : : "a" (value),
+			      "Nd" (port));
+#endif
+}
+#else /* !RTE_ARCH_X86 */
+#define pci_uio_outw_p(value, reg) (*(volatile uint16_t *)(reg) = (value))
+#endif
+
+#ifdef RTE_ARCH_X86
+static inline void
+pci_uio_outb_p(unsigned char value, unsigned short int port)
+{
+#ifdef __GLIBC__
+	outb_p(value, port);
+#else
+	__asm__ __volatile__ ("outb %b0,%w1\noutb %%al,$0x80" : : "a" (value),
+			      "Nd" (port));
+#endif
+}
+#else /* !RTE_ARCH_X86 */
+#define pci_uio_outb_p(value, reg) (*(volatile uint8_t *)(reg) = (value))
+#endif
+
 void
 pci_uio_ioport_write(struct rte_pci_ioport *p,
 		     const void *data, size_t len, off_t offset)
@@ -534,25 +577,13 @@  pci_uio_ioport_write(struct rte_pci_ioport *p,
 	for (s = data; len > 0; s += size, reg += size, len -= size) {
 		if (len >= 4) {
 			size = 4;
-#if defined(RTE_ARCH_X86)
-			outl_p(*(const uint32_t *)s, reg);
-#else
-			*(volatile uint32_t *)reg = *(const uint32_t *)s;
-#endif
+			pci_uio_outl_p(*(const uint32_t *)s, reg);
 		} else if (len >= 2) {
 			size = 2;
-#if defined(RTE_ARCH_X86)
-			outw_p(*(const uint16_t *)s, reg);
-#else
-			*(volatile uint16_t *)reg = *(const uint16_t *)s;
-#endif
+			pci_uio_outw_p(*(const uint16_t *)s, reg);
 		} else {
 			size = 1;
-#if defined(RTE_ARCH_X86)
-			outb_p(*s, reg);
-#else
-			*(volatile uint8_t *)reg = *s;
-#endif
+			pci_uio_outb_p(*s, reg);
 		}
 	}
 }