[v1] net/ice: fix QinQ switch rule input set mask

Message ID 20210204060751.515216-1-yuying.zhang@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Qi Zhang
Headers
Series [v1] net/ice: fix QinQ switch rule input set mask |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Functional success Functional Testing PASS
ci/intel-Testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/travis-robot warning Travis build: failed
ci/iol-testing warning Testing issues

Commit Message

Zhang, Yuying Feb. 4, 2021, 6:07 a.m. UTC
  QinQ switch rule doesn't support ethertype field match.
QinQ ethertype pattern should not be created. Change the
input set mask to fix the issue.

Fixes: bb3386f348dd ("net/ice: enable QinQ filter for switch")

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
---
 drivers/net/ice/ice_switch_filter.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
  

Comments

Qi Zhang Feb. 4, 2021, 8:06 a.m. UTC | #1
> -----Original Message-----
> From: Zhang, Yuying <yuying.zhang@intel.com>
> Sent: Thursday, February 4, 2021 2:08 PM
> To: dev@dpdk.org; Zhang, Qi Z <qi.z.zhang@intel.com>; Wang, Haiyue
> <haiyue.wang@intel.com>
> Cc: Fu, Qi <qi.fu@intel.com>; Zhang, Yuying <yuying.zhang@intel.com>
> Subject: [PATCH v1] net/ice: fix QinQ switch rule input set mask
> 
> QinQ switch rule doesn't support ethertype field match.
> QinQ ethertype pattern should not be created. Change the input set mask to
> fix the issue.
> 
> Fixes: bb3386f348dd ("net/ice: enable QinQ filter for switch")
> 
> Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>

Acked-by: Qi Zhang <qi.z.zhang@intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi
  

Patch

diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c
index 5ca0985e21..6525e6c115 100644
--- a/drivers/net/ice/ice_switch_filter.c
+++ b/drivers/net/ice/ice_switch_filter.c
@@ -38,7 +38,8 @@ 
 	ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE | \
 	ICE_INSET_VLAN_INNER)
 #define ICE_SW_INSET_MAC_QINQ  ( \
-	ICE_SW_INSET_MAC_VLAN | ICE_INSET_VLAN_OUTER)
+	ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_VLAN_INNER | \
+	ICE_INSET_VLAN_OUTER)
 #define ICE_SW_INSET_MAC_IPV4 ( \
 	ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \
 	ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS)