From patchwork Fri Jan 29 12:45:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pradeep Nalla X-Patchwork-Id: 87544 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 340DBA09E4; Fri, 29 Jan 2021 13:46:00 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE403240205; Fri, 29 Jan 2021 13:45:25 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id EBF792401EC for ; Fri, 29 Jan 2021 13:45:17 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10TCZgkf024583; Fri, 29 Jan 2021 04:45:17 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=7ANs7J0Zb3aPvzJhX8cl7u6P39I5+P8UPDvHmgEd/Tg=; b=KUDmgsUPD3vi+FfvJZTn3NsMVNAlveskaTZxI80+WTFHkzazUDhy746v/DunJbJJb9UK f3ScQTXmb+Ks8ijLEuW3naEHePQr4Rcl0Twxg4navZHs4Y+ua3/Sp3rTfxq9qzTxsKth uWZmcgOccDFOzwAh+wbl+q4gDAIzh1pCIFrTEsmO4crjZLAvbVi2uxnLQLH8DGERSw8Z rsGOYjxQcq5y363/8RLJhm/T90dUA9OIea1l2sMIC3vdcLziNcduwQ4YU29BntpZGGil YrS8k7cpeuBqpNFRJMIuE4UNwSEOzf3tBasBzXK8dpScVWY+3EhVdEjSu4BlUfapAe0A Bg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 36b1xpqw4t-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 29 Jan 2021 04:45:17 -0800 Received: from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 Jan 2021 04:45:15 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 Jan 2021 04:45:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 29 Jan 2021 04:45:14 -0800 Received: from sburla-PowerEdge-T630.caveonetworks.com (unknown [10.106.27.217]) by maili.marvell.com (Postfix) with ESMTP id E4B2E3F703F; Fri, 29 Jan 2021 04:45:13 -0800 (PST) From: Nalla Pradeep To: Nalla Pradeep , Radha Mohan Chintakuntla , Veerasenareddy Burru , "Anatoly Burakov" CC: , , Date: Fri, 29 Jan 2021 04:45:02 -0800 Message-ID: <20210129124510.12158-5-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210129001640.1251-1-pnalla@marvell.com> References: <20210129001640.1251-1-pnalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-01-29_05:2021-01-28, 2021-01-29 signatures=0 Subject: [dpdk-dev] [PATCH v7 04/12] net/octeontx_ep: add device init and uninit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add basic init and uninit function which includes initializing fields of ethdev private structure. Signed-off-by: Nalla Pradeep --- drivers/net/octeontx_ep/otx_ep_common.h | 22 +++++++- drivers/net/octeontx_ep/otx_ep_ethdev.c | 72 +++++++++++++++++++++++-- 2 files changed, 88 insertions(+), 6 deletions(-) diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index 35ea99a79..9bf14540b 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -4,11 +4,31 @@ #ifndef _OTX_EP_COMMON_H_ #define _OTX_EP_COMMON_H_ +#define otx_ep_info(fmt, args...) \ + rte_log(RTE_LOG_INFO, otx_net_ep_logtype, \ + "%s():%u " fmt "\n", \ + __func__, __LINE__, ##args) + +#define otx_ep_err(fmt, args...) \ + rte_log(RTE_LOG_ERR, otx_net_ep_logtype, \ + "%s():%u " fmt "\n", \ + __func__, __LINE__, ##args) + +#define otx_ep_dbg(fmt, args...) \ + rte_log(RTE_LOG_DEBUG, otx_net_ep_logtype, \ + "%s():%u " fmt "\n", \ + __func__, __LINE__, ##args) + /* OTX_EP EP VF device data structure */ struct otx_ep_device { /* PCI device pointer */ struct rte_pci_device *pdev; - + uint16_t chip_id; struct rte_eth_dev *eth_dev; + int port_id; + /* Memory mapped h/w address */ + uint8_t *hw_addr; }; + +extern int otx_net_ep_logtype; #endif /* _OTX_EP_COMMON_H_ */ diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index 607f9c15b..c672021e8 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -8,20 +8,81 @@ #include "otx_ep_common.h" #include "otx_ep_vf.h" +#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private) static int -otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev) +otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) { - RTE_SET_USED(eth_dev); + struct rte_pci_device *pdev = otx_epvf->pdev; + uint32_t dev_id = pdev->id.device_id; + int ret = 0; - return -ENODEV; + switch (dev_id) { + case PCI_DEVID_OCTEONTX_EP_VF: + otx_epvf->chip_id = dev_id; + break; + case PCI_DEVID_OCTEONTX2_EP_NET_VF: + case PCI_DEVID_CN98XX_EP_NET_VF: + otx_epvf->chip_id = dev_id; + break; + default: + otx_ep_err("Unsupported device\n"); + ret = -EINVAL; + } + + if (!ret) + otx_ep_info("OTX_EP dev_id[%d]\n", dev_id); + + return ret; +} + +/* OTX_EP VF device initialization */ +static int +otx_epdev_init(struct otx_ep_device *otx_epvf) +{ + int ret = 0; + + ret = otx_ep_chip_specific_setup(otx_epvf); + if (ret) { + otx_ep_err("Chip specific setup failed\n"); + goto setup_fail; + } + +setup_fail: + return ret; +} + +static int +otx_ep_eth_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev) +{ + return 0; } static int otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) { - RTE_SET_USED(eth_dev); + struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + struct rte_ether_addr vf_mac_addr; + + /* Single process support */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + otx_epvf->eth_dev = eth_dev; + otx_epvf->port_id = eth_dev->data->port_id; + eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0); + if (eth_dev->data->mac_addrs == NULL) { + otx_ep_err("MAC addresses memory allocation failed\n"); + return -ENOMEM; + } + rte_eth_random_addr(vf_mac_addr.addr_bytes); + rte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs); + otx_epvf->hw_addr = pdev->mem_resource[0].addr; + otx_epvf->pdev = pdev; + + otx_epdev_init(otx_epvf); - return -ENODEV; + return 0; } static int @@ -58,3 +119,4 @@ static struct rte_pci_driver rte_otx_ep_pmd = { RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map); RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, "* igb_uio | vfio-pci"); +RTE_LOG_REGISTER(otx_net_ep_logtype, pmd.net.octeontx_ep, NOTICE);