[v6,04/12] net/octeontx_ep: add device init and uninit
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Commit Message
Add basic init and uninit function which includes
initializing fields of ethdev private structure.
Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
---
drivers/net/octeontx_ep/otx_ep_common.h | 24 +++++++-
drivers/net/octeontx_ep/otx_ep_ethdev.c | 75 +++++++++++++++++++++++--
2 files changed, 93 insertions(+), 6 deletions(-)
Comments
On 1/29/2021 12:16 AM, Nalla Pradeep wrote:
> Add basic init and uninit function which includes
> initializing fields of ethdev private structure.
>
> Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
<...>
> @@ -43,6 +104,7 @@ otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
> /* Set of PCI devices this driver supports */
> static const struct rte_pci_id pci_id_otx_ep_map[] = {
> { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) },
> + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_EP_NET_VF) },
Can you please move this to 3/12 where 'pci_id_otx_ep_map' is introduced?
> { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },
> { .vendor_id = 0, /* sentinel */ }
> };
> @@ -57,3 +119,6 @@ static struct rte_pci_driver rte_otx_ep_pmd = {
> RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd);
> RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map);
> RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, "* igb_uio | vfio-pci");
> +RTE_LOG_REGISTER(otx_net_ep_logdbg, pmd.net.octeontx_ep, DEBUG);
> +RTE_LOG_REGISTER(otx_net_ep_logerr, pmd.net.octeontx_ep, ERR);
> +RTE_LOG_REGISTER(otx_net_ep_loginfo, pmd.net.octeontx_ep, INFO);
>
This is wrong. You should register single logtype, as done in v5, and use for
various log levels.
Please make the default log level for registered logtype 'NOTICE' (again as done
in v5)
The macros 'otx_ep_info', 'otx_ep_err' & 'otx_ep_dbg' should share same logtype.
@@ -4,11 +4,33 @@
#ifndef _OTX_EP_COMMON_H_
#define _OTX_EP_COMMON_H_
+#define otx_ep_info(fmt, args...) \
+ rte_log(RTE_LOG_DEBUG, otx_net_ep_loginfo, \
+ "%s():%u " fmt "\n", \
+ __func__, __LINE__, ##args)
+
+#define otx_ep_err(fmt, args...) \
+ rte_log(RTE_LOG_DEBUG, otx_net_ep_logerr, \
+ "%s():%u " fmt "\n", \
+ __func__, __LINE__, ##args)
+
+#define otx_ep_dbg(fmt, args...) \
+ rte_log(RTE_LOG_DEBUG, otx_net_ep_logdbg, \
+ "%s():%u " fmt "\n", \
+ __func__, __LINE__, ##args)
+
/* OTX_EP EP VF device data structure */
struct otx_ep_device {
/* PCI device pointer */
struct rte_pci_device *pdev;
-
+ uint16_t chip_id;
struct rte_eth_dev *eth_dev;
+ int port_id;
+ /* Memory mapped h/w address */
+ uint8_t *hw_addr;
};
+
+extern int otx_net_ep_logdbg;
+extern int otx_net_ep_logerr;
+extern int otx_net_ep_loginfo;
#endif /* _OTX_EP_COMMON_H_ */
@@ -8,20 +8,81 @@
#include "otx_ep_common.h"
#include "otx_ep_vf.h"
+#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)
static int
-otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)
+otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
{
- RTE_SET_USED(eth_dev);
+ struct rte_pci_device *pdev = otx_epvf->pdev;
+ uint32_t dev_id = pdev->id.device_id;
+ int ret = 0;
- return -ENODEV;
+ switch (dev_id) {
+ case PCI_DEVID_OCTEONTX_EP_VF:
+ otx_epvf->chip_id = dev_id;
+ break;
+ case PCI_DEVID_OCTEONTX2_EP_NET_VF:
+ case PCI_DEVID_CN98XX_EP_NET_VF:
+ otx_epvf->chip_id = dev_id;
+ break;
+ default:
+ otx_ep_err("Unsupported device\n");
+ ret = -EINVAL;
+ }
+
+ if (!ret)
+ otx_ep_info("OTX_EP dev_id[%d]\n", dev_id);
+
+ return ret;
+}
+
+/* OTX_EP VF device initialization */
+static int
+otx_epdev_init(struct otx_ep_device *otx_epvf)
+{
+ int ret = 0;
+
+ ret = otx_ep_chip_specific_setup(otx_epvf);
+ if (ret) {
+ otx_ep_err("Chip specific setup failed\n");
+ goto setup_fail;
+ }
+
+setup_fail:
+ return ret;
+}
+
+static int
+otx_ep_eth_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev)
+{
+ return 0;
}
static int
otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
{
- RTE_SET_USED(eth_dev);
+ struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
+ struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
+ struct rte_ether_addr vf_mac_addr;
+
+ /* Single process support */
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ otx_epvf->eth_dev = eth_dev;
+ otx_epvf->port_id = eth_dev->data->port_id;
+ eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0);
+ if (eth_dev->data->mac_addrs == NULL) {
+ otx_ep_err("MAC addresses memory allocation failed\n");
+ return -ENOMEM;
+ }
+ rte_eth_random_addr(vf_mac_addr.addr_bytes);
+ rte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs);
+ otx_epvf->hw_addr = pdev->mem_resource[0].addr;
+ otx_epvf->pdev = pdev;
+
+ otx_epdev_init(otx_epvf);
- return -ENODEV;
+ return 0;
}
static int
@@ -43,6 +104,7 @@ otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
/* Set of PCI devices this driver supports */
static const struct rte_pci_id pci_id_otx_ep_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_EP_NET_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },
{ .vendor_id = 0, /* sentinel */ }
};
@@ -57,3 +119,6 @@ static struct rte_pci_driver rte_otx_ep_pmd = {
RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map);
RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, "* igb_uio | vfio-pci");
+RTE_LOG_REGISTER(otx_net_ep_logdbg, pmd.net.octeontx_ep, DEBUG);
+RTE_LOG_REGISTER(otx_net_ep_logerr, pmd.net.octeontx_ep, ERR);
+RTE_LOG_REGISTER(otx_net_ep_loginfo, pmd.net.octeontx_ep, INFO);