From patchwork Fri Jan 22 19:19:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 87143 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6542A0A0A; Fri, 22 Jan 2021 20:23:58 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 38935141179; Fri, 22 Jan 2021 20:20:52 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 037B3141173 for ; Fri, 22 Jan 2021 20:20:49 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10MJBDom016553 for ; Fri, 22 Jan 2021 11:20:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=sPHyNj44uDF/aXOrNPi1dO2Zy5VLCwv3BQAtak6O8ho=; b=eTDJx5Shq7TXDdLESvTQyAMMOSi8sB1jwTWwsdVsf74LDOYCbJ1d1N0XvkG3Je37q//6 Wf3spaoWF7o7wvP/oemTh2XAJhUkfXNcoYkuXrHFGZH+PFGWaYz3/WRV5IPJCVBvkeMs Sa8Q2/hcNbzdDn0saTvVxAYiCbGUjGwSwcBseErwACWemxR2MxK6AZzsco+cN3XKh0Jh S+80yG3FHT6yZXlY89WoOiU198/ElDlOnH0ovljgIiAJHP8lrpC66F/5V7z7u7b0X73X jwomaN23i5YzrKlJPpVdbrL1+QtWEirMSYDIwbXJfO3W7j7YL64zLdBuT5sAhbvq7whi 2Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3668p7tph4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 22 Jan 2021 11:20:49 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Jan 2021 11:20:47 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Jan 2021 11:20:46 -0800 From: To: CC: , Dana Vardi , Liron Himi Date: Fri, 22 Jan 2021 21:19:20 +0200 Message-ID: <20210122191925.24308-33-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210122191925.24308-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> <20210122191925.24308-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-22_14:2021-01-22, 2021-01-22 signatures=0 Subject: [dpdk-dev] [PATCH v2 32/37] net/mvpp2: update start hdr name X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dana Vardi Change 'dsa_mode' to 'start_hdr' in config file Signed-off-by: Dana Vardi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_qos.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index a3add540b..e420c0cbc 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -20,9 +20,10 @@ /* Parsing tokens. Defined conveniently, so that any correction is easy. */ #define MRVL_TOK_DEFAULT "default" #define MRVL_TOK_DSA_MODE "dsa_mode" -#define MRVL_TOK_DSA_MODE_NONE "none" -#define MRVL_TOK_DSA_MODE_DSA "dsa" -#define MRVL_TOK_DSA_MODE_EXT_DSA "ext_dsa" +#define MRVL_TOK_START_HDR "start_hdr" +#define MRVL_TOK_START_HDR_NONE "none" +#define MRVL_TOK_START_HDR_DSA "dsa" +#define MRVL_TOK_START_HDR_EXT_DSA "ext_dsa" #define MRVL_TOK_DEFAULT_TC "default_tc" #define MRVL_TOK_DSCP "dscp" #define MRVL_TOK_MAPPING_PRIORITY "mapping_priority" @@ -722,25 +723,33 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) continue; } + /* MRVL_TOK_START_HDR replaces MRVL_TOK_DSA_MODE parameter. + * MRVL_TOK_DSA_MODE will be supported for backward + * compatibillity. + */ entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_START_HDR); + /* if start_hsr is missing, check if dsa_mode exist instead */ + if (entry == NULL) + entry = rte_cfgfile_get_entry(file, sec_name, MRVL_TOK_DSA_MODE); if (entry) { - if (!strncmp(entry, MRVL_TOK_DSA_MODE_NONE, - sizeof(MRVL_TOK_DSA_MODE_NONE))) + if (!strncmp(entry, MRVL_TOK_START_HDR_NONE, + sizeof(MRVL_TOK_START_HDR_NONE))) (*cfg)->port[n].eth_start_hdr = PP2_PPIO_HDR_ETH; - else if (!strncmp(entry, MRVL_TOK_DSA_MODE_DSA, - sizeof(MRVL_TOK_DSA_MODE_DSA))) + else if (!strncmp(entry, MRVL_TOK_START_HDR_DSA, + sizeof(MRVL_TOK_START_HDR_DSA))) (*cfg)->port[n].eth_start_hdr = PP2_PPIO_HDR_ETH_DSA; - else if (!strncmp(entry, MRVL_TOK_DSA_MODE_EXT_DSA, - sizeof(MRVL_TOK_DSA_MODE_EXT_DSA))) { + else if (!strncmp(entry, MRVL_TOK_START_HDR_EXT_DSA, + sizeof(MRVL_TOK_START_HDR_EXT_DSA))) { (*cfg)->port[n].eth_start_hdr = PP2_PPIO_HDR_ETH_EXT_DSA; } else { MRVL_LOG(ERR, "Error in parsing %s value (%s)!\n", - MRVL_TOK_DSA_MODE, entry); + MRVL_TOK_START_HDR, entry); return -1; } } else {