From patchwork Fri Jan 22 19:19:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 87140 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 88341A0A0A; Fri, 22 Jan 2021 20:23:37 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 62281141165; Fri, 22 Jan 2021 20:20:47 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C739A14115B for ; Fri, 22 Jan 2021 20:20:44 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10MJBKw9016567 for ; Fri, 22 Jan 2021 11:20:44 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=LiVypZrURQ/quUS4Fqk7Ya2r48t4Y8ICMkhinMXI25k=; b=YOdzOJL8sJOCJnS/y6U+E3MZnWDPzbfWvsm1PBN0n1NLZP/NUQcXKRYnzKV3p+7P8sv4 KqAXhDgT+DpweRByJ5u1qZQ3upxcBhaJInq8ZwndliFeb1lxWXeJImMp8PLJ10+4rPKY 6EgPCp5KqX5PnpnIrNfhZ7hnIqZx2fqkGFc6DV6AEToiZcHjYEskyVkD4EG2wDjuc1Tx jmdU+9j2fp+GzF+QSzGFPmkH0qWEU87ooDyGwSvShhdV4/N6xqUPJr5ZfDlLSsQDFd1b IEfCL92YGlPwNkUHUNe0zD+82OB66Lqti9sPiRDC0BT3/EYG3vyqrljqurgYlfdTEYBW Hw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3668p7tpgq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 22 Jan 2021 11:20:44 -0800 Received: from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Jan 2021 11:20:42 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Jan 2021 11:20:41 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Jan 2021 11:20:40 -0800 From: To: CC: , Liron Himi , Yuri Chipchev Date: Fri, 22 Jan 2021 21:19:17 +0200 Message-ID: <20210122191925.24308-30-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210122191925.24308-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> <20210122191925.24308-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-22_14:2021-01-22, 2021-01-22 signatures=0 Subject: [dpdk-dev] [PATCH v2 29/37] net/mvpp2: expose max MTU size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi Expose max-MTU based on the max frame size that l4 checksum generation can be done by HW. Signed-off-by: Liron Himi Reviewed-by: Yuri Chipchev --- drivers/net/mvpp2/mrvl_ethdev.c | 24 ++++++++++++++++++++++-- drivers/net/mvpp2/mrvl_ethdev.h | 1 + 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 037125497..41971394d 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -499,9 +499,17 @@ mrvl_dev_configure(struct rte_eth_dev *dev) return -EINVAL; } - if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - MRVL_PP2_ETH_HDRS_LEN; + if (dev->data->mtu > priv->max_mtu) { + MRVL_LOG(ERR, "inherit MTU %u from max_rx_pkt_len %u is larger than max_mtu %u\n", + dev->data->mtu, + dev->data->dev_conf.rxmode.max_rx_pkt_len, + priv->max_mtu); + return -EINVAL; + } + } if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) priv->multiseg = 1; @@ -1686,9 +1694,11 @@ mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, * Info structure output buffer. */ static int -mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, +mrvl_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) { + struct mrvl_priv *priv = dev->data->dev_private; + info->speed_capa = ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | @@ -1720,6 +1730,7 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, info->default_rxconf.rx_drop_en = 1; info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; + info->max_mtu = priv->max_mtu; return 0; } @@ -3118,6 +3129,7 @@ mrvl_priv_create(const char *dev_name) struct pp2_bpool_params bpool_params; char match[MRVL_MATCH_LEN]; struct mrvl_priv *priv; + uint16_t max_frame_size; int ret, bpool_bit; priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); @@ -3129,6 +3141,14 @@ mrvl_priv_create(const char *dev_name) if (ret) goto out_free_priv; + ret = pp2_ppio_get_l4_cksum_max_frame_size(priv->pp_id, priv->ppio_id, + &max_frame_size); + if (ret) + goto out_free_priv; + + priv->max_mtu = max_frame_size + RTE_ETHER_CRC_LEN - + MRVL_PP2_ETH_HDRS_LEN; + bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], PP2_BPOOL_NUM_POOLS); if (bpool_bit < 0) diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index b0cdddd15..42b0cc053 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -159,6 +159,7 @@ struct mrvl_priv { uint8_t uc_mc_flushed; uint8_t isolated; uint8_t multiseg; + uint16_t max_mtu; struct pp2_ppio_params ppio_params; struct pp2_cls_qos_tbl_params qos_tbl_params;