From patchwork Mon Jan 18 20:35:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86831 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 471D9A0A03; Mon, 18 Jan 2021 21:36:53 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E3718140E9B; Mon, 18 Jan 2021 21:35:55 +0100 (CET) Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) by mails.dpdk.org (Postfix) with ESMTP id D7BF8140EA3 for ; Mon, 18 Jan 2021 21:35:53 +0100 (CET) Received: by mail-pg1-f177.google.com with SMTP id n25so11658770pgb.0 for ; Mon, 18 Jan 2021 12:35:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eZHLIajdEoFA3Nym+Z5BFhCDgWh82946qXblVzvYSvA=; b=x9YCfjcT/W/SWF9m2z/JA+OtaxInk4dJFRZcaWSypXy0A3DTfRviogk/7gqaUMy/Bz Iy2DcZM5j6Dn5gUmQ0Na30cXaDW6U7VG/59V5geLt/DwYPXE8lDSiEaIxD8rbZxCXqn4 zHB2magFPL3tTqXpX6XI+MR/c/HiZYs9r3+TAAQHaqBtM9zxw5M6CuRom8ozd74HOGtU gPqP0PQ1JfITbYS+OjBmOY+PoWNoKzdNwmvNaeCJlajl1snu2CJv6BN+r8Uf0YaaqY/G z1Cz5gZ2s3pX5Gvkro/c/bTiNYZywVlq1zQKucwHiytWaSyJMafvUtdxrFlcMvCiwITJ Trrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eZHLIajdEoFA3Nym+Z5BFhCDgWh82946qXblVzvYSvA=; b=Dl2bcp2eFyg/N70DHuS9uLdD0gjdBKywpRzEHix2H4R0ILMonoO/iDsL90NAodv5FV mph179vj95OiqRB6EGTuorAyBm63doXYJGQgI4rCHllDUKrz5nr7wd/L3QiL/CdbOjOW kMP0cuftM97nJ/HL4Ek8naX4d5hxEKCAJhYt/Y4sLsCw5FZlrH+TorG1UBKjrCh7jSwB eiC3niZmLQTWXk/mpjlOnKkNKjqModyJJioL0go6ef/saeb11aP3iTcZb8wRI4BLKHt3 FKzQIjijEr2dIaHT7YdjPjyqD6nV2tN7ESvq8HDZk9dMHuTuGE4o2rCvU1RZwYFzqKSh Cc3A== X-Gm-Message-State: AOAM530UaGPuUAw/pv+qvra4Cwcbr9BE1Wzam/lhowU8v5IeW36mWnXN AGW3Mih1KPrQIcDFO9psFuZWErBVbD5rvw== X-Google-Smtp-Source: ABdhPJzBX6cu2n6tMwsZOz8w65SsdxnNQmH71sv5H9lStBhB/BGiRBj5DqDAKBtu4nytpuBBLD2UgA== X-Received: by 2002:a62:b60c:0:b029:1ae:6d91:4eb6 with SMTP id j12-20020a62b60c0000b02901ae6d914eb6mr1158160pff.33.1611002152897; Mon, 18 Jan 2021 12:35:52 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:52 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:35:06 -0800 Message-Id: <20210118203508.1332-12-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 11/13] net/ionic: convert per-queue offloads into queue flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This will conserve resources by reducing struct ionic_qcq. Saving a cacheline or two in the rxq and txq structs helps when running in embedded configurations where CPU cache space is at a premium. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_lif.h | 4 +++- drivers/net/ionic/ionic_rxtx.c | 35 +++++++++++++++++++--------------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h index bf5637afce..8f01aefd60 100644 --- a/drivers/net/ionic/ionic_lif.h +++ b/drivers/net/ionic/ionic_lif.h @@ -49,10 +49,12 @@ struct ionic_rx_stats { #define IONIC_QCQ_F_INITED BIT(0) #define IONIC_QCQ_F_SG BIT(1) #define IONIC_QCQ_F_DEFERRED BIT(4) +#define IONIC_QCQ_F_CSUM_L3 BIT(7) +#define IONIC_QCQ_F_CSUM_UDP BIT(8) +#define IONIC_QCQ_F_CSUM_TCP BIT(9) /* Queue / Completion Queue */ struct ionic_qcq { - uint64_t offloads; struct ionic_queue q; /**< Queue */ struct ionic_cq cq; /**< Completion Queue */ struct ionic_lif *lif; /**< LIF */ diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index d0f8954753..918701f463 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -63,7 +63,7 @@ ionic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct ionic_queue *q = &txq->q; qinfo->nb_desc = q->num_descs; - qinfo->conf.offloads = txq->offloads; + qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads; qinfo->conf.tx_deferred_start = txq->flags & IONIC_QCQ_F_DEFERRED; } @@ -200,7 +200,13 @@ ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id, if (tx_conf->tx_deferred_start) txq->flags |= IONIC_QCQ_F_DEFERRED; - txq->offloads = offloads; + /* Convert the offload flags into queue flags */ + if (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) + txq->flags |= IONIC_QCQ_F_CSUM_L3; + if (offloads & DEV_TX_OFFLOAD_TCP_CKSUM) + txq->flags |= IONIC_QCQ_F_CSUM_TCP; + if (offloads & DEV_TX_OFFLOAD_UDP_CKSUM) + txq->flags |= IONIC_QCQ_F_CSUM_UDP; eth_dev->data->tx_queues[tx_queue_id] = txq; @@ -320,9 +326,10 @@ ionic_tx_tso_next(struct ionic_queue *q, struct ionic_txq_sg_elem **elem) } static int -ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm, - uint64_t offloads __rte_unused, bool not_xmit_more) +ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm, + bool not_xmit_more) { + struct ionic_queue *q = &txq->q; struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q); struct ionic_txq_desc *desc; struct ionic_txq_sg_elem *elem; @@ -442,9 +449,10 @@ ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm, } static int -ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm, - uint64_t offloads, bool not_xmit_more) +ionic_tx(struct ionic_qcq *txq, struct rte_mbuf *txm, + bool not_xmit_more) { + struct ionic_queue *q = &txq->q; struct ionic_txq_desc *desc_base = q->base; struct ionic_txq_sg_desc_v1 *sg_desc_base = q->sg_base; struct ionic_txq_desc *desc = &desc_base[q->head_idx]; @@ -460,15 +468,15 @@ ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm, uint8_t flags = 0; if ((ol_flags & PKT_TX_IP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) { + (txq->flags & IONIC_QCQ_F_CSUM_L3)) { opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3; } if (((ol_flags & PKT_TX_TCP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) || + (txq->flags & IONIC_QCQ_F_CSUM_TCP)) || ((ol_flags & PKT_TX_UDP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) { + (txq->flags & IONIC_QCQ_F_CSUM_UDP))) { opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; } @@ -536,10 +544,9 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, } if (tx_pkts[nb_tx]->ol_flags & PKT_TX_TCP_SEG) - err = ionic_tx_tso(q, tx_pkts[nb_tx], txq->offloads, - last); + err = ionic_tx_tso(txq, tx_pkts[nb_tx], last); else - err = ionic_tx(q, tx_pkts[nb_tx], txq->offloads, last); + err = ionic_tx(txq, tx_pkts[nb_tx], last); if (err) { stats->drop += nb_pkts - nb_tx; if (nb_tx > 0) @@ -621,7 +628,7 @@ ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, qinfo->scattered_rx = dev->data->scattered_rx; qinfo->nb_desc = q->num_descs; qinfo->conf.rx_deferred_start = rxq->flags & IONIC_QCQ_F_DEFERRED; - qinfo->conf.offloads = rxq->offloads; + qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; } static void __rte_cold @@ -724,8 +731,6 @@ ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, if (rx_conf->rx_deferred_start) rxq->flags |= IONIC_QCQ_F_DEFERRED; - rxq->offloads = offloads; - eth_dev->data->rx_queues[rx_queue_id] = rxq; return 0;