[v2,05/11] net/octeontx_ep: Add dev info get and configure
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Commit Message
Add device information get and device configure operations.
Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
---
drivers/net/octeontx_ep/otx_ep_common.h | 16 +++++
drivers/net/octeontx_ep/otx_ep_ethdev.c | 89 ++++++++++++++++++++++++-
drivers/net/octeontx_ep/otx_ep_rxtx.h | 10 +++
3 files changed, 112 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/octeontx_ep/otx_ep_rxtx.h
Comments
On 1/18/2021 9:35 AM, Nalla Pradeep wrote:
> Add device information get and device configure operations.
>
> Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
<...>
> +static int
> +otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,
> + struct rte_eth_dev_info *devinfo)
> +{
> + struct otx_ep_device *otx_epvf;
> + struct rte_pci_device *pdev;
> + uint32_t dev_id;
> +
> + otx_epvf = OTX_EP_DEV(eth_dev);
> + pdev = otx_epvf->pdev;
> + dev_id = pdev->id.device_id;
> +
> + devinfo->speed_capa = ETH_LINK_SPEED_10G;
Is it always 10G independent from the device type and PHY?
Also can you please update the featutes file, octeontx_ep.ini, as the same patch
features are added.
For example the 'Speed capabilities' feature can be set as P (partially
supported) with this patch.
> + devinfo->max_rx_queues = otx_epvf->max_rx_queues;
> + devinfo->max_tx_queues = otx_epvf->max_tx_queues;
> +
> + devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;
> + if (dev_id == PCI_DEVID_OCTEONTX_EP_VF ||
> + dev_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||
> + dev_id == PCI_DEVID_CN98XX_EP_NET_VF) {
> + devinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;
> + devinfo->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME;
> + devinfo->rx_offload_capa |= DEV_RX_OFFLOAD_SCATTER;
> + devinfo->tx_offload_capa = DEV_TX_OFFLOAD_MULTI_SEGS;
> + }
The above list seems all the devices this driver probes, is there a reason to
check for them?
<...>
> +static int
> +otx_ep_dev_configure(struct rte_eth_dev *eth_dev)
> +{
> + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
> + struct rte_eth_dev_data *data = eth_dev->data;
> + struct rte_eth_rxmode *rxmode;
> + struct rte_eth_txmode *txmode;
> + struct rte_eth_conf *conf;
> + uint32_t ethdev_queues;
> +
> + conf = &data->dev_conf;
> + rxmode = &conf->rxmode;
> + txmode = &conf->txmode;
> + ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
> + if (eth_dev->data->nb_rx_queues > ethdev_queues ||
> + eth_dev->data->nb_tx_queues > ethdev_queues) {
In dev_info, 'max_rx_queues' & 'max_tx_queues' set by 'otx_epvf->max_rx_queues'
& 'otx_epvf->max_tx_queues' respectively, but here they are checked against
'otx_epvf->sriov_info.rings_per_vf' are they same values? Or should dev_info
chaged to set correct limits?
-----Original Message-----
From: Ferruh Yigit <ferruh.yigit@intel.com>
Sent: Tuesday, January 26, 2021 9:01 PM
To: Pradeep Kumar Nalla <pnalla@marvell.com>; Radha Chintakuntla <radhac@marvell.com>; Veerasenareddy Burru <vburru@marvell.com>
Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; dev@dpdk.org; Satananda Burla <sburla@marvell.com>
Subject: [EXT] Re: [dpdk-dev] [PATCH v2 05/11] net/octeontx_ep: Add dev info get and configure
External Email
----------------------------------------------------------------------
On 1/18/2021 9:35 AM, Nalla Pradeep wrote:
> Add device information get and device configure operations.
>
> Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
<...>
> +static int
> +otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,
> + struct rte_eth_dev_info *devinfo) {
> + struct otx_ep_device *otx_epvf;
> + struct rte_pci_device *pdev;
> + uint32_t dev_id;
> +
> + otx_epvf = OTX_EP_DEV(eth_dev);
> + pdev = otx_epvf->pdev;
> + dev_id = pdev->id.device_id;
> +
> + devinfo->speed_capa = ETH_LINK_SPEED_10G;
>Is it always 10G independent from the device type and PHY?
Right now it is fixed for 10G. When communication infrastructure is incorporated with PF, will get information from PF.
>Also can you please update the featutes file, octeontx_ep.ini, as the same patch features are >added.
>For example the 'Speed capabilities' feature can be set as P (partially
>supported) with this patch.
> + devinfo->max_rx_queues = otx_epvf->max_rx_queues;
> + devinfo->max_tx_queues = otx_epvf->max_tx_queues;
> +
> + devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;
> + if (dev_id == PCI_DEVID_OCTEONTX_EP_VF ||
> + dev_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||
> + dev_id == PCI_DEVID_CN98XX_EP_NET_VF) {
> + devinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;
> + devinfo->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME;
> + devinfo->rx_offload_capa |= DEV_RX_OFFLOAD_SCATTER;
> + devinfo->tx_offload_capa = DEV_TX_OFFLOAD_MULTI_SEGS;
> + }
The above list seems all the devices this driver probes, is there a reason to check for them?
<...>
> +static int
> +otx_ep_dev_configure(struct rte_eth_dev *eth_dev) {
> + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
> + struct rte_eth_dev_data *data = eth_dev->data;
> + struct rte_eth_rxmode *rxmode;
> + struct rte_eth_txmode *txmode;
> + struct rte_eth_conf *conf;
> + uint32_t ethdev_queues;
> +
> + conf = &data->dev_conf;
> + rxmode = &conf->rxmode;
> + txmode = &conf->txmode;
> + ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
> + if (eth_dev->data->nb_rx_queues > ethdev_queues ||
> + eth_dev->data->nb_tx_queues > ethdev_queues) {
In dev_info, 'max_rx_queues' & 'max_tx_queues' set by 'otx_epvf->max_rx_queues'
& 'otx_epvf->max_tx_queues' respectively, but here they are checked against 'otx_epvf->sriov_info.rings_per_vf' are they same values? Or should dev_info chaged to set correct limits?
@@ -7,9 +7,12 @@
#define OTX_EP_MAX_RINGS_PER_VF (8)
#define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF
#define OTX_EP_64BYTE_INSTR (64)
+#define OTX_EP_MIN_IQ_DESCRIPTORS (128)
+#define OTX_EP_MIN_OQ_DESCRIPTORS (128)
#define OTX_EP_MAX_IQ_DESCRIPTORS (8192)
#define OTX_EP_MAX_OQ_DESCRIPTORS (8192)
#define OTX_EP_OQ_BUF_SIZE (2048)
+#define OTX_EP_MIN_RX_BUF_SIZE (64)
#define OTX_EP_OQ_INFOPTR_MODE (0)
#define OTX_EP_OQ_REFIL_THRESHOLD (16)
@@ -112,6 +115,10 @@ struct otx_ep_device {
struct otx_ep_fn_list fn_list;
+ uint32_t max_tx_queues;
+
+ uint32_t max_rx_queues;
+
/* SR-IOV info */
struct otx_ep_sriov_info sriov_info;
@@ -119,5 +126,14 @@ struct otx_ep_device {
const struct otx_ep_config *conf;
int port_configured;
+
+ uint64_t rx_offloads;
+
+ uint64_t tx_offloads;
};
+
+#define OTX_EP_MAX_PKT_SZ 64000U
+
+#define OTX_EP_MAX_MAC_ADDRS 1
+
#endif /* _OTX_EP_COMMON_H_ */
@@ -10,8 +10,57 @@
#include "otx_ep_common.h"
#include "otx_ep_vf.h"
#include "otx2_ep_vf.h"
+#include "otx_ep_rxtx.h"
+
+#define OTX_EP_DEV(_eth_dev) \
+ ((struct otx_ep_device *)(_eth_dev)->data->dev_private)
+
+static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = {
+ .nb_max = OTX_EP_MAX_OQ_DESCRIPTORS,
+ .nb_min = OTX_EP_MIN_OQ_DESCRIPTORS,
+ .nb_align = OTX_EP_RXD_ALIGN,
+};
+
+static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = {
+ .nb_max = OTX_EP_MAX_IQ_DESCRIPTORS,
+ .nb_min = OTX_EP_MIN_IQ_DESCRIPTORS,
+ .nb_align = OTX_EP_TXD_ALIGN,
+};
+
+static int
+otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_dev_info *devinfo)
+{
+ struct otx_ep_device *otx_epvf;
+ struct rte_pci_device *pdev;
+ uint32_t dev_id;
+
+ otx_epvf = OTX_EP_DEV(eth_dev);
+ pdev = otx_epvf->pdev;
+ dev_id = pdev->id.device_id;
+
+ devinfo->speed_capa = ETH_LINK_SPEED_10G;
+ devinfo->max_rx_queues = otx_epvf->max_rx_queues;
+ devinfo->max_tx_queues = otx_epvf->max_tx_queues;
+
+ devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;
+ if (dev_id == PCI_DEVID_OCTEONTX_EP_VF ||
+ dev_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||
+ dev_id == PCI_DEVID_CN98XX_EP_NET_VF) {
+ devinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;
+ devinfo->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME;
+ devinfo->rx_offload_capa |= DEV_RX_OFFLOAD_SCATTER;
+ devinfo->tx_offload_capa = DEV_TX_OFFLOAD_MULTI_SEGS;
+ }
+
+ devinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS;
+
+ devinfo->rx_desc_lim = otx_ep_rx_desc_lim;
+ devinfo->tx_desc_lim = otx_ep_tx_desc_lim;
+
+ return 0;
+}
-#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)
static int
otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
{
@@ -62,6 +111,41 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)
return -ENOMEM;
}
+static int
+otx_ep_dev_configure(struct rte_eth_dev *eth_dev)
+{
+ struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct rte_eth_rxmode *rxmode;
+ struct rte_eth_txmode *txmode;
+ struct rte_eth_conf *conf;
+ uint32_t ethdev_queues;
+
+ conf = &data->dev_conf;
+ rxmode = &conf->rxmode;
+ txmode = &conf->txmode;
+ ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
+ if (eth_dev->data->nb_rx_queues > ethdev_queues ||
+ eth_dev->data->nb_tx_queues > ethdev_queues) {
+ otx_ep_err("invalid num queues\n");
+ return -ENOMEM;
+ }
+ otx_ep_info("OTX_EP Device is configured with num_txq %d num_rxq %d\n",
+ eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues);
+
+ otx_epvf->port_configured = 1;
+ otx_epvf->rx_offloads = rxmode->offloads;
+ otx_epvf->tx_offloads = txmode->offloads;
+
+ return 0;
+}
+
+/* Define our ethernet definitions */
+static const struct eth_dev_ops otx_ep_eth_dev_ops = {
+ .dev_configure = otx_ep_dev_configure,
+ .dev_infos_get = otx_ep_dev_info_get,
+};
+
static int
otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)
{
@@ -99,6 +183,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
}
otx_epvf->eth_dev = eth_dev;
otx_epvf->port_id = eth_dev->data->port_id;
+ eth_dev->dev_ops = &otx_ep_eth_dev_ops;
eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0);
if (eth_dev->data->mac_addrs == NULL) {
otx_ep_err("MAC addresses memory allocation failed\n");
@@ -139,8 +224,6 @@ static const struct rte_pci_id pci_id_otx_ep_map[] = {
{ .vendor_id = 0, /* sentinel */ }
};
-
-
static struct rte_pci_driver rte_otx_ep_pmd = {
.id_table = pci_id_otx_ep_map,
.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
new file mode 100644
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2020 Marvell.
+ */
+
+#ifndef _OTX_EP_RXTX_H_
+#define _OTX_EP_RXTX_H_
+
+#define OTX_EP_RXD_ALIGN 1
+#define OTX_EP_TXD_ALIGN 1
+#endif