From patchwork Mon Jan 11 17:43:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 86330 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BDD1DA09FF; Mon, 11 Jan 2021 18:44:39 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0FB3F140FB3; Mon, 11 Jan 2021 18:44:17 +0100 (CET) Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mails.dpdk.org (Postfix) with ESMTP id 50A90140FA5 for ; Mon, 11 Jan 2021 18:44:13 +0100 (CET) Received: by mail-pj1-f41.google.com with SMTP id j13so17162pjz.3 for ; Mon, 11 Jan 2021 09:44:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RR0vydwDrFllLhk0bVcLhdFn2ZBXbS0aU/Ku5wwyT9M=; b=WbQfWylyZcu+jLg+mqoX3HBVUD2GCjKyIH94el39U+hFJpfTSnTmoxHsifg2XxvWdE KxjpGGWOzcX2RKqf22Au2cZKk76iP+SDq9jwS0SDxXctbVzAb0PptjwQpG6ocuVh3mB1 0sfKxksaBVBdSGsnaVpQQzXn1P6nTC1Lmj9sVZfp8fcsC2UDKwfukfhmGjMyugfjxjMu 1uq+fkWHdkp2VKCigQARLuSfMFqWmYLIGz96Y1dsaMvrUESnf3evpF24TfpOqzWAV84L IECDLe4Mlu6eYcEEmxolDvbKCsMM8c1pOFFpUwQDXBMyAgr/NARI5Advc+enU3Ew7N0H I+bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RR0vydwDrFllLhk0bVcLhdFn2ZBXbS0aU/Ku5wwyT9M=; b=mgXPlY0gWp3dAmbu4RKCPIMatJiTuOkh0ck2lEIk9GNuoJ0lc+lOyN0vlAk1XpEnct s1YUHbxcoazJfmOOp3MVgOiBq0nl3SH3QFFgR3dwqGaocXv9a6rwqmcJHwhqVrhWTTkJ hA7bMCfrcvsX3YZWUB+tnLStZqU91dj6oekJeoLFtThE3bB9fpIXMbIm1NuNYeoAeuB5 77olD5JhUQLRPLrHQc9hViM34GHivDUvGQxSDE16EcwYQpRKeSYsRAytC15qzcnxNycD k/PrjbChc7Q4mFEYBgf+km0x6QdN3x/0ySH9X5A9uDoeJOTWKn723ZJQHYkGNIwWjNLo fYzg== X-Gm-Message-State: AOAM531GFQ7/rz/fBRU+pdaaLdHCfQ0yWJCrQ6FvEaykkUSfzECkyW5d ajP/zIddtu9yTgE+boG1Me4tWcpRq5W95Q== X-Google-Smtp-Source: ABdhPJx0SZ3v+LzWLxU25UJQlgxuN/pciwf0Vq8QC20D05l+Fc1TfhquO+EyMWi1odZk88XQ65UlyA== X-Received: by 2002:a17:90b:1187:: with SMTP id gk7mr396865pjb.162.1610387052270; Mon, 11 Jan 2021 09:44:12 -0800 (PST) Received: from localhost.localdomain ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t6sm4750pjg.49.2021.01.11.09.44.11 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jan 2021 09:44:11 -0800 (PST) From: Ajit Khaparde X-Google-Original-From: Ajit Khaparde To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Kalesh AP Date: Mon, 11 Jan 2021 09:43:58 -0800 Message-Id: <20210111174400.10606-5-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20210111174400.10606-1-ajit.khaparde@broadcom.com> References: <20210108051301.33416-1-ajit.khaparde@broadcom.com> <20210111174400.10606-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 4/6] net/bnxt: add LRO support for SR2 chip X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP Add the new chip specific TPA v2 logic to bnxt_tpa_start() to fully support TPA on the new chip. Signed-off-by: Kalesh AP Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt_rxr.c | 72 +++++++++++++++++++++++++++++++------ drivers/net/bnxt/bnxt_rxr.h | 12 ++++++- 2 files changed, 72 insertions(+), 12 deletions(-) diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c index 14901f1b9..af3f9b936 100644 --- a/drivers/net/bnxt/bnxt_rxr.c +++ b/drivers/net/bnxt/bnxt_rxr.c @@ -134,6 +134,53 @@ struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr, return mbuf; } +static void bnxt_tpa_get_metadata(struct bnxt *bp, + struct bnxt_tpa_info *tpa_info, + struct rx_tpa_start_cmpl *tpa_start, + struct rx_tpa_start_cmpl_hi *tpa_start1) +{ + tpa_info->cfa_code_valid = 0; + tpa_info->vlan_valid = 0; + tpa_info->hash_valid = 0; + tpa_info->l4_csum_valid = 0; + + if (likely(tpa_start->flags_type & + rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) { + tpa_info->hash_valid = 1; + tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash); + } + + if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) { + struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start; + struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 = + (void *)tpa_start1; + + if (v2_tpa_start->agg_id & + RX_TPA_START_V2_CMPL_METADATA1_VALID) { + tpa_info->vlan_valid = 1; + tpa_info->vlan = + rte_le_to_cpu_16(v2_tpa_start1->metadata0); + } + + if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK) + tpa_info->l4_csum_valid = 1; + + return; + } + + tpa_info->cfa_code_valid = 1; + tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code); + if (tpa_start1->flags2 & + rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) { + tpa_info->vlan_valid = 1; + tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata); + } + + if (likely(tpa_start1->flags2 & + rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC))) + tpa_info->l4_csum_valid = 1; +} + static void bnxt_tpa_start(struct bnxt_rx_queue *rxq, struct rx_tpa_start_cmpl *tpa_start, struct rx_tpa_start_cmpl_hi *tpa_start1) @@ -164,21 +211,23 @@ static void bnxt_tpa_start(struct bnxt_rx_queue *rxq, mbuf->data_len = mbuf->pkt_len; mbuf->port = rxq->port_id; mbuf->ol_flags = PKT_RX_LRO; - if (likely(tpa_start->flags_type & - rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) { - mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash); + + bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1); + + if (likely(tpa_info->hash_valid)) { + mbuf->hash.rss = tpa_info->rss_hash; mbuf->ol_flags |= PKT_RX_RSS_HASH; - } else { - mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code); + } else if (tpa_info->cfa_code_valid) { + mbuf->hash.fdir.id = tpa_info->cfa_code; mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID; } - if (tpa_start1->flags2 & - rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) { - mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata); + + if (tpa_info->vlan_valid) { + mbuf->vlan_tci = tpa_info->vlan; mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; } - if (likely(tpa_start1->flags2 & - rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC))) + + if (likely(tpa_info->l4_csum_valid)) mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD; /* recycle next mbuf */ @@ -751,7 +800,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt, cpr->cp_ring_struct->ring_mask, cpr->valid); - if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) { + if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START || + cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) { bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp, (struct rx_tpa_start_cmpl_hi *)rxcmp1); rc = -EINVAL; /* Continue w/o new mbuf */ diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h index b2942030a..78814edbb 100644 --- a/drivers/net/bnxt/bnxt_rxr.h +++ b/drivers/net/bnxt/bnxt_rxr.h @@ -50,6 +50,14 @@ struct bnxt_tpa_info { uint16_t len; uint32_t agg_count; struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS]; + + uint32_t rss_hash; + uint32_t vlan; + uint16_t cfa_code; + uint8_t hash_valid:1; + uint8_t vlan_valid:1; + uint8_t cfa_code_valid:1; + uint8_t l4_csum_valid:1; }; struct bnxt_rx_ring_info { @@ -122,4 +130,6 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf) #define BNXT_PTYPE_TBL_DIM 128 extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM]; -#endif + +#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14) +#endif /* _BNXT_RXR_H_ */