From patchwork Thu Dec 31 07:22:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pradeep Nalla X-Patchwork-Id: 85921 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DFFF5A0A00; Thu, 31 Dec 2020 08:24:19 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 71649140D1E; Thu, 31 Dec 2020 08:23:09 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B3A20140CEC for ; Thu, 31 Dec 2020 08:23:00 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0BV7G0IN022182 for ; Wed, 30 Dec 2020 23:22:59 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=Z51CNQwmNsdNzopUOCF7wMeGef+w+2YAtWW7EguuFTI=; b=j/aaTvkfk+2QKk9ZmK9W7qeRnH2Yn8H2ierLC5QWj547ru7QoKeao/xrICCnuM9icAnN wvsIZvu3gqb1IPoxr3mW1DDw7JPSHYzsAM2jgOgGxq9hyQuCOASftnAikpaSN7JVRZsb zgmcHH7LVoTdn1AUCzzLuv0XqaolLQLkJhLuhRa+qW8AMrbdl9glZjdz1Kiy/V83QP8B xY8ya43dYIeN46jfXd/DZzma4SS9ve5t7MjTcGqYuDKbLw04e2PrXDcO103txXXw9zqX fXx7V+Og4gVmqGG2+0KRd89A2QaR9ordoGAehtIt9lltT1Bpg+yHg6s8tWDVDGRiPDvQ 6w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx58-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 30 Dec 2020 23:22:59 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Dec 2020 23:22:58 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Dec 2020 23:22:58 -0800 Received: from localhost.localdomain (unknown [10.111.145.157]) by maili.marvell.com (Postfix) with ESMTP id 3968C3F7041; Wed, 30 Dec 2020 23:22:58 -0800 (PST) From: "Nalla, Pradeep" To: "Nalla, Pradeep" , Radha Mohan Chintakuntla , Veerasenareddy Burru CC: , , Date: Thu, 31 Dec 2020 07:22:44 +0000 Message-ID: <20201231072247.5719-13-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201231072247.5719-1-pnalla@marvell.com> References: <20201231072247.5719-1-pnalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-31_02:2020-12-30, 2020-12-31 signatures=0 Subject: [dpdk-dev] [PATCH 12/15] net/octeontx_ep: INFO PTR mode support added. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Nalla Pradeep" Hardware can be programmed to write the meta data of incoming packet in the same buffer it uses to fill the packet(BUF PTR mode) or a different buffer (INFO PTR mode). Signed-off-by: Nalla Pradeep --- drivers/net/octeontx_ep/meson.build | 2 +- drivers/net/octeontx_ep/otx_ep_common.h | 8 ++++ drivers/net/octeontx_ep/otx_ep_rxtx.c | 55 ++++++++++++++++++++++++- 3 files changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build index 8d804a0398..08e8131bfe 100644 --- a/drivers/net/octeontx_ep/meson.build +++ b/drivers/net/octeontx_ep/meson.build @@ -9,7 +9,7 @@ sources = files( 'otx_ep_rxtx.c', ) -extra_flags = [] +extra_flags = ['-DBUFPTR_ONLY_MODE'] # This integrated controller runs only on a arm64 machine, remove 32bit warnings if not dpdk_conf.get('RTE_ARCH_64') extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast'] diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index 978cceab01..0b6e7e2042 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -239,11 +239,19 @@ union otx_ep_rh { * about the packet. */ struct otx_ep_droq_info { +#ifndef BUFPTR_ONLY_MODE + /* The Output Receive Header. */ + union otx_ep_rh rh; + + /* The Length of the packet. */ + uint64_t length; +#else /* The Length of the packet. */ uint64_t length; /* The Output Receive Header. */ union otx_ep_rh rh; +#endif }; #define OTX_EP_DROQ_INFO_SIZE (sizeof(struct otx_ep_droq_info)) diff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.c b/drivers/net/octeontx_ep/otx_ep_rxtx.c index 4ffe0b8546..279ab9f6d6 100644 --- a/drivers/net/octeontx_ep/otx_ep_rxtx.c +++ b/drivers/net/octeontx_ep/otx_ep_rxtx.c @@ -215,6 +215,13 @@ otx_ep_delete_oqs(struct otx_ep_device *otx_ep, uint32_t oq_no) rte_free(droq->recv_buf_list); droq->recv_buf_list = NULL; +#ifndef BUFPTR_ONLY_MODE + if (droq->info_mz) { + otx_ep_dmazone_free(droq->info_mz); + droq->info_mz = NULL; + } +#endif + if (droq->desc_ring_mz) { otx_ep_dmazone_free(droq->desc_ring_mz); droq->desc_ring_mz = NULL; @@ -249,6 +256,13 @@ otx_ep_droq_setup_ring_buffers(struct otx_ep_droq *droq) } droq->recv_buf_list[idx] = buf; +#ifndef BUFPTR_ONLY_MODE + droq->info_list[idx].length = 0; + + /* Map ring buffers into memory */ + desc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma + + (idx * OTX_EP_DROQ_INFO_SIZE)); +#endif info = rte_pktmbuf_mtod(buf, struct otx_ep_droq_info *); memset(info, 0, sizeof(*info)); desc_ring[idx].buffer_ptr = rte_mbuf_data_iova_default(buf); @@ -259,6 +273,28 @@ otx_ep_droq_setup_ring_buffers(struct otx_ep_droq *droq) return 0; } +#ifndef BUFPTR_ONLY_MODE +static void * +otx_ep_alloc_info_buffer(struct otx_ep_device *otx_ep __rte_unused, + struct otx_ep_droq *droq, unsigned int socket_id) +{ + droq->info_mz = rte_memzone_reserve_aligned("OQ_info_list", + (droq->nb_desc * OTX_EP_DROQ_INFO_SIZE), + socket_id, + RTE_MEMZONE_IOVA_CONTIG, + OTX_EP_PCI_RING_ALIGN); + + if (droq->info_mz == NULL) + return NULL; + + droq->info_list_dma = droq->info_mz->iova; + droq->info_alloc_size = droq->info_mz->len; + droq->info_base_addr = (size_t)droq->info_mz->addr; + + return droq->info_mz->addr; +} +#endif + /* OQ initialization */ static int otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no, @@ -301,6 +337,16 @@ otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no, q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma); otx_ep_dbg("OQ[%d]: num_desc: %d\n", q_no, droq->nb_desc); +#ifndef BUFPTR_ONLY_MODE + /* OQ info_list set up */ + droq->info_list = otx_ep_alloc_info_buffer(otx_ep, droq, socket_id); + if (droq->info_list == NULL) { + otx_ep_err("memory allocation failed for OQ[%d] info_list\n", + q_no); + goto init_droq_fail; + } + +#endif /* OQ buf_list set up */ droq->recv_buf_list = rte_zmalloc_socket("recv_buf_list", (droq->nb_desc * sizeof(struct rte_mbuf *)), @@ -836,7 +882,10 @@ otx_ep_droq_refill(struct otx_ep_droq *droq) desc_ring[droq->refill_idx].buffer_ptr = rte_mbuf_data_iova_default(buf); - +#ifndef BUFPTR_ONLY_MODE + /* Reset any previous values in the length field. */ + droq->info_list[droq->refill_idx].length = 0; +#endif droq->refill_idx = otx_ep_incr_index(droq->refill_idx, 1, droq->nb_desc); @@ -862,6 +911,9 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep, droq_pkt = droq->recv_buf_list[droq->read_idx]; droq_pkt2 = droq->recv_buf_list[droq->read_idx]; +#ifndef BUFPTR_ONLY_MODE + info = &droq->info_list[droq->read_idx]; +#else info = rte_pktmbuf_mtod(droq_pkt, struct otx_ep_droq_info *); /* make sure info is available */ rte_rmb(); @@ -893,6 +945,7 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep, info2 = rte_pktmbuf_mtod(droq_pkt2, struct otx_ep_droq_info *); rte_prefetch_non_temporal((const void *)info2); } +#endif info->length = rte_bswap64(info->length); /* Deduce the actual data size */