From patchwork Thu Dec 31 07:22:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pradeep Nalla X-Patchwork-Id: 85926 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C960BA0A00; Thu, 31 Dec 2020 08:25:24 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A623F140D51; Thu, 31 Dec 2020 08:23:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 475C5140CF5 for ; Thu, 31 Dec 2020 08:23:01 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0BV7G0IP022182 for ; Wed, 30 Dec 2020 23:23:00 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=FYooKExqCew6z63sX5XboHmeaGm21uIo8dHCueoL9bo=; b=jIDdUUq0e0daBTB7sFIoaZ09Agd87/5Ol3frY7gD/qCgy73NMQBHQxzvACMSYlqiJBKj frESvDFKqe+Ka8z4YlvNmO1eIF3GA2OcgzNyRTQncH4QMpjnsM9redTQHMBNPVTeM2gm aRXknSHcNxl5oz2qpFJn4Eiuk0kHMRU1qFZeill3yAUOQ4+MkoPJWocYxti8xWWaUJVy 2z/tDPS4Qby4M7zdxdy5nA0N1vqrdcuKj8jUNe6l4a5F1e+yuF+6bzz/XQd9FoXbpa/n Hu6BwhFaKQ+MF3rDKiXS1Q5iJjs0c8ZI7ZnDu5qz0zzxNEPnWXv1RFccIlRW0dJOM2t1 8g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx58-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 30 Dec 2020 23:23:00 -0800 Received: from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Dec 2020 23:22:58 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Dec 2020 23:22:57 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Dec 2020 23:22:57 -0800 Received: from localhost.localdomain (unknown [10.111.145.157]) by maili.marvell.com (Postfix) with ESMTP id 531903F7041; Wed, 30 Dec 2020 23:22:57 -0800 (PST) From: "Nalla, Pradeep" To: "Nalla, Pradeep" , Radha Mohan Chintakuntla , Veerasenareddy Burru CC: , , Date: Thu, 31 Dec 2020 07:22:41 +0000 Message-ID: <20201231072247.5719-10-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201231072247.5719-1-pnalla@marvell.com> References: <20201231072247.5719-1-pnalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-31_02:2020-12-30, 2020-12-31 signatures=0 Subject: [dpdk-dev] [PATCH 09/15] net/octeontx_ep: Added dev start and stop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Nalla Pradeep" Dev start and stop operations are added. To accomplish this internal functions to enable or disable io queues are incorporated. Signed-off-by: Nalla Pradeep --- drivers/net/octeontx_ep/otx2_ep_vf.c | 92 +++++++++++++++++++ drivers/net/octeontx_ep/otx_ep_common.h | 13 +++ drivers/net/octeontx_ep/otx_ep_ethdev.c | 45 ++++++++++ drivers/net/octeontx_ep/otx_ep_vf.c | 114 ++++++++++++++++++++++++ drivers/net/octeontx_ep/otx_ep_vf.h | 4 + 5 files changed, 268 insertions(+) diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c index f2cd442e97..b570a49566 100644 --- a/drivers/net/octeontx_ep/otx2_ep_vf.c +++ b/drivers/net/octeontx_ep/otx2_ep_vf.c @@ -199,6 +199,89 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no) rte_read32(droq->pkts_sent_reg)); } +static void +otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no) +{ + volatile uint64_t reg_val = 0ull; + uint64_t loop = SDP_VF_BUSY_LOOP_COUNT; + + /* Resetting doorbells during IQ enabling also to handle abrupt + * guest reboot. IQ reset does not clear the doorbells. + */ + otx2_write64(0xFFFFFFFF, otx_ep->hw_addr + + SDP_VF_R_IN_INSTR_DBELL(q_no)); + + while (((otx2_read64(otx_ep->hw_addr + + SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) { + rte_delay_ms(1); + } + + reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no)); + reg_val |= 0x1ull; + + otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no)); + + otx2_info("IQ[%d] enable done", q_no); +} + +static void +otx2_vf_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no) +{ + volatile uint64_t reg_val = 0ull; + + reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no)); + reg_val |= 0x1ull; + otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no)); + + otx2_info("OQ[%d] enable done", q_no); +} + +static void +otx2_vf_enable_io_queues(struct otx_ep_device *otx_ep) +{ + uint32_t q_no = 0; + + for (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) + otx2_vf_enable_iq(otx_ep, q_no); + + for (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++) + otx2_vf_enable_oq(otx_ep, q_no); +} + +static void +otx2_vf_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no) +{ + volatile uint64_t reg_val = 0ull; + + /* Reset the doorbell register for this Input Queue. */ + reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no)); + reg_val &= ~0x1ull; + + otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no)); +} + +static void +otx2_vf_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no) +{ + volatile uint64_t reg_val = 0ull; + + reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no)); + reg_val &= ~0x1ull; + + otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no)); +} + +static void +otx2_vf_disable_io_queues(struct otx_ep_device *otx_ep) +{ + uint32_t q_no = 0; + + for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) { + otx2_vf_disable_iq(otx_ep, q_no); + otx2_vf_disable_oq(otx_ep, q_no); + } +} + static const struct otx_ep_config default_otx2_ep_conf = { /* IQ attributes */ .iq = { @@ -258,5 +341,14 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep) otx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs; + otx_ep->fn_list.enable_io_queues = otx2_vf_enable_io_queues; + otx_ep->fn_list.disable_io_queues = otx2_vf_disable_io_queues; + + otx_ep->fn_list.enable_iq = otx2_vf_enable_iq; + otx_ep->fn_list.disable_iq = otx2_vf_disable_iq; + + otx_ep->fn_list.enable_oq = otx2_vf_enable_oq; + otx_ep->fn_list.disable_oq = otx2_vf_disable_oq; + return 0; } diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index e7e393ef00..50c9e2daa3 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -19,6 +19,8 @@ #define OTX_EP_PCI_RING_ALIGN 65536 #define SDP_PKIND 40 #define SDP_OTX2_PKIND 57 +#define OTX_EP_BUSY_LOOP_COUNT (10000) + #define OTX_EP_MAX_IOQS_PER_VF 8 #define otx_ep_printf(level, fmt, args...) \ rte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD, \ @@ -362,7 +364,14 @@ struct otx_ep_fn_list { int (*setup_device_regs)(struct otx_ep_device *otx_ep); + void (*enable_io_queues)(struct otx_ep_device *otx_ep); void (*disable_io_queues)(struct otx_ep_device *otx_ep); + + void (*enable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no); + void (*disable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no); + + void (*enable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no); + void (*disable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no); }; /* SRIOV information */ @@ -417,6 +426,10 @@ struct otx_ep_device { /* Device configuration */ const struct otx_ep_config *conf; + int started; + + int linkup; + int port_configured; uint64_t rx_offloads; diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index dc419d3447..f782c90ad7 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -60,6 +60,47 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev, return 0; } +static int +otx_ep_dev_start(struct rte_eth_dev *eth_dev) +{ + struct otx_ep_device *otx_epvf; + unsigned int q; + + otx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev); + /* Enable IQ/OQ for this device */ + otx_epvf->fn_list.enable_io_queues(otx_epvf); + + for (q = 0; q < otx_epvf->nb_rx_queues; q++) { + rte_write32(otx_epvf->droq[q]->nb_desc, + otx_epvf->droq[q]->pkts_credit_reg); + + rte_wmb(); + otx_ep_info("OQ[%d] dbells [%d]\n", q, + rte_read32(otx_epvf->droq[q]->pkts_credit_reg)); + } + + otx_epvf->started = 1; + otx_epvf->linkup = 1; + + rte_wmb(); + otx_ep_info("dev started\n"); + + return 0; +} + +/* Stop device and disable input/output functions */ +static int +otx_ep_dev_stop(struct rte_eth_dev *eth_dev) +{ + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + + otx_epvf->fn_list.disable_io_queues(otx_epvf); + otx_epvf->started = 0; + otx_epvf->linkup = 0; + + return 0; +} + static int otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) { @@ -304,6 +345,8 @@ otx_ep_tx_queue_release(void *txq) /* Define our ethernet definitions */ static const struct eth_dev_ops otx_ep_eth_dev_ops = { .dev_configure = otx_ep_dev_configure, + .dev_start = otx_ep_dev_start, + .dev_stop = otx_ep_dev_stop, .rx_queue_setup = otx_ep_rx_queue_setup, .rx_queue_release = otx_ep_rx_queue_release, .tx_queue_setup = otx_ep_tx_queue_setup, @@ -323,6 +366,8 @@ otx_epdev_exit(struct rte_eth_dev *eth_dev) otx_epvf = OTX_EP_DEV(eth_dev); + otx_epvf->fn_list.disable_io_queues(otx_epvf); + num_queues = otx_epvf->nb_rx_queues; for (q = 0; q < num_queues; q++) { if (otx_ep_delete_oqs(otx_epvf, q)) { diff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c index 3d990a488f..4a00736dab 100644 --- a/drivers/net/octeontx_ep/otx_ep_vf.c +++ b/drivers/net/octeontx_ep/otx_ep_vf.c @@ -220,6 +220,110 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no) } } +static void +otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no) +{ + volatile uint64_t reg_val = 0ull; + uint64_t loop = OTX_EP_BUSY_LOOP_COUNT; + + /* Resetting doorbells during IQ enabling also to handle abrupt + * guest reboot. IQ reset does not clear the doorbells. + */ + otx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr, + OTX_EP_R_IN_INSTR_DBELL(q_no)); + + while (((rte_read64(otx_ep->hw_addr + + OTX_EP_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) { + rte_delay_ms(1); + } + if (loop == 0) { + otx_ep_err("dbell reset failed\n"); + return; + } + + + reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no)); + reg_val |= 0x1ull; + + otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no)); + + otx_ep_info("IQ[%d] enable done\n", q_no); +} + +static void +otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no) +{ + volatile uint64_t reg_val = 0ull; + uint64_t loop = OTX_EP_BUSY_LOOP_COUNT; + + /* Resetting doorbells during IQ enabling also to handle abrupt + * guest reboot. IQ reset does not clear the doorbells. + */ + otx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr, + OTX_EP_R_OUT_SLIST_DBELL(q_no)); + while (((rte_read64(otx_ep->hw_addr + + OTX_EP_R_OUT_SLIST_DBELL(q_no))) != 0ull) && loop--) { + rte_delay_ms(1); + } + if (loop == 0) { + otx_ep_err("dbell reset failed\n"); + return; + } + + + reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no)); + reg_val |= 0x1ull; + otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no)); + + otx_ep_info("OQ[%d] enable done\n", q_no); +} + +static void +otx_ep_enable_io_queues(struct otx_ep_device *otx_ep) +{ + uint32_t q_no = 0; + + for (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) + otx_ep_enable_iq(otx_ep, q_no); + + for (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++) + otx_ep_enable_oq(otx_ep, q_no); +} + +static void +otx_ep_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no) +{ + volatile uint64_t reg_val = 0ull; + + /* Reset the doorbell register for this Input Queue. */ + reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no)); + reg_val &= ~0x1ull; + + otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no)); +} + +static void +otx_ep_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no) +{ + volatile uint64_t reg_val = 0ull; + + reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no)); + reg_val &= ~0x1ull; + + otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no)); +} + +static void +otx_ep_disable_io_queues(struct otx_ep_device *otx_ep) +{ + uint32_t q_no = 0; + + for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) { + otx_ep_disable_iq(otx_ep, q_no); + otx_ep_disable_oq(otx_ep, q_no); + } +} + /* OTX_EP default configuration */ static const struct otx_ep_config default_otx_ep_conf = { /* IQ attributes */ @@ -282,5 +386,15 @@ otx_ep_vf_setup_device(struct otx_ep_device *otx_ep) otx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs; + otx_ep->fn_list.enable_io_queues = otx_ep_enable_io_queues; + otx_ep->fn_list.disable_io_queues = otx_ep_disable_io_queues; + + otx_ep->fn_list.enable_iq = otx_ep_enable_iq; + otx_ep->fn_list.disable_iq = otx_ep_disable_iq; + + otx_ep->fn_list.enable_oq = otx_ep_enable_oq; + otx_ep->fn_list.disable_oq = otx_ep_disable_oq; + + return 0; } diff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h index d6aa326dc3..d2128712aa 100644 --- a/drivers/net/octeontx_ep/otx_ep_vf.h +++ b/drivers/net/octeontx_ep/otx_ep_vf.h @@ -12,6 +12,7 @@ /* OTX_EP VF IQ Registers */ #define OTX_EP_R_IN_CONTROL_START (0x10000) +#define OTX_EP_R_IN_ENABLE_START (0x10010) #define OTX_EP_R_IN_INSTR_BADDR_START (0x10020) #define OTX_EP_R_IN_INSTR_RSIZE_START (0x10030) #define OTX_EP_R_IN_INSTR_DBELL_START (0x10040) @@ -21,6 +22,9 @@ #define OTX_EP_R_IN_CONTROL(ring) \ (OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET)) +#define OTX_EP_R_IN_ENABLE(ring) \ + (OTX_EP_R_IN_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET)) + #define OTX_EP_R_IN_INSTR_BADDR(ring) \ (OTX_EP_R_IN_INSTR_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))