From patchwork Sun Dec 20 05:24:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 85512 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 39CC9A052A; Sun, 20 Dec 2020 06:25:17 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CAFEACB7E; Sun, 20 Dec 2020 06:24:43 +0100 (CET) Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) by dpdk.org (Postfix) with ESMTP id 78020CB2F for ; Sun, 20 Dec 2020 06:24:39 +0100 (CET) Received: by mail-pf1-f175.google.com with SMTP id f9so4442092pfc.11 for ; Sat, 19 Dec 2020 21:24:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QjJsPQwxHzH6eKBpzx/SBNEjsRg91DUBB1vquBRgSeI=; b=b0zibezIUiKsmqeMpOiRpXY2aBaSEz1nCxXHVIm1npKjuVkz5ZnJk6bS6rSutuvGYu uTohSlAtqDBH1mykxuOzpnZw28Y0U13quifGLK2jE8Ct5vC6TJ33SXnSX1adeQx1R3G0 /5ctiGqhkBdbFm51AzDNq530NsaXZCQlY3nWTq+2DVNHcBLjB7hl91/2UoptQm0gwqy6 WMNYE89YR7n9+cX8poEHHYer6EJ9A67bnXCWXjkJn4wOGTAuNpn8ytZvPGuAGoG2zlxo aT67hg9RI8lSy6ImNeeciQx1Qurl+btvq/bqn9bqDv6mrHmbE/N1FnW/EOJOg3Zncj+D Y+Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QjJsPQwxHzH6eKBpzx/SBNEjsRg91DUBB1vquBRgSeI=; b=A5IleqehtEyCXcYksNo9GRNJwbh3obRxZOnWFxEoDKmd6885gLpwXvYChpqNz347yK Y6zKlOoZGyYxYR7BkEY3cIP5DhviHcI0n8UcbcMqVEFvtlDSnqLdrzbRlw7fJ44W5r85 SNIlhHpKzVKed7b7ecxqdtCR9fCztfhCx9dB/vUyG5Bu59pXpk6BnOqrMDPouLntC3AO apNDUCaK7ERdULs8HWsWCPaz6Vr8z/q8vF934PEqP00awmqHsnCmG4JXSfIg7P+13d7e hNChqpv6cxYwTRN4up8PuGw8p1UPFR5lIpp6doVDtZ5TuwMOPEDeRJcqQacThzDsyqRz TO5g== X-Gm-Message-State: AOAM530nFe/GscvsXx+IBMoIpK66TnITjaa4c4NP7WsfD0XW10XB1ba6 HXZV6g7+rz+bc2Sjy6OCNWm67phdEUU8Ug== X-Google-Smtp-Source: ABdhPJysbyECR6iSYqJ0GJiu8S0SuEtqhQGqKsTd+itAfassDF9TxyITDucGKLm1/G0nSqUDMbZLbg== X-Received: by 2002:a63:1220:: with SMTP id h32mr10415123pgl.309.1608441877438; Sat, 19 Dec 2020 21:24:37 -0800 (PST) Received: from localhost.localdomain ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id b11sm12936544pfr.38.2020.12.19.21.24.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 19 Dec 2020 21:24:36 -0800 (PST) From: Ajit Khaparde X-Google-Original-From: Ajit Khaparde To: dev@dpdk.org Cc: Kalesh AP Date: Sat, 19 Dec 2020 21:24:26 -0800 Message-Id: <20201220052430.99990-3-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20201220052430.99990-1-ajit.khaparde@broadcom.com> References: <20201220052430.99990-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/6] net/bnxt: add new RX checksum mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP The 58818 chips support two different checksum modes. Host driver has to register with FW which checksum mode it prefers to use. DPDK driver want to use "cs_all_ok_mode=1". FW advertises the support of the different checksum modes on per VNIC basis in the HWRM_VNIC_QCAPS response. Driver should use HWRM_VNIC_CFG to configure the needed checksum mode. Signed-off-by: Kalesh AP Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt.h | 1 + drivers/net/bnxt/bnxt_hwrm.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 0d3998f20..14f52b2c4 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -679,6 +679,7 @@ struct bnxt { uint32_t vnic_cap_flags; #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) +#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2) unsigned int rx_nr_rings; unsigned int rx_cp_nr_rings; unsigned int rx_num_qs_per_vnic; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 36c229de1..350fe2f97 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -860,6 +860,9 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP) bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS; + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP) + bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2; + bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported); HWRM_UNLOCK(); @@ -1961,6 +1964,11 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic) rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id); enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID | HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID; + if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) { + enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE; + req.rx_csum_v2_mode = + HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK; + } goto config_mru; }