From patchwork Tue Nov 3 10:08:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 83546 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A8430A0521; Tue, 3 Nov 2020 11:16:17 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4C6C7CA54; Tue, 3 Nov 2020 11:07:44 +0100 (CET) Received: from smtpproxy21.qq.com (smtpbg702.qq.com [203.205.195.102]) by dpdk.org (Postfix) with ESMTP id 6FB7BC9D2 for ; Tue, 3 Nov 2020 11:07:26 +0100 (CET) X-QQ-mid: bizesmtp26t1604398043t0nbknsp Received: from localhost.localdomain.com (unknown [183.129.236.74]) by esmtp10.qq.com (ESMTP) with id ; Tue, 03 Nov 2020 18:07:22 +0800 (CST) X-QQ-SSF: 01400000002000C0C000B00A0000000 X-QQ-FEAT: Oux8rCUi2/hcBOyDaitxgXC7XebLZo1QVnBsJCsiuntZV9S4pgstklApcHI+k jslx16CYswO+PI+ZCM/v9pzDDSrQBPr41DbhBT8ACmLs6Yuc4x7fLocxVK1nrGQn2g1dcZa ozliYv0PQhAPA/BZZx1EhLXEw1o6iRopXRdn6YwhrRSt2TEY7ARXyRCl/unSqAMxjaihY1g tjzU797GURsDAJNyYr0eM2Y/xIOEL9Z51qJxfQh4v/fEhyyxa9J8Wztftg7ltjUheUW3ebK tMeAn3E54jNbLkoCvTJAOlxjrP+ajnK8IoRNCX0IWU+ys44Swc/HSh7x6xHBGcJ29Z6YlWj zzpuSJyFAzZu6fqovvyNF8LBFsrdw== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Date: Tue, 3 Nov 2020 18:08:06 +0800 Message-Id: <20201103100818.311881-26-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20201103100818.311881-1-jiawenwu@trustnetic.com> References: <20201103100818.311881-1-jiawenwu@trustnetic.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign7 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH 25/37] net/txgbe: add flow API flush function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support to flush operation for flow API. Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_hw.c | 87 +++++++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_hw.h | 1 + drivers/net/txgbe/txgbe_ethdev.c | 21 ++++++++ drivers/net/txgbe/txgbe_ethdev.h | 2 + drivers/net/txgbe/txgbe_fdir.c | 47 +++++++++++++++++ drivers/net/txgbe/txgbe_flow.c | 43 +++++++++++++++ 6 files changed, 201 insertions(+) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 5ee13b0f8..dc419d7d4 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -3649,6 +3649,93 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw) return status; } +/** + * txgbe_fdir_check_cmd_complete - poll to check whether FDIRPICMD is complete + * @hw: pointer to hardware structure + * @fdircmd: current value of FDIRCMD register + */ +static s32 txgbe_fdir_check_cmd_complete(struct txgbe_hw *hw, u32 *fdircmd) +{ + int i; + + for (i = 0; i < TXGBE_FDIRCMD_CMD_POLL; i++) { + *fdircmd = rd32(hw, TXGBE_FDIRPICMD); + if (!(*fdircmd & TXGBE_FDIRPICMD_OP_MASK)) + return 0; + usec_delay(10); + } + + return TXGBE_ERR_FDIR_CMD_INCOMPLETE; +} + +/** + * txgbe_reinit_fdir_tables - Reinitialize Flow Director tables. + * @hw: pointer to hardware structure + **/ +s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw) +{ + s32 err; + int i; + u32 fdirctrl = rd32(hw, TXGBE_FDIRCTL); + u32 fdircmd; + fdirctrl &= ~TXGBE_FDIRCTL_INITDONE; + + DEBUGFUNC("txgbe_reinit_fdir_tables"); + + /* + * Before starting reinitialization process, + * FDIRPICMD.OP must be zero. + */ + err = txgbe_fdir_check_cmd_complete(hw, &fdircmd); + if (err) { + DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); + return err; + } + + wr32(hw, TXGBE_FDIRFREE, 0); + txgbe_flush(hw); + /* + * adapters flow director init flow cannot be restarted, + * Workaround silicon errata by performing the following steps + * before re-writing the FDIRCTL control register with the same value. + * - write 1 to bit 8 of FDIRPICMD register & + * - write 0 to bit 8 of FDIRPICMD register + */ + wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, TXGBE_FDIRPICMD_CLR); + txgbe_flush(hw); + wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, 0); + txgbe_flush(hw); + /* + * Clear FDIR Hash register to clear any leftover hashes + * waiting to be programmed. + */ + wr32(hw, TXGBE_FDIRPIHASH, 0x00); + txgbe_flush(hw); + + wr32(hw, TXGBE_FDIRCTL, fdirctrl); + txgbe_flush(hw); + + /* Poll init-done after we write FDIRCTL register */ + for (i = 0; i < TXGBE_FDIR_INIT_DONE_POLL; i++) { + if (rd32m(hw, TXGBE_FDIRCTL, TXGBE_FDIRCTL_INITDONE)) + break; + msec_delay(1); + } + if (i >= TXGBE_FDIR_INIT_DONE_POLL) { + DEBUGOUT("Flow Director Signature poll time exceeded!\n"); + return TXGBE_ERR_FDIR_REINIT_FAILED; + } + + /* Clear FDIR statistics registers (read to clear) */ + rd32(hw, TXGBE_FDIRUSED); + rd32(hw, TXGBE_FDIRFAIL); + rd32(hw, TXGBE_FDIRMATCH); + rd32(hw, TXGBE_FDIRMISS); + rd32(hw, TXGBE_FDIRLEN); + + return 0; +} + /** * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx * @hw: pointer to hardware structure diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index 09298ea0c..a7473e7e5 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -108,5 +108,6 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw); s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval); s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value); s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 value); +s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw); bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw); #endif /* _TXGBE_HW_H_ */ diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index cc061e0d6..83c078a2a 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -5186,6 +5186,27 @@ txgbe_clear_syn_filter(struct rte_eth_dev *dev) } } +/* remove all the L2 tunnel filters */ +int +txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) +{ + struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); + struct txgbe_l2_tn_filter *l2_tn_filter; + struct txgbe_l2_tunnel_conf l2_tn_conf; + int ret = 0; + + while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { + l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; + l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; + l2_tn_conf.pool = l2_tn_filter->pool; + ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); + if (ret < 0) + return ret; + } + + return 0; +} + static const struct eth_dev_ops txgbe_eth_dev_ops = { .dev_configure = txgbe_dev_configure, .dev_infos_get = txgbe_dev_info_get, diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h index f439a201b..1df74ab9b 100644 --- a/drivers/net/txgbe/txgbe_ethdev.h +++ b/drivers/net/txgbe/txgbe_ethdev.h @@ -488,12 +488,14 @@ int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev); uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val); void txgbe_fdir_filter_restore(struct rte_eth_dev *dev); +int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev); extern const struct rte_flow_ops txgbe_flow_ops; void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev); void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev); void txgbe_clear_syn_filter(struct rte_eth_dev *dev); +int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev); int txgbe_vt_check(struct txgbe_hw *hw); int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, diff --git a/drivers/net/txgbe/txgbe_fdir.c b/drivers/net/txgbe/txgbe_fdir.c index 2342cf681..6ddb023c0 100644 --- a/drivers/net/txgbe/txgbe_fdir.c +++ b/drivers/net/txgbe/txgbe_fdir.c @@ -902,6 +902,27 @@ txgbe_fdir_filter_program(struct rte_eth_dev *dev, return err; } +static int +txgbe_fdir_flush(struct rte_eth_dev *dev) +{ + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + struct txgbe_hw_fdir_info *info = TXGBE_DEV_FDIR(dev); + int ret; + + ret = txgbe_reinit_fdir_tables(hw); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to re-initialize FD table."); + return ret; + } + + info->f_add = 0; + info->f_remove = 0; + info->add = 0; + info->remove = 0; + + return ret; +} + /* restore flow director filter */ void txgbe_fdir_filter_restore(struct rte_eth_dev *dev) @@ -936,3 +957,29 @@ txgbe_fdir_filter_restore(struct rte_eth_dev *dev) } } +/* remove all the flow director filters */ +int +txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev) +{ + struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(dev); + struct txgbe_fdir_filter *fdir_filter; + struct txgbe_fdir_filter *filter_flag; + int ret = 0; + + /* flush flow director */ + rte_hash_reset(fdir_info->hash_handle); + memset(fdir_info->hash_map, 0, + sizeof(struct txgbe_fdir_filter *) * TXGBE_MAX_FDIR_FILTER_NUM); + filter_flag = TAILQ_FIRST(&fdir_info->fdir_list); + while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { + TAILQ_REMOVE(&fdir_info->fdir_list, + fdir_filter, + entries); + rte_free(fdir_filter); + } + + if (filter_flag != NULL) + ret = txgbe_fdir_flush(dev); + + return ret; +} diff --git a/drivers/net/txgbe/txgbe_flow.c b/drivers/net/txgbe/txgbe_flow.c index 8d5362175..b5f4073e2 100644 --- a/drivers/net/txgbe/txgbe_flow.c +++ b/drivers/net/txgbe/txgbe_flow.c @@ -2555,6 +2555,16 @@ txgbe_parse_rss_filter(struct rte_eth_dev *dev, return 0; } +/* remove the rss filter */ +static void +txgbe_clear_rss_filter(struct rte_eth_dev *dev) +{ + struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); + + if (filter_info->rss_info.conf.queue_num) + txgbe_config_rss_filter(dev, &filter_info->rss_info, FALSE); +} + void txgbe_filterlist_init(void) { @@ -3069,9 +3079,42 @@ txgbe_flow_destroy(struct rte_eth_dev *dev, return ret; } +/* Destroy all flow rules associated with a port on txgbe. */ +static int +txgbe_flow_flush(struct rte_eth_dev *dev, + struct rte_flow_error *error) +{ + int ret = 0; + + txgbe_clear_all_ntuple_filter(dev); + txgbe_clear_all_ethertype_filter(dev); + txgbe_clear_syn_filter(dev); + + ret = txgbe_clear_all_fdir_filter(dev); + if (ret < 0) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, + NULL, "Failed to flush rule"); + return ret; + } + + ret = txgbe_clear_all_l2_tn_filter(dev); + if (ret < 0) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, + NULL, "Failed to flush rule"); + return ret; + } + + txgbe_clear_rss_filter(dev); + + txgbe_filterlist_flush(); + + return 0; +} + const struct rte_flow_ops txgbe_flow_ops = { .validate = txgbe_flow_validate, .create = txgbe_flow_create, .destroy = txgbe_flow_destroy, + .flush = txgbe_flow_flush, };