diff mbox series

[v8,11/18] net/mlx5: add checks for max SIMD bitwidth

Message ID 20201016081320.186775-12-ciara.power@intel.com (mailing list archive)
State Superseded, archived
Delegated to: David Marchand
Headers show
Series add max SIMD bitwidth to EAL | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Power, Ciara Oct. 16, 2020, 8:13 a.m. UTC
When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.

Cc: Matan Azrad <matan@mellanox.com>
Cc: Shahaf Shuler <shahafs@mellanox.com>
Cc: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

---
v4: Updated enum name.
v2: Moved check for max bitwidth into existing check vec
    support function.
---
 drivers/net/mlx5/mlx5_rxtx_vec.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c
index 711dcd35fa..49f1b61ff8 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec.c
+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c
@@ -148,6 +148,8 @@  mlx5_check_vec_rx_support(struct rte_eth_dev *dev)
 	struct mlx5_priv *priv = dev->data->dev_private;
 	uint32_t i;
 
+	if (rte_get_max_simd_bitwidth() < RTE_SIMD_128)
+		return -ENOTSUP;
 	if (!priv->config.rx_vec_en)
 		return -ENOTSUP;
 	if (mlx5_mprq_enabled(dev))