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[v6,04/18] net/axgbe: add checks for max SIMD bitwidth

Message ID 20201015103814.253636-5-ciara.power@intel.com (mailing list archive)
State Superseded, archived
Delegated to: David Marchand
Headers show
Series add max SIMD bitwidth to EAL | expand


Context Check Description
ci/checkpatch success coding style OK

Commit Message

Ciara Power Oct. 15, 2020, 10:38 a.m. UTC
When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled

Cc: Somalapuram Amaranath <asomalap@amd.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Amaranath Somalapuram <asomalap@amd.com>

v4: Updated enum name.
 drivers/net/axgbe/axgbe_rxtx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index bc93becaa5..5386bd86f8 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -557,7 +557,8 @@  int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 	if (!pdata->tx_queues)
 		pdata->tx_queues = dev->data->tx_queues;
-	if (txq->vector_disable)
+	if (txq->vector_disable || rte_get_max_simd_bitwidth()
+			< RTE_SIMD_128)
 		dev->tx_pkt_burst = &axgbe_xmit_pkts;
 #ifdef RTE_ARCH_X86