diff mbox series

[v3,05/18] net/axgbe: add checks for max SIMD bitwidth

Message ID	20200930130415.11211-6-ciara.power@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	David Marchand
Headers	IronPort-SDR: yij+k3BzMuhzTkgZLQJvxnDwz0Iey6LMtYKl1Gy/1UE0Cy4Fo/vqe/FR89DxzjsC9I04JgAfeY I36Pvtv71z7w== IronPort-SDR: g+HXJXzthxpuDGzfreavxWDN4l4t7Se0jOORomTp18NpcWGTdOOgtJ7lLjVO+9Bee52zbHfzJz sqJ3/Qx5/TeA== From: Ciara Power <ciara.power@intel.com> To: dev@dpdk.org Cc: Ciara Power <ciara.power@intel.com>, Somalapuram Amaranath <asomalap@amd.com> Date: Wed, 30 Sep 2020 14:04:01 +0100 Message-Id: <20200930130415.11211-6-ciara.power@intel.com> In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 05/18] net/axgbe: add checks for max SIMD bitwidth Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	add max SIMD bitwidth to EAL \| [v3,00/18] add max SIMD bitwidth to EAL [v3,01/18] eal: add max SIMD bitwidth [v3,02/18] eal: add default SIMD bitwidth values [v3,03/18] doc: add detail on using max SIMD bitwidth [v3,04/18] net/i40e: add checks for max SIMD bitwidth [v3,05/18] net/axgbe: add checks for max SIMD bitwidth [v3,06/18] net/bnxt: add checks for max SIMD bitwidth [v3,07/18] net/enic: add checks for max SIMD bitwidth [v3,08/18] net/fm10k: add checks for max SIMD bitwidth [v3,09/18] net/iavf: add checks for max SIMD bitwidth [v3,10/18] net/ice: add checks for max SIMD bitwidth [v3,11/18] net/ixgbe: add checks for max SIMD bitwidth [v3,12/18] net/mlx5: add checks for max SIMD bitwidth [v3,13/18] net/virtio: add checks for max SIMD bitwidth [v3,14/18] distributor: add checks for max SIMD bitwidth [v3,15/18] member: add checks for max SIMD bitwidth [v3,16/18] efd: add checks for max SIMD bitwidth [v3,17/18] net: add checks for max SIMD bitwidth [v3,18/18] lpm: choose vector path at runtime

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Power, Ciara Sept. 30, 2020, 1:04 p.m. UTC

When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.

Cc: Somalapuram Amaranath <asomalap@amd.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>
---
 drivers/net/axgbe/axgbe_rxtx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Somalapuram, Amaranath Sept. 30, 2020, 1:29 p.m. UTC | #1

-----Original Message-----
From: Ciara Power <ciara.power@intel.com> 
Sent: Wednesday, September 30, 2020 6:34 PM
To: dev@dpdk.org
Cc: Ciara Power <ciara.power@intel.com>; Somalapuram, Amaranath <Amaranath.Somalapuram@amd.com>
Subject: [PATCH v3 05/18] net/axgbe: add checks for max SIMD bitwidth

[CAUTION: External Email]

When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path.

Cc: Somalapuram Amaranath <asomalap@amd.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>
---
 drivers/net/axgbe/axgbe_rxtx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index bc93becaa5..6093ec7279 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -557,7 +557,8 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
        if (!pdata->tx_queues)
                pdata->tx_queues = dev->data->tx_queues;

-       if (txq->vector_disable)
+       if (txq->vector_disable || rte_get_max_simd_bitwidth()
+                       < RTE_MAX_128_SIMD)
                dev->tx_pkt_burst = &axgbe_xmit_pkts;
        else
 #ifdef RTE_ARCH_X86
--
2.17.1

Acked-by: Amaranath Somalapuram <asomalap@amd.com>

diff mbox series

Patch

diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index bc93becaa5..6093ec7279 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -557,7 +557,8 @@  int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 	if (!pdata->tx_queues)
 		pdata->tx_queues = dev->data->tx_queues;
 
-	if (txq->vector_disable)
+	if (txq->vector_disable || rte_get_max_simd_bitwidth()
+			< RTE_MAX_128_SIMD)
 		dev->tx_pkt_burst = &axgbe_xmit_pkts;
 	else
 #ifdef RTE_ARCH_X86