diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index c460271be..7d6d5579c 100644
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -84,6 +84,7 @@ New Features
 
   * Added support for 200G PAM4 link speed.
   * Added support for RSS hash level selection.
+  * Updated HWRM structures to 1.10.1.70 version.
 
 
 Removed Items
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index fc89cc29a..faeaf4b5d 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1364,7 +1364,8 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 	link_info->phy_ver[0] = resp->phy_maj;
 	link_info->phy_ver[1] = resp->phy_min;
 	link_info->phy_ver[2] = resp->phy_bld;
-	link_info->link_signal_mode = rte_le_to_cpu_16(resp->link_signal_mode);
+	link_info->link_signal_mode =
+		rte_le_to_cpu_16(resp->active_fec_signal_mode);
 	link_info->force_pam4_link_speed =
 			rte_le_to_cpu_16(resp->force_pam4_link_speed);
 	link_info->support_pam4_speeds =
@@ -4011,8 +4012,8 @@ int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
 		stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
 		stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
 		stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
-		stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
-		stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
+		stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
+		stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
 	} else {
 		stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
 		stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 20683315e..c55497960 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -216,6 +216,10 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
 					&txr->tx_desc_ring[txr->tx_prod];
 		txbd1->lflags = 0;
 		txbd1->cfa_meta = vlan_tag_flags;
+		/* Legacy tx_bd_long_hi->mss =
+		 * tx_bd_long_hi->kid_or_ts_high_mss
+		 */
+		txbd1->kid_or_ts_high_mss = 0;
 
 		if (txq->vfr_tx_cfa_action)
 			txbd1->cfa_action = txq->vfr_tx_cfa_action;
@@ -235,91 +239,76 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
 				    tx_pkt->outer_l3_len : 0;
 			/* The hdr_size is multiple of 16bit units not 8bit.
 			 * Hence divide by 2.
+			 * Also legacy hdr_size = kid_or_ts_low_hdr_size.
 			 */
-			txbd1->hdr_size = hdr_size >> 1;
-			txbd1->mss = tx_pkt->tso_segsz;
-			RTE_VERIFY(txbd1->mss);
+			txbd1->kid_or_ts_low_hdr_size = hdr_size >> 1;
+			txbd1->kid_or_ts_high_mss = tx_pkt->tso_segsz;
+			RTE_VERIFY(txbd1->kid_or_ts_high_mss);
 
 		} else if ((tx_pkt->ol_flags & PKT_TX_OIP_IIP_TCP_UDP_CKSUM) ==
 			   PKT_TX_OIP_IIP_TCP_UDP_CKSUM) {
 			/* Outer IP, Inner IP, Inner TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_TIP_IP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_OIP_IIP_TCP_CKSUM) ==
 			   PKT_TX_OIP_IIP_TCP_CKSUM) {
 			/* Outer IP, Inner IP, Inner TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_TIP_IP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_OIP_IIP_UDP_CKSUM) ==
 			   PKT_TX_OIP_IIP_UDP_CKSUM) {
 			/* Outer IP, Inner IP, Inner TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_TIP_IP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_IIP_TCP_UDP_CKSUM) ==
 			   PKT_TX_IIP_TCP_UDP_CKSUM) {
 			/* (Inner) IP, (Inner) TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_IP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_IIP_UDP_CKSUM) ==
 			   PKT_TX_IIP_UDP_CKSUM) {
 			/* (Inner) IP, (Inner) TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_IP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_IIP_TCP_CKSUM) ==
 			   PKT_TX_IIP_TCP_CKSUM) {
 			/* (Inner) IP, (Inner) TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_IP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_OIP_TCP_UDP_CKSUM) ==
 			   PKT_TX_OIP_TCP_UDP_CKSUM) {
 			/* Outer IP, (Inner) TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_TIP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_OIP_UDP_CKSUM) ==
 			   PKT_TX_OIP_UDP_CKSUM) {
 			/* Outer IP, (Inner) TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_TIP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_OIP_TCP_CKSUM) ==
 			   PKT_TX_OIP_TCP_CKSUM) {
 			/* Outer IP, (Inner) TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_FLG_TIP_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_OIP_IIP_CKSUM) ==
 			   PKT_TX_OIP_IIP_CKSUM) {
 			/* Outer IP, Inner IP CSO */
 			txbd1->lflags |= TX_BD_FLG_TIP_IP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_TCP_UDP_CKSUM) ==
 			   PKT_TX_TCP_UDP_CKSUM) {
 			/* TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_TCP_CKSUM) ==
 			   PKT_TX_TCP_CKSUM) {
 			/* TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_UDP_CKSUM) ==
 			   PKT_TX_UDP_CKSUM) {
 			/* TCP/UDP CSO */
 			txbd1->lflags |= TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_IP_CKSUM) ==
 			   PKT_TX_IP_CKSUM) {
 			/* IP CSO */
 			txbd1->lflags |= TX_BD_LONG_LFLAGS_IP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_OUTER_IP_CKSUM) ==
 			   PKT_TX_OUTER_IP_CKSUM) {
 			/* IP CSO */
 			txbd1->lflags |= TX_BD_LONG_LFLAGS_T_IP_CHKSUM;
-			txbd1->mss = 0;
 		} else if ((tx_pkt->ol_flags & PKT_TX_IEEE1588_TMST) ==
 			   PKT_TX_IEEE1588_TMST) {
 			/* PTP */
 			txbd1->lflags |= TX_BD_LONG_LFLAGS_STAMP;
-			txbd1->mss = 0;
 		}
 	} else {
 		txbd->flags_type |= TX_BD_SHORT_TYPE_TX_BD_SHORT;
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 8dfc14b1e..72100919d 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -392,7 +392,11 @@ struct cmd_nums {
 	#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE            UINT32_C(0xb7)
 	#define HWRM_PORT_PHY_MDIO_BUS_RELEASE            UINT32_C(0xb8)
 	#define HWRM_PORT_QSTATS_EXT_PFC_WD               UINT32_C(0xb9)
-	#define HWRM_PORT_ECN_QSTATS                      UINT32_C(0xba)
+	/* Reserved. */
+	#define HWRM_RESERVED7                            UINT32_C(0xba)
+	#define HWRM_PORT_TX_FIR_CFG                      UINT32_C(0xbb)
+	#define HWRM_PORT_TX_FIR_QCFG                     UINT32_C(0xbc)
+	#define HWRM_PORT_ECN_QSTATS                      UINT32_C(0xbd)
 	#define HWRM_FW_RESET                             UINT32_C(0xc0)
 	#define HWRM_FW_QSTATUS                           UINT32_C(0xc1)
 	#define HWRM_FW_HEALTH_CHECK                      UINT32_C(0xc2)
@@ -619,7 +623,7 @@ struct cmd_nums {
 	#define HWRM_FUNC_HOST_PF_IDS_QUERY               UINT32_C(0x197)
 	/* Queries extended stats per function */
 	#define HWRM_FUNC_QSTATS_EXT                      UINT32_C(0x198)
-	/* Queries extended statistics context */
+	/* Queries extended statitics context */
 	#define HWRM_STAT_EXT_CTX_QUERY                   UINT32_C(0x199)
 	/* Experimental */
 	#define HWRM_SELFTEST_QLIST                       UINT32_C(0x200)
@@ -677,6 +681,12 @@ struct cmd_nums {
 	/* Experimental */
 	#define HWRM_TF_TBL_TYPE_SET                      UINT32_C(0x2db)
 	/* Experimental */
+	#define HWRM_TF_TBL_TYPE_BULK_GET                 UINT32_C(0x2dc)
+	/* Experimental */
+	#define HWRM_TF_CTXT_MEM_ALLOC                    UINT32_C(0x2e2)
+	/* Experimental */
+	#define HWRM_TF_CTXT_MEM_FREE                     UINT32_C(0x2e3)
+	/* Experimental */
 	#define HWRM_TF_CTXT_MEM_RGTR                     UINT32_C(0x2e4)
 	/* Experimental */
 	#define HWRM_TF_CTXT_MEM_UNRGTR                   UINT32_C(0x2e5)
@@ -860,6 +870,11 @@ struct ret_codes {
 	 * may try again later.
 	 */
 	#define HWRM_ERR_CODE_BUSY                         UINT32_C(0x10)
+	/*
+	 * This error code is reported by Firmware when an operation requested
+	 * by the host is not allowed due to a secure lock violation.
+	 */
+	#define HWRM_ERR_CODE_RESOURCE_LOCKED              UINT32_C(0x11)
 	/*
 	 * This value indicates that the HWRM response is in TLV format and
 	 * should be interpreted as one or more TLVs starting with the
@@ -947,8 +962,8 @@ struct hwrm_err_output {
 #define HWRM_VERSION_MINOR 10
 #define HWRM_VERSION_UPDATE 1
 /* non-zero means beta version */
-#define HWRM_VERSION_RSVD 56
-#define HWRM_VERSION_STR "1.10.1.56"
+#define HWRM_VERSION_RSVD 70
+#define HWRM_VERSION_STR "1.10.1.70"
 
 /****************
  * hwrm_ver_get *
@@ -1499,6 +1514,645 @@ struct hwrm_ver_get_output {
 	uint8_t	valid;
 } __rte_packed;
 
+/* cfa_bds_read_cmd_data_msg (size:128b/16B) */
+struct cfa_bds_read_cmd_data_msg {
+	/* This value selects the format for the mid-path command for the CFA. */
+	uint8_t	opcode;
+	/*
+	 * This is read command. From 32 to 128B can be read from a table
+	 * using this command.
+	 */
+	#define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
+	#define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \
+		CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
+	/* This value selects the table type to be acted upon. */
+	uint8_t	table_type;
+	/* This value selects the table type to be acted upon. */
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf)
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT   0
+	/* This command acts on the action table of the specified scope. */
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION  UINT32_C(0x0)
+	/* This command acts on the exact match table of the specified scope. */
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM      UINT32_C(0x1)
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \
+		CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
+	/* This value selects which table scope will be accessed. */
+	uint8_t	table_scope;
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+	/*
+	 * This value identifies the number of 32B units will be accessed. A
+	 * value of zero is invalid. Maximum value is 4.
+	 */
+	uint8_t	data_size;
+	#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+	#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
+	/* This is the 32B index into the selected table to access. */
+	uint32_t	table_index;
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
+	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+	/*
+	 * This is the 64b host address where you want the data returned to. The
+	 * data will be written to the same function as the one that owns the SQ
+	 * this command is read from. The bottom two bits of this value must be
+	 * zero. The size of the write is controlled by the data_size field.
+	 */
+	uint64_t	host_address;
+} __rte_packed;
+
+/* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
+struct cfa_bds_write_cmd_data_msg {
+	/* This value selects the format for the mid-path command for the CFA. */
+	uint8_t	opcode;
+	/*
+	 * This is write command. From 32 to 128B can be written to a table
+	 * using this command.
+	 */
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \
+		CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
+	/* This value selects the table type to be acted upon. */
+	uint8_t	write_thru_table_type;
+	/* This value selects the table type to be acted upon. */
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf)
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT   0
+	/* This command acts on the action table of the specified scope. */
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION  UINT32_C(0x0)
+	/* This command acts on the exact match table of the specified scope. */
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM      UINT32_C(0x1)
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \
+		CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
+	/*
+	 * Indicates write-through control. Indicates write-through when set,
+	 * or write back when cleared.
+	 */
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU       UINT32_C(0x10)
+	/* This value selects which table scope will be accessed. */
+	uint8_t	table_scope;
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+	/*
+	 * This value identifies the number of 32B units will be accessed. A
+	 * value of zero is invalid. Maximum value is 4.
+	 */
+	uint8_t	data_size;
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
+	/* This is the 32B index into the selected table to access. */
+	uint32_t	table_index;
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
+	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+	uint32_t	unused0;
+	uint32_t	unused1;
+	/*
+	 * This is the data to be written. Data length is determined by the
+	 * data_size field. The bd_cnt in the encapsulating BD must also be set
+	 * correctly to ensure that the BD is processed correctly and the full
+	 * WRITE_CMD message is extracted from the BD.
+	 */
+	uint32_t	dta[32];
+} __rte_packed;
+
+/* cfa_bds_read_clr_cmd_data_msg (size:192b/24B) */
+struct cfa_bds_read_clr_cmd_data_msg {
+	/* This value selects the format for the mid-path command for the CFA. */
+	uint8_t	opcode;
+	/*
+	 * This is read-clear command. 32B can be read from a table and
+	 * a 16b mask can be used to clear specific 16b units after the
+	 * read as an atomic operation.
+	 */
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \
+		CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
+	/* This value selects the table type to be acted upon. */
+	uint8_t	table_type;
+	/* This value selects the table type to be acted upon. */
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf)
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT   0
+	/* This command acts on the action table of the specified scope. */
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION  UINT32_C(0x0)
+	/* This command acts on the exact match table of the specified scope. */
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM      UINT32_C(0x1)
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \
+		CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
+	/* This value selects which table scope will be accessed. */
+	uint8_t	table_scope;
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+	uint8_t	unused0;
+	/* This is the 32B index into the selected table to access. */
+	uint32_t	table_index;
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \
+		UINT32_C(0x3ffffff)
+	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+	/*
+	 * This is the 64b host address where you want the data returned to. The
+	 * data will be written to the same function as the one that owns the SQ
+	 * this command is read from. The bottom two bits of this value must be
+	 * zero. The size of the write is controlled by the data_size field.
+	 */
+	uint64_t	host_address;
+	/*
+	 * This is active high clear mask for the 32B of data that this command
+	 * can read. Bit 0 of the field will clear bits 15:0 of the first word
+	 * of data read when set to '1'.
+	 */
+	uint16_t	clear_mask;
+	uint16_t	unused1[3];
+} __rte_packed;
+
+/* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
+struct cfa_bds_em_insert_cmd_data_msg {
+	/* This value selects the format for the mid-path command for the CFA. */
+	uint8_t	opcode;
+	/*
+	 * An exact match table insert will be attempted into the table.
+	 * If there is a free location in the bucket, the payload will
+	 * be written to the bucket.
+	 */
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \
+		CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
+	/*
+	 * Indicates write-through control. Indicates write-through when set,
+	 * or write back when cleared.
+	 */
+	uint8_t	write_thru;
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK    UINT32_C(0xf)
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT     0
+	/*
+	 * Indicates write-through control. Indicates write-through when set,
+	 * or write back when cleared.
+	 */
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU     UINT32_C(0x10)
+	/* This value selects which table scope will be accessed. */
+	uint8_t	table_scope;
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+	/*
+	 * This value identifies the number of 32B units will be accessed. A
+	 * value of zero is invalid. Maximum value is 4.
+	 */
+	uint8_t	data_size;
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
+	/* This is the 32B index into the selected table to access. */
+	uint32_t	table_index;
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \
+		UINT32_C(0x3ffffff)
+	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+	/*
+	 * This is the 64b host address where you want the data returned to. The
+	 * data will be written to the same function as the one that owns the SQ
+	 */
+	uint64_t	host_address;
+	/*
+	 * This is the Exact Match Lookup Record. Data length is determined by
+	 * the data_size field. The bd_cnt in the encapsulating BD must also be
+	 */
+	uint32_t	dta[32];
+} __rte_packed;
+
+/* cfa_bds_em_delete_cmd_data_msg (size:192b/24B) */
+struct cfa_bds_em_delete_cmd_data_msg {
+	/* This value selects the format for the mid-path command for the CFA. */
+	uint8_t	opcode;
+	/* An exact match table delete will be attempted. */
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \
+		CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
+	/*
+	 * Indicates write-through control. Indicates write-through when set,
+	 * or write back when cleared.
+	 */
+	uint8_t	write_thru;
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK    UINT32_C(0xf)
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT     0
+	/*
+	 * Indicates write-through control. Indicates write-through when set,
+	 * or write back when cleared.
+	 */
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU     UINT32_C(0x10)
+	/* This value selects which table scope will be accessed. */
+	uint8_t	table_scope;
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+	/*
+	 * This value identifies the number of 32B units will be accessed. A
+	 * value of zero is invalid. Maximum value is 4.
+	 */
+	uint8_t	data_size;
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
+	uint32_t	unused0;
+	/*
+	 * This is the 64b host address where you want the data returned to. The
+	 * data will be written to the same function as the one that owns the SQ
+	 */
+	uint64_t	host_address;
+	/*
+	 * This is the Exact Match Lookup Record. Data length is determined by
+	 * the data_size field. The bd_cnt in the encapsulating BD must also be
+	 */
+	uint64_t	dta;
+} __rte_packed;
+
+/* cfa_bds_invalidate_cmd_data_msg (size:64b/8B) */
+struct cfa_bds_invalidate_cmd_data_msg {
+	/* This value selects the format for the mid-path command for the CFA. */
+	uint8_t	opcode;
+	/*
+	 * The specified table area will be invalidated. If it is needed.
+	 * again, it will be read from the backing store.
+	 */
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \
+		CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
+	/* This value selects the table type to be acted upon. */
+	uint8_t	table_type;
+	/* This value selects the table type to be acted upon. */
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf)
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT   0
+	/* This command acts on the action table of the specified scope. */
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \
+		UINT32_C(0x0)
+	/* This command acts on the exact match table of the specified scope. */
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \
+		UINT32_C(0x1)
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \
+		CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
+	/* This value selects which table scope will be accessed. */
+	uint8_t	table_scope;
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+	uint8_t	unused0;
+	/* This is the 32B index into the selected table to access. */
+	uint32_t	table_index;
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \
+		UINT32_C(0x3ffffff)
+	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+} __rte_packed;
+
+/* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
+struct cfa_bds_event_collect_cmd_data_msg {
+	/* This value selects the format for the mid-path command for the CFA. */
+	uint8_t	opcode;
+	/* Reads notification messages from the Host Notification Queue. */
+	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \
+		UINT32_C(0x6)
+	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \
+		CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
+	uint8_t	unused0;
+	/* This value selects which table scope will be accessed. */
+	uint8_t	table_scope;
+	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \
+		UINT32_C(0x1f)
+	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+	/*
+	 * This value identifies the number of 32B units will be accessed. A
+	 * value of zero is invalid. Maximum value is 4.
+	 */
+	uint8_t	data_size;
+	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
+	uint32_t	unused1;
+	/*
+	 * This is the 64b host address where you want the data returned to. The
+	 * data will be written to the same function as the one that owns the SQ
+	 */
+	uint64_t	host_address;
+} __rte_packed;
+
+/* ce_bds_add_data_msg (size:512b/64B) */
+struct ce_bds_add_data_msg {
+	uint32_t	version_algorithm_kid_opcode;
+	/*
+	 * This value selects the operation for the mid-path command for the
+	 * crypto blocks.
+	 */
+	#define CE_BDS_ADD_DATA_MSG_OPCODE_MASK               UINT32_C(0xf)
+	#define CE_BDS_ADD_DATA_MSG_OPCODE_SFT                0
+	/*
+	 * This is the add command. Using this opcode, Host Driver can add
+	 * information required for kTLS processing. The information is
+	 * updated in the CFCK context.
+	 */
+	#define CE_BDS_ADD_DATA_MSG_OPCODE_ADD                  UINT32_C(0x1)
+	#define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \
+		CE_BDS_ADD_DATA_MSG_OPCODE_ADD
+	/*
+	 * This field is the Crypto Context ID. The KID is used to store
+	 * information used by the associated kTLS offloaded connection.
+	 */
+	#define CE_BDS_ADD_DATA_MSG_KID_MASK \
+		UINT32_C(0xfffff0)
+	#define CE_BDS_ADD_DATA_MSG_KID_SFT                   4
+	/*
+	 * Currently only two algorithms are supported, AES_GCM_128 and
+	 * AES_GCM_256. Additional bits for future growth.
+	 */
+	#define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \
+		UINT32_C(0xf000000)
+	#define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT             24
+	/* AES_GCM_128 Algorithm */
+	#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
+		UINT32_C(0x1000000)
+	/* AES_GCM_256 Algorithm */
+	#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
+		UINT32_C(0x2000000)
+	/*
+	 * Version number of TLS connection. HW will provide registers that
+	 * converts the 4b encoded version number to 16b of actual version
+	 * number in the TLS Header. * Initialized --> By mid-path command *
+	 * Updated --> Never though another mid-path command will result in an
+	 * update.
+	 */
+	#define CE_BDS_ADD_DATA_MSG_VERSION_MASK \
+		UINT32_C(0xf0000000)
+	#define CE_BDS_ADD_DATA_MSG_VERSION_SFT               28
+	/* TLS1.2 Version */
+	#define CE_BDS_ADD_DATA_MSG__TLS1_2 \
+		(UINT32_C(0x0) << 28)
+	/* TLS1.3 Version */
+	#define CE_BDS_ADD_DATA_MSG__TLS1_3 \
+		(UINT32_C(0x1) << 28)
+	#define CE_BDS_ADD_DATA_MSG__LAST \
+		CE_BDS_ADD_DATA_MSG__TLS1_3
+	/*
+	 * Command Type in the TLS header. HW will provide registers that
+	 * converts the 3b encoded command type to 8b of actual command type in
+	 * the TLS Header. * Initialized --> By mid-path command * Updated -->
+	 * Never though another mid-path command will result in an update
+	 */
+	uint8_t	cmd_type;
+	#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
+	#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
+	/* Application */
+	#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP   UINT32_C(0x0)
+	#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
+		CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
+	uint8_t	unused0[3];
+	/*
+	 * Salt is part of the nonce that is used as the Initial Vector (IV) in
+	 * AES-GCM cipher suites. These are exchanged as part of the handshake
+	 * process and is either the client_write_iv (when the client is
+	 * sending) or server_write_iv (when the server is sending). In
+	 * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
+	 * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
+	 * is zero padded to 12B and then xor'ed with the 4B of salt to generate
+	 * the 12B of IV. This value is initialized by this mid-path command.
+	 */
+	uint32_t	salt;
+	uint32_t	unused1;
+	/*
+	 * This field keeps track of the TCP sequence number that is expected as
+	 * the first byte in the next TCP packet. This field is calculated by HW
+	 * using the output of the parser. The field is initialized as part of
+	 * the Mid-path BD download/update of a kTLS connection. For every TCP
+	 * packet processed, TCE HW will update the value to Current packet TCP
+	 * sequence number + Current packet TCP Payload Length.
+	 */
+	uint32_t	pkt_tcp_seq_num;
+	/*
+	 * This field maintains the TCP sequence number of the first byte in the
+	 * header of the active TLS record. This field is initialized as part of
+	 * the Mid-path BD download/update of a kTLS connection. For every
+	 * record that is processed, TCE HW copies the value from the
+	 * next_tls_header_tcp_seq_num field.
+	 */
+	uint32_t	tls_header_tcp_seq_num;
+	/*
+	 * This is sequence number for the TLS record in a particular session.
+	 * In TLS1.2, record sequence number is part of the Associated Data (AD)
+	 * in the AEAD algorithm. In TLS1.3, record sequence number is part of
+	 * the Initial Vector (IV). The field is initialized as part of the
+	 * mid-path BD download/update of a kTLS connection. TCE HW increments
+	 * the field after that for every record processed as it parses the TCP
+	 * packet.
+	 */
+	uint32_t	record_seq_num[2];
+	/*
+	 * Key used for encrypting or decrypting TLS records. The Key is
+	 * exchanged during the hand-shake protocol by the client-server and
+	 * provided to HW through this mid-path BD.
+	 */
+	uint32_t	session_key[8];
+} __rte_packed;
+
+/* ce_bds_delete_data_msg (size:64b/8B) */
+struct ce_bds_delete_data_msg {
+	uint32_t	kid_opcode;
+	/*
+	 * This value selects the operation for the mid-path command for the
+	 * crypto blocks.
+	 */
+	#define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK  UINT32_C(0xf)
+	#define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT   0
+	/*
+	 * This is the delete command. Using this opcode, the host Driver
+	 * can remove a key context from the CFCK. If context is deleted
+	 * and packets with the same KID come through the pipeline, the
+	 * following actions are taken. For transmit packets, no crypto
+	 * operation will be performed, payload will be zero'ed out. For
+	 * receive packets, no crypto operation will be performed,
+	 * payload will be unmodified.
+	 */
+	#define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE  UINT32_C(0x2)
+	#define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \
+		CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
+	/*
+	 * This field is the Crypto Context ID. The KID is used to store
+	 * information used by the associated kTLS offloaded connection.
+	 */
+	#define CE_BDS_DELETE_DATA_MSG_KID_MASK     UINT32_C(0xfffff0)
+	#define CE_BDS_DELETE_DATA_MSG_KID_SFT      4
+	uint32_t	unused0;
+} __rte_packed;
+
+/* ce_bds_resync_resp_ack_msg (size:128b/16B) */
+struct ce_bds_resync_resp_ack_msg {
+	uint32_t	resync_status_kid_opcode;
+	/*
+	 * This value selects the operation for the mid-path command for the
+	 * crypto blocks.
+	 */
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK       UINT32_C(0xf)
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT        0
+	/*
+	 * This command is used by the driver as a response to the resync
+	 * request sent by the crypto engine.
+	 */
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC       UINT32_C(0x3)
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \
+		CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
+	/*
+	 * This field is the Crypto Context ID. The KID is used to store
+	 * information used by the associated kTLS offloaded connection.
+	 */
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK          UINT32_C(0xfffff0)
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT           4
+	/*
+	 * This field indicates if the resync request resulted in a success or
+	 * a failure.
+	 */
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \
+		UINT32_C(0x1000000)
+	/*
+	 * An ACK indicates that the driver was able to find the TLS record
+	 * associated with TCP sequence number provided by the HW
+	 */
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \
+		(UINT32_C(0x0) << 24)
+	#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \
+		CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
+	/*
+	 * This field is the echo of the TCP sequence number provided in the
+	 * resync request by the HW. If HW sent multiple resync requests, it
+	 * only tracks the latest TCP sequence number. When the response from
+	 * the Driver doesn't match the latest request, HW will drop the resync
+	 * response.
+	 */
+	uint32_t	resync_record_tcp_seq_num;
+	/*
+	 * This field indicates the TLS record sequence number associated with
+	 * the resync request. HW will take this number and add the delta records
+	 * it has found since sending the resync request, update the context and
+	 * resume decrypting records.
+	 */
+	uint32_t	resync_record_seq_num[2];
+} __rte_packed;
+
+/* ce_bds_resync_resp_nack_msg (size:64b/8B) */
+struct ce_bds_resync_resp_nack_msg {
+	uint32_t	resync_status_kid_opcode;
+	/*
+	 * This value selects the operation for the mid-path command for the
+	 * crypto blocks.
+	 */
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK       UINT32_C(0xf)
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT        0
+	/*
+	 * This command is used by the driver as a response to the resync
+	 * request sent by the crypto engine.
+	 */
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC       UINT32_C(0x3)
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \
+		CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
+	/*
+	 * This field is the Crypto Context ID. The KID is used to store
+	 * information used by the associated kTLS offloaded connection.
+	 */
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \
+		UINT32_C(0xfffff0)
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT           4
+	/*
+	 * This field indicates if the resync request resulted in a success or
+	 * a failure.
+	 */
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \
+		UINT32_C(0x1000000)
+	/*
+	 * An NAK indicates that the driver wasn't able to find the TLS
+	 * record associated with TCP sequence number provided by the HW
+	 */
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \
+		(UINT32_C(0x1) << 24)
+	#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \
+		CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
+	/*
+	 * This field is the echo of the TCP sequence number provided in the
+	 * resync request by the HW. If HW sent multiple resync requests, it
+	 * only tracks the latest TCP sequence number. When the response from
+	 * the Driver doesn't match the latest request, HW will drop the resync
+	 * response.
+	 */
+	uint32_t	resync_record_tcp_seq_num;
+} __rte_packed;
+
+/* crypto_presync_bd_cmd (size:256b/32B) */
+struct crypto_presync_bd_cmd {
+	uint8_t	flags;
+	/*
+	 * Typically, presync BDs are used for packet retransmissions. Source
+	 * port sends all the packets in order over the network to destination
+	 * port and packets get dropped in the network. The destination port
+	 * will request retranmission of dropped packets and source port driver
+	 * will send presync BD to setup the transmitter appropriately. It will
+	 * provide the start and end TCP sequence number of the data to be
+	 * transmitted. HW keeps two sets of context variable, one for in order
+	 * traffic and one for retransmission traffic. HW is designed to
+	 * transmit everything posted in the presync BD and return to in order
+	 * mode after that. No inorder context variables are updated in the
+	 * process. There is a special case where packets can be dropped
+	 * between the TCP stack and Device Driver (Berkley Packet Filter for
+	 * ex) and HW still needs to transmit rest of the traffic. In this
+	 * mode, driver will send a presync BD as if it is a retransmission but
+	 * at the end of the transmission, the in order variables need to be
+	 * updated. This flag is used by driver to indicate that in order
+	 * variables needs to be updated at the end of completing the task
+	 * associated with the presync BD.
+	 */
+	#define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
+		UINT32_C(0x1)
+	uint8_t	unused0;
+	uint16_t	unused1;
+	/*
+	 * This field maintains the TCP sequence number of the first byte in the
+	 * Header of the active TLS record. This field is set to 0 during
+	 * mid-path BD updates, but is set to correct value when a presync BD is
+	 * detected. For every record that is processed, the value from the
+	 * next_tls_header_tcp_seq_num field is copied.
+	 */
+	uint32_t	header_tcp_seq_num;
+	/*
+	 * When a retransmitted packet has a TLS authentication TAG present and
+	 * the data spans multiple TCP Packets, HW is required to read the entire
+	 * record to recalculate the TAG but only transmit what is required. This
+	 * field is the start TCP sequence number of the packet(s) that need to
+	 * be re-transmitted. This field is initialized to 0 during Mid-path BD
+	 * add command and initialized to value provided by the driver when
+	 * Pre-sync BD is detected. This field is never updated unless another
+	 * Pre-sync BD signaling a new retransmission is scheduled.
+	 */
+	uint32_t	start_tcp_seq_num;
+	/*
+	 * When a retransmitted packet has a TLS authentication TAG present and
+	 * the data spans multiple TCP Packets, HW is required to read the
+	 * entire record to recalculate the TAG but only transmit what is
+	 * required. This field is the end TCP sequence number of the packet(s)
+	 * that need to be re-transmitted. This field is initialized to 0 during
+	 * Mid-path BD add command and initialized to value provided by the
+	 * driver when Pre-sync BD is detected. This field is never updated
+	 * unless another Pre-sync BD signaling a new retransmission is
+	 * scheduled.
+	 */
+	uint32_t	end_tcp_seq_num;
+	/*
+	 * For TLS1.2, an explicit nonce is used as part of the IV (concatenated
+	 * with the SALT). For retans packets, this field is extracted from the
+	 * TLS record, field right after the TLS Header and stored in the
+	 * context. This field needs to be stored in context as TCP segmentation
+	 * could have split the field into multiple TCP packets. This value is
+	 * initialized to 0 when presync BD is detected by taking the value from
+	 * the first TLS header. When subsequent TLS Headers are detected, the
+	 * value is extracted from packet.
+	 */
+	uint32_t	explicit_nonce[2];
+	/*
+	 * This is sequence number for the TLS record in a particular session. In
+	 * TLS1.2, record sequence number is part of the Associated Data (AD) in
+	 * the AEAD algorithm. In TLS1.3, record sequence number is part of the
+	 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
+	 * download. Is initialized to correct value when a pre-sync BD is
+	 * detected. TCE HW increments the field after that for every record
+	 * processed as it parses the TCP packet. Subsequent pre-sync BDs
+	 * delivering more retransmission instruction will also update this
+	 * field.
+	 */
+	uint32_t	record_seq_num[2];
+} __rte_packed;
+
 /* bd_base (size:64b/8B) */
 struct bd_base {
 	uint8_t	type;
@@ -1530,6 +2184,16 @@ struct bd_base {
 	 * RX Producer Assembly Buffer Descriptor.
 	 */
 	#define BD_BASE_TYPE_RX_PROD_AGG        UINT32_C(0x6)
+	/*
+	 * Indicates that this BD is used to issue a command to one of
+	 * the mid-path destinations.
+	 */
+	#define BD_BASE_TYPE_TX_BD_MP_CMD       UINT32_C(0x8)
+	/*
+	 * Indicates that this BD is used to issue a cryptographic pre-
+	 * sync command through the fast path and destined for TCE.
+	 */
+	#define BD_BASE_TYPE_TX_BD_PRESYNC_CMD  UINT32_C(0x9)
 	/*
 	 * Indicates that this BD is 32B long and is used for
 	 * normal L2 packet transmission.
@@ -1642,7 +2306,12 @@ struct tx_bd_short {
 	 * used for any data that the driver wants to associate with the
 	 * transmit BD.
 	 *
-	 * This field must be valid on the first BD of a packet.
+	 * This field must be valid on the first BD of a packet. If completion
+	 * coalescing is enabled on the TX ring, it is suggested that the driver
+	 * populate the opaque field to indicate the specific TX ring with which
+	 * the completion is associated, then utilize the opaque and sq_cons_idx
+	 * fields in the coalesced completion record to determine the specific
+	 * packets that are to be completed on that ring.
 	 */
 	uint32_t	opaque;
 	/*
@@ -1745,11 +2414,16 @@ struct tx_bd_long {
 	 */
 	uint16_t	len;
 	/*
-	 * The opaque data field is pass through to the completion and can be
+	 * The opaque data field is passed through to the completion and can be
 	 * used for any data that the driver wants to associate with the
 	 * transmit BD.
 	 *
-	 * This field must be valid on the first BD of a packet.
+	 * This field must be valid on the first BD of a packet. If completion
+	 * coalescing is enabled on the TX ring, it is suggested that the driver
+	 * populate the opaque field to indicate the specific TX ring with which
+	 * the completion is associated, then utilize the opaque and sq_cons_idx
+	 * fields in the coalesced completion record to determine the specific
+	 * packets that are to be completed on that ring.
 	 */
 	uint32_t	opaque;
 	/*
@@ -1802,7 +2476,7 @@ struct tx_bd_long_hi {
 	#define TX_BD_LONG_LFLAGS_NOCRC              UINT32_C(0x4)
 	/*
 	 * If set to 1, the device will record the time at which the packet
-	 * was actually transmitted at the TX MAC.
+	 * was actually transmitted at the TX MAC for 2-step time sync.
 	 *
 	 * This bit must be valid on the first BD of a packet.
 	 */
@@ -1829,9 +2503,9 @@ struct tx_bd_long_hi {
 	 * Send Offload) processing for both normal or encapsulated
 	 * packets, which is a form of TCP segmentation. When this bit
 	 * is 1, the hdr_size and mss fields must be valid. The driver
-	 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
-	 * flags since the controller will replace the appropriate
-	 * checksum fields for segmented packets.
+	 * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
+	 * tcp_udp_chksum flags since the controller will replace the
+	 * appropriate checksum fields for segmented packets.
 	 *
 	 * When this bit is 1, the hdr_size and mss fields must be valid.
 	 */
@@ -1868,7 +2542,47 @@ struct tx_bd_long_hi {
 	 * packet. Packet must be a valid FCoE format packet.
 	 */
 	#define TX_BD_LONG_LFLAGS_FCOE_CRC           UINT32_C(0x200)
-	uint16_t	hdr_size;
+	/*
+	 * If set to '1', then the timestamp from the BD is used. If cleared
+	 * to 0, then TWE provides the timestamp.
+	 */
+	#define TX_BD_LONG_LFLAGS_BD_TS_EN           UINT32_C(0x400)
+	/*
+	 * If set to '1', this operation will cause a trace capture in each
+	 * block it passes through.
+	 */
+	#define TX_BD_LONG_LFLAGS_DEBUG_TRACE        UINT32_C(0x800)
+	/*
+	 * If set to '1', the device will record the time at which the packet
+	 * was actually transmitted at the TX MAC for 1-step time sync. This
+	 * bit must be valid on the first BD of a packet.
+	 */
+	#define TX_BD_LONG_LFLAGS_STAMP_1STEP        UINT32_C(0x1000)
+	/*
+	 * If set to '1', the controller replaces the Outer-tunnel IP checksum
+	 * field with hardware calculated IP checksum for the IP header of the
+	 * packet associated with this descriptor. For outer UDP checksum, it
+	 * will be the following behavior for all cases independent of settings
+	 * of inner LSO and checksum offload BD flags. If outer UDP checksum
+	 * is 0, then do not update it. If outer UDP checksum is non zero, then
+	 * the hardware should compute and update it.
+	 */
+	#define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM       UINT32_C(0x2000)
+	/*
+	 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
+	 * header will not be modified during LSO operations. If set to one
+	 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
+	 * incremented for each subsequent segment of an LSO operation. The
+	 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
+	 * packet.
+	 */
+	#define TX_BD_LONG_LFLAGS_OT_IPID            UINT32_C(0x4000)
+	/*
+	 * If set to '1', When set to 1, KTLS encryption will be enabled for
+	 * the packet.
+	 */
+	#define TX_BD_LONG_LFLAGS_CRYPTO_EN          UINT32_C(0x8000)
+	uint16_t	kid_or_ts_low_hdr_size;
 	/*
 	 * When LSO is '1', this field must contain the offset of the
 	 * TCP payload from the beginning of the packet in as
@@ -1878,9 +2592,16 @@ struct tx_bd_long_hi {
 	 *
 	 * This value must be valid on the first BD of a packet.
 	 */
-	#define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
-	#define TX_BD_LONG_HDR_SIZE_SFT 0
-	uint32_t	mss;
+	#define TX_BD_LONG_HDR_SIZE_MASK     UINT32_C(0x1ff)
+	#define TX_BD_LONG_HDR_SIZE_SFT      0
+	/*
+	 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
+	 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the
+	 * 20-bit KID.
+	 */
+	#define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
+	#define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
+	uint32_t	kid_or_ts_high_mss;
 	/*
 	 * This is the MSS value that will be used to do the LSO processing.
 	 * The value is the length in bytes of the TCP payload for each
@@ -1888,9 +2609,22 @@ struct tx_bd_long_hi {
 	 *
 	 * This value must be valid on the first BD of a packet.
 	 */
-	#define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
-	#define TX_BD_LONG_MSS_SFT 0
-	uint16_t	unused2;
+	#define TX_BD_LONG_MSS_MASK           UINT32_C(0x7fff)
+	#define TX_BD_LONG_MSS_SFT            0
+	/*
+	 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
+	 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
+	 * of this field contain the upper 13 bits of the 20-bit KID.
+	 */
+	#define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
+	#define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
+	/*
+	 * This value selects bits 25:16 of the CFA action to perform on the
+	 * packet. See the cfa_action field for more information.
+	 */
+	uint16_t	cfa_action_high;
+	#define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
+	#define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
 	/*
 	 * This value selects a CFA action to perform on the packet.
 	 * Set this value to zero if no CFA action is desired.
@@ -2025,7 +2759,12 @@ struct tx_bd_long_inline {
 	/*
 	 * The opaque data field is passed through to the completion and can be
 	 * used for any data that the driver wants to associate with the transmit
-	 * BD.
+	 * BD. This field must be valid on the first BD of a packet. If
+	 * completion coalescing is enabled on the TX ring, it is suggested that
+	 * the driver populate the opaque field to indicate the specific TX ring
+	 * with which the completion is associated, then utilize the opaque and
+	 * sq_cons_idx fields in the coalesced completion record to determine
+	 * the specific packets that are to be completed on that ring.
 	 *
 	 * This field must be valid on the first BD of a packet.
 	 */
@@ -2063,7 +2802,8 @@ struct tx_bd_long_inline {
 	#define TX_BD_LONG_INLINE_LFLAGS_NOCRC              UINT32_C(0x4)
 	/*
 	 * If set to 1, the device will record the time at which the packet
-	 * was actually transmitted at the TX MAC.
+	 * was actually transmitted at the TX MAC for 2-step time sync. This
+	 * bit must be valid on the first BD of a packet.
 	 */
 	#define TX_BD_LONG_INLINE_LFLAGS_STAMP              UINT32_C(0x8)
 	/*
@@ -2092,9 +2832,73 @@ struct tx_bd_long_inline {
 	 * packet. Packet must be a valid FCoE format packet.
 	 */
 	#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC           UINT32_C(0x200)
-	uint16_t	unused2;
-	uint32_t	unused3;
-	uint16_t	unused4;
+	/*
+	 * If set to '1', then the timestamp from the BD is used. If cleared
+	 * to 0, then TWE provides the timestamp.
+	 */
+	#define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN           UINT32_C(0x400)
+	/*
+	 * If set to '1', this operation will cause a trace capture in each
+	 * block it passes through.
+	 */
+	#define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE        UINT32_C(0x800)
+	/*
+	 * If set to '1', the device will record the time at which the packet
+	 * was actually transmitted at the TX MAC for 1-step time sync. This
+	 * bit must be valid on the first BD of a packet.
+	 */
+	#define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP        UINT32_C(0x1000)
+	/*
+	 * If set to '1', the controller replaces the Outer-tunnel IP checksum
+	 * field with hardware calculated IP checksum for the IP header of the
+	 * packet associated with this descriptor. For outer UDP checksum, it
+	 * will be the following behavior for all cases independent of settings
+	 * of inner LSO and checksum offload BD flags. If outer UDP checksum
+	 * is 0, then do not update it. If outer UDP checksum is non zero, then
+	 * the hardware should compute and update it.
+	 */
+	#define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM       UINT32_C(0x2000)
+	/*
+	 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
+	 * header will not be modified during LSO operations. If set to one
+	 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
+	 * incremented for each subsequent segment of an LSO operation. The
+	 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
+	 * packet.
+	 */
+	#define TX_BD_LONG_INLINE_LFLAGS_OT_IPID            UINT32_C(0x4000)
+	/*
+	 * If set to '1', When set to 1, KTLS encryption will be enabled for
+	 * the packet.
+	 */
+	#define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN          UINT32_C(0x8000)
+	uint8_t	unused2;
+	uint8_t	kid_or_ts_low;
+	#define TX_BD_LONG_INLINE_UNUSED            UINT32_C(0x1)
+	/*
+	 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
+	 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
+	 * the 20-bit KID.
+	 */
+	#define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
+	#define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
+	uint32_t	kid_or_ts_high;
+	#define TX_BD_LONG_INLINE_UNUSED_MASK        UINT32_C(0x7fff)
+	#define TX_BD_LONG_INLINE_UNUSED_SFT         0
+	/*
+	 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
+	 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
+	 * of this field contain the upper 13 bits of the 20-bit KID.
+	 */
+	#define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
+	#define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
+	/*
+	 * This value selects bits 25:16 of the CFA action to perform on the
+	 * packet. See the cfa_action field for more information.
+	 */
+	uint16_t	cfa_action_high;
+	#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
+	#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
 	/*
 	 * This value selects a CFA action to perform on the packet.
 	 * Set this value to zero if no CFA action is desired.
@@ -2182,6 +2986,97 @@ struct tx_bd_empty {
 	uint8_t	unused_4[8];
 } __rte_packed;
 
+/* tx_bd_mp_cmd (size:128b/16B) */
+struct tx_bd_mp_cmd {
+	/* Unless otherwise stated, sub-fields of this field are always valid. */
+	uint16_t	flags_type;
+	/* This value identifies the type of buffer descriptor. */
+	#define TX_BD_MP_CMD_TYPE_MASK        UINT32_C(0x3f)
+	#define TX_BD_MP_CMD_TYPE_SFT         0
+	/*
+	 * Indicates that this BD is used to issue a command to one of
+	 * the mid-path destinations.
+	 */
+	#define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD  UINT32_C(0x8)
+	#define TX_BD_MP_CMD_TYPE_LAST         TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
+	#define TX_BD_MP_CMD_FLAGS_MASK       UINT32_C(0xffc0)
+	#define TX_BD_MP_CMD_FLAGS_SFT        6
+	/*  */
+	#define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
+	#define TX_BD_MP_CMD_FLAGS_UNUSED_SFT  6
+	/*
+	 * This value indicates the number of 16B BD locations (slots)
+	 * consumed in the ring by this mid-path command BD, including the
+	 * BD header and the command field.
+	 */
+	#define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
+	#define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT  8
+	/*
+	 * This value defines the length of command field in bytes. The maximum
+	 * value shall be 496.
+	 */
+	uint16_t	len;
+	/*
+	 * The opaque data field is pass through to the completion and can be
+	 * used for any data that the driver wants to associate with this
+	 * Tx mid-path command.
+	 */
+	uint32_t	opaque;
+	uint64_t	unused1;
+} __rte_packed;
+
+/* tx_bd_presync_cmd (size:128b/16B) */
+struct tx_bd_presync_cmd {
+	/* Unless otherwise stated, sub-fields of this field are always valid. */
+	uint16_t	flags_type;
+	/* This value identifies the type of buffer descriptor. */
+	#define TX_BD_PRESYNC_CMD_TYPE_MASK             UINT32_C(0x3f)
+	#define TX_BD_PRESYNC_CMD_TYPE_SFT              0
+	/*
+	 * Indicates that this BD is used to issue a cryptographic pre-
+	 * sync command through the fast path and destined for TCE.
+	 */
+	#define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD  UINT32_C(0x9)
+	#define TX_BD_PRESYNC_CMD_TYPE_LAST \
+		TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
+	#define TX_BD_PRESYNC_CMD_FLAGS_MASK            UINT32_C(0xffc0)
+	#define TX_BD_PRESYNC_CMD_FLAGS_SFT             6
+	/*  */
+	#define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK      UINT32_C(0xc0)
+	#define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT       6
+	/*
+	 * This value indicates the number of 16B BD locations (slots)
+	 * consumed in the ring by this pre-sync command BD, including the
+	 * BD header and the command field.
+	 */
+	#define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK      UINT32_C(0x1f00)
+	#define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT       8
+	/*
+	 * This value defines the length of command field in bytes. The maximum
+	 * value shall be 496.
+	 */
+	uint16_t	len;
+	/*
+	 * The opaque data field is pass through to TCE and can be used for
+	 * debug.
+	 */
+	uint32_t	opaque;
+	/*
+	 * This field is the Crypto Context ID to which the retransmit packet is
+	 * applied. The KID references the context fields used by the
+	 * associated kTLS offloaded connection.
+	 */
+	uint32_t	kid;
+	/*
+	 * The KID value of all-ones is reserved for non-KTLS packets, which
+	 * only implies that this value must not be used when filling this
+	 * field for crypto packets.
+	 */
+	#define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
+	#define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
+	uint32_t	unused_1;
+} __rte_packed;
+
 /* rx_prod_pkt_bd (size:128b/16B) */
 struct rx_prod_pkt_bd {
 	/* This value identifies the type of buffer descriptor. */
@@ -2310,6 +3205,297 @@ struct rx_prod_agg_bd {
 	uint64_t	address;
 } __rte_packed;
 
+/* cfa_cmpls_cmp_data_msg (size:128b/16B) */
+struct cfa_cmpls_cmp_data_msg {
+	uint32_t	mp_client_dma_length_opcode_status_type;
+	/*
+	 * This field represents the Mid-Path client that generated the
+	 * completion.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK                UINT32_C(0x3f)
+	#define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT                 0
+	/* Mid Path Short Completion with length = 16B. */
+	#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \
+		UINT32_C(0x1e)
+	#define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \
+		CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
+	/* This value indicates the status for the command. */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK              UINT32_C(0x3c0)
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT               6
+	/* Completed without error. */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \
+		(UINT32_C(0x0) << 6)
+	/* Indicates an unsupported CFA opcode in the command. */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \
+		(UINT32_C(0x1) << 6)
+	/*
+	 * Indicates a CFA command formatting error. This error can occur on
+	 * any of the supported CFA commands.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \
+		(UINT32_C(0x2) << 6)
+	/*
+	 * Indicates an SVIF-Table scope error. This error can occur on any
+	 * of the supported CFA commands.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \
+		(UINT32_C(0x3) << 6)
+	/*
+	 * Indicates that the table_index is either outside of the
+	 * table_scope range set by its EM_SIZE or, for EM Insert, it is in
+	 * the static bucket range. This error can occur on EM Insert
+	 * commands. It can also occur on Read, Read Clear, Write, and
+	 * Invalidate commands if the table_type is EM.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \
+		(UINT32_C(0x4) << 6)
+	/*
+	 * Cache operation responded with an error. This error can occur on
+	 * Read, Read Clear, Write, EM Insert, and EM Delete commands.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \
+		(UINT32_C(0x5) << 6)
+	/*
+	 * Indicates failure on EM Insert or EM Delete Command. Hash index
+	 * and hash msb are returned in table_index and hash_msb fields.
+	 * Dma_length is set to 1 if the bucket is also returned (as dma
+	 * data).
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \
+		(UINT32_C(0x6) << 6)
+	/*
+	 * Indicates no notifications were available on an Event Collection
+	 * command.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \
+		(UINT32_C(0x7) << 6)
+	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \
+		CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
+	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK             UINT32_C(0xc00)
+	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT              10
+	/* This is the opcode from the command. */
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \
+		UINT32_C(0xff000)
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT               12
+	/*
+	 * This is read command. From 32 to 128B can be read from a table
+	 * using this command.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \
+		(UINT32_C(0x0) << 12)
+	/*
+	 * This is write command. From 32 to 128B can be written to a table
+	 * using this command.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \
+		(UINT32_C(0x1) << 12)
+	/*
+	 * This is read-clear command. 32B can be read from a table and a 16b
+	 * mask can be used to clear specific 16b units after the read as an
+	 * atomic operation.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \
+		(UINT32_C(0x2) << 12)
+	/*
+	 * An exact match table insert will be attempted into the table. If
+	 * there is a free location in the bucket, the payload will be
+	 * written to the bucket.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \
+		(UINT32_C(0x3) << 12)
+	/* An exact match table delete will be attempted. */
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \
+		(UINT32_C(0x4) << 12)
+	/*
+	 * The specified table area will be invalidated. If it is needed
+	 * again, it will be read from the backing store.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \
+		(UINT32_C(0x5) << 12)
+	/* Reads notification messages from the Host Notification Queue. */
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \
+		(UINT32_C(0x6) << 12)
+	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \
+		CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
+	/*
+	 * This field indicates the length of the DMA that accompanies the
+	 * completion. Specified in units of DWords (32b). Valid values are
+	 * between 0 and 128. A value of zero indicates that there is no DMA
+	 * that accompanies the completion.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \
+		UINT32_C(0xff00000)
+	#define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT           20
+	/*
+	 * This field represents the Mid-Path client that generated the
+	 * completion.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \
+		UINT32_C(0xf0000000)
+	#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT            28
+	/* TX configrable flow processing block. */
+	#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \
+		(UINT32_C(0x2) << 28)
+	/* RX configrable flow processing block. */
+	#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \
+		(UINT32_C(0x3) << 28)
+	#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
+		CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
+	/*
+	 * This is a copy of the opaque field from the mid path BD of this
+	 * command.
+	 */
+	uint32_t	opaque;
+	uint16_t	hash_msb_v;
+	/*
+	 * This value is written by the NIC such that it will be different for
+	 * each pass through the completion queue. The even passes will
+	 * write 1. The odd passes will write 0.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_V            UINT32_C(0x1)
+	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
+	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT  1
+	/*
+	 * This is the upper 12b of the hash, returned on Exact Match
+	 * Insertion/Deletion Commands.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
+	#define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
+	/* This is the table type from the command. */
+	uint8_t	table_type;
+	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK     UINT32_C(0xf)
+	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT      0
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf0)
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT   4
+	/* This command acts on the action table of the specified scope. */
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION  (UINT32_C(0x0) << 4)
+	/* This command acts on the exact match table of the specified scope. */
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM      (UINT32_C(0x1) << 4)
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \
+		CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
+	uint8_t	table_scope;
+	/* This is the table scope from the command. */
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
+	uint32_t	table_index;
+	/*
+	 * This is the table index from the command (if it exists). However, if
+	 * an Exact Match Insertion/Deletion command failed, then this is the
+	 * table index of the calculated static hash bucket.
+	 */
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
+	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
+} __rte_packed;
+
+/* CFA Mid-Path 32B DMA Message */
+/* cfa_dma32b_data_msg (size:256b/32B) */
+struct cfa_dma32b_data_msg {
+	/* DMA data value. */
+	uint32_t	dta[8];
+} __rte_packed;
+
+/* CFA Mid-Path 64B DMA Message */
+/* cfa_dma64b_data_msg (size:512b/64B) */
+struct cfa_dma64b_data_msg {
+	/* DMA data value. */
+	uint32_t	dta[16];
+} __rte_packed;
+
+/* CFA Mid-Path 96B DMA Message */
+/* cfa_dma96b_data_msg (size:768b/96B) */
+struct cfa_dma96b_data_msg {
+	/* DMA data value. */
+	uint32_t	dta[24];
+} __rte_packed;
+
+/* CFA Mid-Path 128B DMA Message */
+/* cfa_dma128b_data_msg (size:1024b/128B) */
+struct cfa_dma128b_data_msg {
+	/* DMA data value. */
+	uint32_t	dta[32];
+} __rte_packed;
+
+/* ce_cmpls_cmp_data_msg (size:128b/16B) */
+struct ce_cmpls_cmp_data_msg {
+	uint16_t	status_subtype_type;
+	/*
+	 * This field indicates the exact type of the completion. By
+	 * convention, the LSB identifies the length of the record in 16B
+	 * units. Even values indicate 16B records. Odd values indicate 32B
+	 * records.
+	 */
+	#define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK          UINT32_C(0x3f)
+	#define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT           0
+	/* Completion of a Mid Path Command. Length = 16B */
+	#define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT  UINT32_C(0x1e)
+	#define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
+		CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
+	/*
+	 * This value indicates the CE sub-type operation that is being
+	 * completed.
+	 */
+	#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK       UINT32_C(0x3c0)
+	#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT        6
+	/* Completion Response for a Solicited Command. */
+	#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED    (UINT32_C(0x0) << 6)
+	/* Error Completion (Unsolicited). */
+	#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR          (UINT32_C(0x1) << 6)
+	/* Re-Sync Completion (Unsolicited) */
+	#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC       (UINT32_C(0x2) << 6)
+	#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
+		CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
+	/* This value indicates the status for the command. */
+	#define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK        UINT32_C(0x3c00)
+	#define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT         10
+	/* Completed without error. */
+	#define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
+		(UINT32_C(0x0) << 10)
+	/* CFCK load error. */
+	#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
+		(UINT32_C(0x1) << 10)
+	/* FID check error. */
+	#define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
+		(UINT32_C(0x2) << 10)
+	#define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
+		CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR
+	uint8_t	unused0;
+	uint8_t	mp_clients;
+	#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK   UINT32_C(0xf)
+	#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT    0
+	/*
+	 * This field represents the Mid-Path client that generated the
+	 * completion.
+	 */
+	#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
+	#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
+	/* TX crypto engine block. */
+	#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE   (UINT32_C(0x0) << 4)
+	/* RX crypto engine block. */
+	#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE   (UINT32_C(0x1) << 4)
+	#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
+		CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
+	/*
+	 * This is a copy of the opaque field from the mid path BD of this
+	 * command.
+	 */
+	uint32_t	opaque;
+	/*  */
+	uint32_t	kid_v;
+	/*
+	 * This value is written by the NIC such that it will be different
+	 * for each pass through the completion queue. The even passes will
+	 * write 1. The odd passes will write 0.
+	 */
+	#define CE_CMPLS_CMP_DATA_MSG_V       UINT32_C(0x1)
+	/*
+	 * This field is the Crypto Context ID. The KID is used to store
+	 * information used by the associated kTLS offloaded connection.
+	 */
+	#define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
+	#define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
+	uint32_t	unused2;
+} __rte_packed;
+
 /* cmpl_base (size:128b/16B) */
 struct cmpl_base {
 	uint16_t	type;
@@ -5423,27 +6609,32 @@ struct rx_tpa_v2_end_cmpl {
 	 * records. Odd values indicate 32B
 	 * records.
 	 */
-	#define RX_TPA_V2_END_CMPL_TYPE_MASK                UINT32_C(0x3f)
-	#define RX_TPA_V2_END_CMPL_TYPE_SFT                 0
+	#define RX_TPA_V2_END_CMPL_TYPE_MASK \
+		UINT32_C(0x3f)
+	#define RX_TPA_V2_END_CMPL_TYPE_SFT                       0
 	/*
 	 * RX L2 TPA End Completion:
 	 * Completion at the end of a TPA operation.
 	 * Length = 32B
 	 */
-	#define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END            UINT32_C(0x15)
+	#define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \
+		UINT32_C(0x15)
 	#define RX_TPA_V2_END_CMPL_TYPE_LAST \
 		RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
-	#define RX_TPA_V2_END_CMPL_FLAGS_MASK               UINT32_C(0xffc0)
-	#define RX_TPA_V2_END_CMPL_FLAGS_SFT                6
+	#define RX_TPA_V2_END_CMPL_FLAGS_MASK \
+		UINT32_C(0xffc0)
+	#define RX_TPA_V2_END_CMPL_FLAGS_SFT                      6
 	/*
 	 * When this bit is '1', it indicates a packet that has an
 	 * error of some type. Type of error is indicated in
 	 * error_flags.
 	 */
-	#define RX_TPA_V2_END_CMPL_FLAGS_ERROR               UINT32_C(0x40)
+	#define RX_TPA_V2_END_CMPL_FLAGS_ERROR \
+		UINT32_C(0x40)
 	/* This field indicates how the packet was placed in the buffer. */
-	#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK      UINT32_C(0x380)
-	#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT       7
+	#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \
+		UINT32_C(0x380)
+	#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT             7
 	/*
 	 * Jumbo:
 	 * TPA Packet was placed using jumbo algorithm. This means
@@ -5482,11 +6673,30 @@ struct rx_tpa_v2_end_cmpl {
 	 */
 	#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
 		(UINT32_C(0x6) << 7)
+	/*
+	 * IOC/Header-Data Separation:
+	 * Packet will be placed using In-Order Completion/HDS where
+	 * the header is in the first packet buffer. Payload of each
+	 * packet will be placed such that each packet starts at the
+	 * beginning of an aggregation buffer.
+	 */
+	#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
+		(UINT32_C(0x7) << 7)
 	#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
-		RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
-	/* unused is 2 b */
-	#define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK         UINT32_C(0xc00)
-	#define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT          10
+		RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
+	/* unused is 1 b */
+	#define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \
+		UINT32_C(0x400)
+	/*
+	 * This bit is '1' if metadata has been added to the end of the
+	 * packet in host memory. Metadata starts at the first 32B boundary
+	 * after the end of the packet for regular and jumbo placement.
+	 * It starts at the first 32B boundary after the end of the header
+	 * for HDS placement. The length of the metadata is indicated in the
+	 * metadata itself.
+	 */
+	#define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \
+		UINT32_C(0x800)
 	/*
 	 * This value indicates what the inner packet determined for the
 	 * packet was.
@@ -5496,8 +6706,9 @@ struct rx_tpa_v2_end_cmpl {
 	 *     field is valid and contains the TCP checksum.
 	 *     This also indicates that the payload_offset field is valid.
 	 */
-	#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK          UINT32_C(0xf000)
-	#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT           12
+	#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \
+		UINT32_C(0xf000)
+	#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT                 12
 	/*
 	 * This value is zero for TPA End completions.
 	 * There is no data in the buffer that corresponds to the opaque
@@ -6047,6 +7258,12 @@ struct hwrm_async_event_cmpl {
 	/* Master function selection event */
 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
 		UINT32_C(0x9)
+	/*
+	 * An event signifying that a ring has been disabled by
+	 * hw due to error.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \
+		UINT32_C(0xa)
 	/* Function driver unloaded */
 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
 		UINT32_C(0x10)
@@ -6156,6 +7373,9 @@ struct hwrm_async_event_cmpl {
 	 */
 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
 		UINT32_C(0x41)
+	/* Maximum Registrable event id. */
+	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
+		UINT32_C(0x42)
 	/*
 	 * A trace log message. This contains firmware trace logs string
 	 * embedded in the asynchronous message. This is an experimental
@@ -6792,7 +8012,7 @@ struct hwrm_async_event_cmpl_reset_notify {
 		UINT32_C(0x8)
 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
 		HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
-	/* Event specific data */
+	/* Event specific data. The data is for internal debug use only. */
 	uint32_t	event_data2;
 	uint8_t	opaque_v;
 	/*
@@ -6936,6 +8156,71 @@ struct hwrm_async_event_cmpl_error_recovery {
 		UINT32_C(0x2)
 } __rte_packed;
 
+/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
+struct hwrm_async_event_cmpl_ring_monitor_msg {
+	uint16_t	type;
+	/*
+	 * This field indicates the exact type of the completion.
+	 * By convention, the LSB identifies the length of the
+	 * record in 16B units. Even values indicate 16B
+	 * records. Odd values indicate 32B
+	 * records.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \
+		UINT32_C(0x3f)
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT             0
+	/* HWRM Asynchronous Event Information */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \
+		UINT32_C(0x2e)
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \
+		HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
+	/* Identifiers of events. */
+	uint16_t	event_id;
+	/* Ring Monitor Message. */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \
+		UINT32_C(0xa)
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \
+		HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
+	/* Event specific data */
+	uint32_t	event_data2;
+	/* Type of Ring disabled. */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \
+		UINT32_C(0xff)
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \
+		0
+	/* tx ring disabled. */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \
+		UINT32_C(0x0)
+	/* rx ring disabled. */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \
+		UINT32_C(0x1)
+	/* cmpl ring disabled. */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \
+		UINT32_C(0x2)
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \
+		HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
+	uint8_t	opaque_v;
+	/*
+	 * This value is written by the NIC such that it will be different
+	 * for each pass through the completion queue. The even passes
+	 * will write 1. The odd passes will write 0.
+	 */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V          UINT32_C(0x1)
+	/* opaque is 7 b */
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \
+		UINT32_C(0xfe)
+	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
+	/* 8-lsb timestamp from POR (100-msec resolution) */
+	uint8_t	timestamp_lo;
+	/* 16-lsb timestamp from POR (100-msec resolution) */
+	uint16_t	timestamp_hi;
+	/*
+	 * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl
+	 * then this field will indicate the ring id.
+	 */
+	uint32_t	event_data1;
+} __rte_packed;
+
 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
 struct hwrm_async_event_cmpl_func_drvr_unload {
 	uint16_t	type;
@@ -8396,6 +9681,388 @@ struct hwrm_async_event_cmpl_hwrm_error {
 		UINT32_C(0x1)
 } __rte_packed;
 
+/* metadata_base_msg (size:64b/8B) */
+struct metadata_base_msg {
+	uint16_t	md_type_link;
+	/* This field classifies the data present in the meta-data. */
+	#define METADATA_BASE_MSG_MD_TYPE_MASK      UINT32_C(0x1f)
+	#define METADATA_BASE_MSG_MD_TYPE_SFT       0
+	/* Meta data fiels are not valid */
+	#define METADATA_BASE_MSG_MD_TYPE_NONE        UINT32_C(0x0)
+	/*
+	 * This setting is used when packets are coming in-order. Depending on
+	 * the state of the receive context, the meta-data will carry different
+	 * information.
+	 */
+	#define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC  UINT32_C(0x1)
+	/*
+	 * With this setting HW passes the TCP sequence number of the TLS
+	 * record that it is requesting a resync on in the meta data.
+	 */
+	#define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC  UINT32_C(0x2)
+	#define METADATA_BASE_MSG_MD_TYPE_LAST \
+		METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
+	/*
+	 * This field indicates where the next metadata block starts. It is
+	 * counted in 16B units. A value of zero indicates that there is no
+	 * metadata.
+	 */
+	#define METADATA_BASE_MSG_LINK_MASK         UINT32_C(0x1e0)
+	#define METADATA_BASE_MSG_LINK_SFT          5
+	uint16_t	unused0;
+	uint32_t	unused1;
+} __rte_packed;
+
+/* tls_metadata_base_msg (size:64b/8B) */
+struct tls_metadata_base_msg {
+	uint32_t	md_type_link_flags_kid_lo;
+	/* This field classifies the data present in the meta-data. */
+	#define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
+		UINT32_C(0x1f)
+	#define TLS_METADATA_BASE_MSG_MD_TYPE_SFT                  0
+	/*
+	 * This setting is used when packets are coming in-order. Depending on
+	 * the state of the receive context, the meta-data will carry different
+	 * information.
+	 */
+	#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
+		UINT32_C(0x1)
+	/*
+	 * With this setting HW passes the TCP sequence number of the TLS
+	 * record that it is requesting a resync on in the meta data.
+	 */
+	#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \
+		UINT32_C(0x2)
+	#define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \
+		TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
+	/*
+	 * This field indicates where the next metadata block starts. It is
+	 * counted in 16B units. A value of zero indicates that there is no
+	 * metadata.
+	 */
+	#define TLS_METADATA_BASE_MSG_LINK_MASK \
+		UINT32_C(0x1e0)
+	#define TLS_METADATA_BASE_MSG_LINK_SFT                     5
+	/* These are flags present in the metadata. */
+	#define TLS_METADATA_BASE_MSG_FLAGS_MASK \
+		UINT32_C(0x1fffe00)
+	#define TLS_METADATA_BASE_MSG_FLAGS_SFT                    9
+	/*
+	 * A value of 1 implies that the packet was decrypted by HW. Otherwise
+	 * the packet is passed on as it came in on the wire.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \
+		UINT32_C(0x200)
+	/*
+	 * This field indicates the state of the ghash field passed in the
+	 * meta-data.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
+		UINT32_C(0xc00)
+	#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT               10
+	/*
+	 * This enumeration states that the ghash is not valid in the
+	 * meta-data.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \
+		(UINT32_C(0x0) << 10)
+	/*
+	 * This enumeration indicates that this pkt contains the record's
+	 * tag and this pkt was received ooo, the partial_ghash field
+	 * contains the ghash.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \
+		(UINT32_C(0x1) << 10)
+	/*
+	 * This enumeration indicates that the current record's tag wasn't
+	 * seen and the chip is moving on to the next record, the
+	 * partial_ghash field contains the ghash.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \
+		(UINT32_C(0x2) << 10)
+	#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \
+		TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC
+	/* This field indicates the status of tag authentication. */
+	#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
+		UINT32_C(0x3000)
+	#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT     12
+	/*
+	 * This enumeration is set when there is no tags present in the
+	 * packet.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+		(UINT32_C(0x0) << 12)
+	/*
+	 * This enumeration states that there is at least one tag in the
+	 * packet and every tag is valid.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
+		(UINT32_C(0x1) << 12)
+	/*
+	 * This enumeration states that there is atleast one tag in the
+	 * packet and atleast one of the tag is invalid. The entire packet
+	 * is sent decrypted to the host.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
+		(UINT32_C(0x2) << 12)
+	#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
+		TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
+	/*
+	 * A value of 1 indicates that this packet contains a record that
+	 * starts in the packet and extends beyond the packet.
+	 */
+	#define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
+		UINT32_C(0x4000)
+	/*
+	 * This value indicates the lower 7-bit of the Crypto Key ID
+	 * associated with this operation.
+	 */
+	#define TLS_METADATA_BASE_MSG_KID_LO_MASK \
+		UINT32_C(0xfe000000)
+	#define TLS_METADATA_BASE_MSG_KID_LO_SFT                   25
+	uint16_t	kid_hi;
+	/*
+	 * This value indicates the upper 13-bit of the Crypto Key ID
+	 * associated with this operation.
+	 */
+	#define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
+	#define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
+	uint16_t	unused0;
+} __rte_packed;
+
+/* tls_metadata_insync_msg (size:192b/24B) */
+struct tls_metadata_insync_msg {
+	uint32_t	md_type_link_flags_kid_lo;
+	/* This field classifies the data present in the meta-data. */
+	#define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
+		UINT32_C(0x1f)
+	#define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT                  0
+	/*
+	 * This setting is used when packets are coming in-order. Depending on
+	 * the state of the receive context, the meta-data will carry different
+	 * information.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
+		UINT32_C(0x1)
+	#define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \
+		TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC
+	/*
+	 * This field indicates where the next metadata block starts. It is
+	 * counted in 16B units. A value of zero indicates that there is no
+	 * metadata.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_LINK_MASK \
+		UINT32_C(0x1e0)
+	#define TLS_METADATA_INSYNC_MSG_LINK_SFT                     5
+	/* These are flags present in the metadata. */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
+		UINT32_C(0x1fffe00)
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_SFT                    9
+	/*
+	 * A value of 1 implies that the packet was decrypted by HW. Otherwise
+	 * the packet is passed on as it came in on the wire.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \
+		UINT32_C(0x200)
+	/*
+	 * This field indicates the state of the ghash field passed in the
+	 * meta-data.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
+		UINT32_C(0xc00)
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT               10
+	/*
+	 * This enumeration states that the ghash is not valid in the
+	 * meta-data.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \
+		(UINT32_C(0x0) << 10)
+	/*
+	 * This enumeration indicates that this pkt contains the record's
+	 * tag and this pkt was received ooo, the partial_ghash field
+	 * contains the ghash.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \
+		(UINT32_C(0x1) << 10)
+	/*
+	 * This enumeration indicates that the current record's tag wasn't
+	 * seen and the chip is moving on to the next record, the
+	 * partial_ghash field contains the ghash.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \
+		(UINT32_C(0x2) << 10)
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \
+		TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC
+	/* This field indicates the status of tag authentication. */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
+		UINT32_C(0x3000)
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT     12
+	/*
+	 * This enumeration is set when there is no tags present in the
+	 * packet.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+		(UINT32_C(0x0) << 12)
+	/*
+	 * This enumeration states that there is at least one tag in the
+	 * packet and every tag is valid.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
+		(UINT32_C(0x1) << 12)
+	/*
+	 * This enumeration states that there is atleast one tag in the
+	 * packet and atleast one of the tag is invalid. The entire packet
+	 * is sent decrypted to the host.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
+		(UINT32_C(0x2) << 12)
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
+		TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
+	/*
+	 * A value of 1 indicates that this packet contains a record that
+	 * starts in the packet and extends beyond the packet.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
+		UINT32_C(0x4000)
+	/*
+	 * This value indicates the lower 7-bit of the Crypto Key ID
+	 * associated with this operation.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
+		UINT32_C(0xfe000000)
+	#define TLS_METADATA_INSYNC_MSG_KID_LO_SFT                   25
+	uint16_t	kid_hi;
+	/*
+	 * This value indicates the upper 13-bit of the Crypto Key ID
+	 * associated with this operation.
+	 */
+	#define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
+	#define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
+	/*
+	 * This field is only valid when md_type is set to tls_insync. This field
+	 * indicates the offset within the current TCP packet where the TLS header
+	 * starts. If there are multiple TLS headers in the packet, this provides
+	 * the offset of the last TLS header.
+	 *
+	 * The field is calculated by subtracting TCP sequence number of the first
+	 * byte of the TCP payload of the packet from the TCP sequence number of
+	 * the last TLS header in the packet.
+	 */
+	uint16_t	tls_header_offset;
+	/*
+	 * This is the sequence Number of the record that was processed by the HW.
+	 * If there are multiple records in a packet, this would be the sequence
+	 * number of the last record.
+	 */
+	uint64_t	record_seq_num;
+	/*
+	 * This field contains cumulative partial GHASH value of all the packets
+	 * decrypted by the HW associated with a TLS record. This field is valid
+	 * on when packets belonging to have arrived out-of-order and HW could
+	 * not decrypt every packet and authenticate the record. Partial GHASH is
+	 * only sent out with packet having the TAG field.
+	 */
+	uint64_t	partial_ghash;
+} __rte_packed;
+
+/* tls_metadata_resync_msg (size:256b/32B) */
+struct tls_metadata_resync_msg {
+	uint32_t	md_type_link_flags_kid_lo;
+	/* This field classifies the data present in the meta-data. */
+	#define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
+		UINT32_C(0x1f)
+	#define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT                 0
+	/*
+	 * With this setting HW passes the TCP sequence number of the TLS
+	 * record that it is requesting a resync on in the meta data.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \
+		UINT32_C(0x2)
+	#define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \
+		TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC
+	/*
+	 * This field indicates where the next metadata block starts. It is
+	 * counted in 16B units. A value of zero indicates that there is no
+	 * metadata.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_LINK_MASK \
+		UINT32_C(0x1e0)
+	#define TLS_METADATA_RESYNC_MSG_LINK_SFT                    5
+	/* These are flags present in the metadata. */
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
+		UINT32_C(0x1fffe00)
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_SFT                   9
+	/*
+	 * A value of 1 implies that the packet was decrypted by HW. Otherwise
+	 * the packet is passed on as it came in on the wire.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \
+		UINT32_C(0x200)
+	/*
+	 * This field indicates the state of the ghash field passed in the
+	 * meta-data.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
+		UINT32_C(0xc00)
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT              10
+	/*
+	 * This enumeration states that the ghash is not valid in the
+	 * meta-data.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \
+		(UINT32_C(0x0) << 10)
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \
+		TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID
+	/* This field indicates the status of tag authentication. */
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
+		UINT32_C(0x3000)
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT    12
+	/*
+	 * This enumeration is set when there is no tags present in the
+	 * packet.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+		(UINT32_C(0x0) << 12)
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
+		TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
+	/*
+	 * A value of 1 indicates that this packet contains a record that
+	 * starts in the packet and extends beyond the packet.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
+		UINT32_C(0x4000)
+	/*
+	 * This value indicates the lower 7-bit of the Crypto Key ID
+	 * associated with this operation.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
+		UINT32_C(0xfe000000)
+	#define TLS_METADATA_RESYNC_MSG_KID_LO_SFT                  25
+	uint16_t	kid_hi;
+	/*
+	 * This value indicates the upper 13-bit of the Crypto Key ID
+	 * associated with this operation.
+	 */
+	#define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
+	#define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
+	/* This field is unused in this context. */
+	uint16_t	metadata_0;
+	/*
+	 * This field indicates the TCP sequence number of the TLS record that HW
+	 * is requesting a resync on from the Driver. HW will keep a count of the
+	 * TLS records it found after this record (delta_records). Driver will
+	 * provide the TLS Record Sequence Number associated with the record. HW
+	 * will add the delta_records to the Record Sequence Number provided by
+	 * the driver and get back on sync.
+	 */
+	uint32_t	resync_record_tcp_seq_num;
+	uint32_t	unused0;
+	/* This field is unused in this context. */
+	uint64_t	metadata_2;
+	/* This field is unused in this context. */
+	uint64_t	metadata_3;
+} __rte_packed;
+
 /*******************
  * hwrm_func_reset *
  *******************/
@@ -9466,7 +11133,38 @@ struct hwrm_func_qcaps_output {
 		UINT32_C(0x80)
 	/* The maximum number of SCHQs supported by this device. */
 	uint8_t	max_schqs;
-	uint8_t	unused_1[2];
+	uint8_t	mpc_chnls_cap;
+	/*
+	 * When this bit is '1', it indicates that HW and firmware
+	 * supports the use of a MPC channel with destination set
+	 * to the TX crypto engine block.
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE         UINT32_C(0x1)
+	/*
+	 * When this bit is '1', it indicates that HW and firmware
+	 * supports the use of a MPC channel with destination set
+	 * to the RX crypto engine block.
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE         UINT32_C(0x2)
+	/*
+	 * When this bit is '1', it indicates that HW and firmware
+	 * supports the use of a MPC channel with destination set
+	 * to the TX configurable flow processing block.
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA      UINT32_C(0x4)
+	/*
+	 * When this bit is '1', it indicates that HW and firmware
+	 * supports the use of a MPC channel with destination set
+	 * to the RX configurable flow processing block.
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA      UINT32_C(0x8)
+	/*
+	 * When this bit is '1', it indicates that HW and firmware
+	 * supports the use of a MPC channel with destination set
+	 * to the primate processor block.
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE     UINT32_C(0x10)
+	uint8_t	unused_1;
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -9643,6 +11341,12 @@ struct hwrm_func_qcfg_output {
 	 */
 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
 		UINT32_C(0x400)
+	/*
+	 * If set to 1, then the firmware will notify driver using async
+	 * event when a ring is disabled due to a Hardware error.
+	 */
+	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \
+		UINT32_C(0x800)
 	/*
 	 * This value is current MAC address configured for this
 	 * function. A value of 00-00-00-00-00-00 indicates no
@@ -9959,7 +11663,40 @@ struct hwrm_func_qcfg_output {
 	#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT       0
 	/* This field specifies whether svif is valid or not */
 	#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID     UINT32_C(0x8000)
-	uint8_t	unused_2[7];
+	uint8_t	mpc_chnls;
+	/*
+	 * When this bit is '1', it indicates that a MPC channel with
+	 * destination set to the TX crypto engine block is enabled.
+	 */
+	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \
+		UINT32_C(0x1)
+	/*
+	 * When this bit is '1', it indicates that a MPC channel with
+	 * destination set to the RX crypto engine block is enabled.
+	 */
+	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \
+		UINT32_C(0x2)
+	/*
+	 * When this bit is '1', it indicates that a MPC channel with
+	 * destination set to the TX configurable flow processing block is
+	 * enabled.
+	 */
+	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \
+		UINT32_C(0x4)
+	/*
+	 * When this bit is '1', it indicates that a MPC channel with
+	 * destination set to the RX configurable flow processing block is
+	 * enabled.
+	 */
+	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \
+		UINT32_C(0x8)
+	/*
+	 * When this bit is '1', it indicates that a MPC channel with
+	 * destination set to the primate processor block is enabled.
+	 */
+	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
+		UINT32_C(0x10)
+	uint8_t	unused_2[6];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -10376,6 +12113,12 @@ struct hwrm_func_cfg_input {
 	 */
 	#define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
 		UINT32_C(0x1000000)
+	/*
+	 * This bit must be '1' for the mpc_chnls field to be
+	 * configured.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \
+		UINT32_C(0x2000000)
 	/*
 	 * The maximum transmission unit of the function.
 	 * The HWRM should make sure that the mtu of
@@ -10642,7 +12385,74 @@ struct hwrm_func_cfg_input {
 	uint16_t	num_mcast_filters;
 	/* Used by a PF driver to associate a SCHQ with a VF. */
 	uint16_t	schq_id;
-	uint8_t	unused_0[6];
+	uint16_t	mpc_chnls;
+	/*
+	 * When this bit is '1', the caller requests to enable a MPC
+	 * channel with destination to the TX crypto engine block.
+	 * When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE          UINT32_C(0x1)
+	/*
+	 * When this bit is '1', the caller requests to disable a MPC
+	 * channel with destination to the TX crypto engine block.
+	 * When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE         UINT32_C(0x2)
+	/*
+	 * When this bit is '1', the caller requests to enable a MPC
+	 * channel with destination to the RX crypto engine block.
+	 * When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE          UINT32_C(0x4)
+	/*
+	 * When this bit is '1', the caller requests to disable a MPC
+	 * channel with destination to the RX crypto engine block.
+	 * When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE         UINT32_C(0x8)
+	/*
+	 * When this bit is '1', the caller requests to enable a MPC
+	 * channel with destination to the TX configurable flow processing
+	 * block. When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \
+		UINT32_C(0x10)
+	/*
+	 * When this bit is '1', the caller requests to disable a MPC
+	 * channel with destination to the TX configurable flow processing
+	 * block block. When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \
+		UINT32_C(0x20)
+	/*
+	 * When this bit is '1', the caller requests to enable a MPC
+	 * channel with destination to the RX configurable flow processing
+	 * block. When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \
+		UINT32_C(0x40)
+	/*
+	 * When this bit is '1', the caller requests to disable a MPC
+	 * channel with destination to the RX configurable flow processing
+	 * block block. When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \
+		UINT32_C(0x80)
+	/*
+	 * When this bit is '1', the caller requests to enable a MPC
+	 * channel with destination to the primate processor block.
+	 * When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \
+		UINT32_C(0x100)
+	/*
+	 * When this bit is '1', the caller requests to disable a MPC
+	 * channel with destination to the primate processor block.
+	 * When this bit is ‘0’, this flag has no effect.
+	 */
+	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \
+		UINT32_C(0x200)
+	uint8_t	unused_0[4];
 } __rte_packed;
 
 /* hwrm_func_cfg_output (size:128b/16B) */
@@ -10889,7 +12699,7 @@ struct hwrm_func_qstats_ext_input {
 	uint8_t	unused_1[4];
 } __rte_packed;
 
-/* hwrm_func_qstats_ext_output (size:1472b/184B) */
+/* hwrm_func_qstats_ext_output (size:1536b/192B) */
 struct hwrm_func_qstats_ext_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
@@ -10941,6 +12751,8 @@ struct hwrm_func_qstats_ext_output {
 	uint64_t	rx_tpa_bytes;
 	/* Number of TPA errors */
 	uint64_t	rx_tpa_errors;
+	/* Number of TPA errors */
+	uint64_t	rx_tpa_events;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -11842,6 +13654,125 @@ struct hwrm_func_resource_qcaps_output {
 	uint8_t	valid;
 } __rte_packed;
 
+/*****************************
+ * hwrm_func_vf_resource_cfg *
+ *****************************/
+
+
+/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
+struct hwrm_func_vf_resource_cfg_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* VF ID that is being configured by PF */
+	uint16_t	vf_id;
+	/* Maximum guaranteed number of MSI-X vectors for the function */
+	uint16_t	max_msix;
+	/* Minimum guaranteed number of RSS/COS contexts */
+	uint16_t	min_rsscos_ctx;
+	/* Maximum non-guaranteed number of RSS/COS contexts */
+	uint16_t	max_rsscos_ctx;
+	/* Minimum guaranteed number of completion rings */
+	uint16_t	min_cmpl_rings;
+	/* Maximum non-guaranteed number of completion rings */
+	uint16_t	max_cmpl_rings;
+	/* Minimum guaranteed number of transmit rings */
+	uint16_t	min_tx_rings;
+	/* Maximum non-guaranteed number of transmit rings */
+	uint16_t	max_tx_rings;
+	/* Minimum guaranteed number of receive rings */
+	uint16_t	min_rx_rings;
+	/* Maximum non-guaranteed number of receive rings */
+	uint16_t	max_rx_rings;
+	/* Minimum guaranteed number of L2 contexts */
+	uint16_t	min_l2_ctxs;
+	/* Maximum non-guaranteed number of L2 contexts */
+	uint16_t	max_l2_ctxs;
+	/* Minimum guaranteed number of VNICs */
+	uint16_t	min_vnics;
+	/* Maximum non-guaranteed number of VNICs */
+	uint16_t	max_vnics;
+	/* Minimum guaranteed number of statistic contexts */
+	uint16_t	min_stat_ctx;
+	/* Maximum non-guaranteed number of statistic contexts */
+	uint16_t	max_stat_ctx;
+	/* Minimum guaranteed number of ring groups */
+	uint16_t	min_hw_ring_grps;
+	/* Maximum non-guaranteed number of ring groups */
+	uint16_t	max_hw_ring_grps;
+	uint16_t	flags;
+	/*
+	 * If this bit is set, all minimum resources requested should be
+	 * reserved if minimum >= 1, otherwise return error. In case of
+	 * error, keep all existing reservations before the call.
+	 */
+	#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
+		UINT32_C(0x1)
+	uint8_t	unused_0[2];
+} __rte_packed;
+
+/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
+struct hwrm_func_vf_resource_cfg_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* Reserved number of RSS/COS contexts */
+	uint16_t	reserved_rsscos_ctx;
+	/* Reserved number of completion rings */
+	uint16_t	reserved_cmpl_rings;
+	/* Reserved number of transmit rings */
+	uint16_t	reserved_tx_rings;
+	/* Reserved number of receive rings */
+	uint16_t	reserved_rx_rings;
+	/* Reserved number of L2 contexts */
+	uint16_t	reserved_l2_ctxs;
+	/* Reserved number of VNICs */
+	uint16_t	reserved_vnics;
+	/* Reserved number of statistic contexts */
+	uint16_t	reserved_stat_ctx;
+	/* Reserved number of ring groups */
+	uint16_t	reserved_hw_ring_grps;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
 /*********************************
  * hwrm_func_backing_store_qcaps *
  *********************************/
@@ -15343,10 +17274,11 @@ struct hwrm_port_phy_cfg_input {
 	 * When set to 1, then the HWRM shall enable FEC autonegotitation
 	 * on this port if supported.  When enabled, at least one of the
 	 * FEC modes must be advertised by enabling the fec_clause_74_enable,
-	 * fec_clause_91_enable, fec_rs544_1xn_enable, or fec_rs544_2xn_enable
-	 * flag.  If none of the FEC mode is currently enabled, the HWRM
-	 * shall choose a default advertisement setting.
-	 * The default advertisement setting can be queried by calling
+	 * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,
+	 * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag.  If none
+	 * of the FEC mode is currently enabled, the HWRM shall choose
+	 * a default advertisement setting.
+	 * The default advertisment setting can be queried by calling
 	 * hwrm_port_phy_qcfg.  Note that the link speed must be
 	 * in autonegotiation mode for FEC autonegotiation to take effect.
 	 * When set to 0, then this flag shall be ignored.
@@ -15357,7 +17289,8 @@ struct hwrm_port_phy_cfg_input {
 		UINT32_C(0x100)
 	/*
 	 * When set to 1, then the HWRM shall disable FEC autonegotiation
-	 * on this port if supported.
+	 * on this port and use forced FEC mode.  In forced FEC mode, one
+	 * or more FEC forced settings under the same clause can be set.
 	 * When set to 0, then this flag shall be ignored.
 	 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
 	 * flag.
@@ -15385,22 +17318,26 @@ struct hwrm_port_phy_cfg_input {
 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
 		UINT32_C(0x800)
 	/*
-	 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
-	 * on this port if supported, by advertising FEC CLAUSE 91 if
-	 * FEC autonegotiation is enabled or force enabled otherwise.
+	 * When set to 1, then the HWRM shall enable FEC CLAUSE 91
+	 * (Reed Solomon RS(528,514) for NRZ) on this port if supported,
+	 * by advertising FEC RS(528,514) if FEC autonegotiation is enabled
+	 * or force enabled otherwise.  In forced FEC mode, this flag
+	 * will only take effect if the speed is NRZ.  Additional
+	 * RS544 or RS272 flags (also under clause 91) may be set for PAM4
+	 * in forced FEC mode.
 	 * When set to 0, then this flag shall be ignored.
-	 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
-	 * flag.
+	 * If FEC RS(528,514) is not supported, then the HWRM shall ignore
+	 * this flag.
 	 */
 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
 		UINT32_C(0x1000)
 	/*
-	 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
-	 * on this port if supported, by not advertising FEC CLAUSE 91 if
-	 * FEC autonegotiation is enabled or force disabled otherwise.
-	 * When set to 0, then this flag shall be ignored.
-	 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
-	 * flag.
+	 * When set to 1, then the HWRM shall disable FEC CLAUSE 91
+	 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by
+	 * not advertising RS(528,514) if FEC autonegotiation is enabled or
+	 * force disabled otherwise.  When set to 0, then this flag shall be
+	 * ignored.  If FEC RS(528,514) is not supported, then the HWRM
+	 * shall ignore this flag.
 	 */
 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
 		UINT32_C(0x2000)
@@ -15428,6 +17365,9 @@ struct hwrm_port_phy_cfg_input {
 	 * When set to 1, then the HWRM shall enable FEC RS544_1XN
 	 * on this port if supported, by advertising FEC RS544_1XN if
 	 * FEC autonegotiation is enabled or force enabled otherwise.
+	 * In forced mode, this flag will only take effect if the speed is
+	 * PAM4.  If this flag and fec_rs544_ieee_enable are set, the
+	 * HWRM shall choose one of the RS544 modes.
 	 * When set to 0, then this flag shall be ignored.
 	 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
 	 * flag.
@@ -15445,25 +17385,76 @@ struct hwrm_port_phy_cfg_input {
 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
 		UINT32_C(0x10000)
 	/*
-	 * When set to 1, then the HWRM shall enable FEC RS544_2XN
-	 * on this port if supported, by advertising FEC RS544_2XN if
+	 * When set to 1, then the HWRM shall enable FEC RS(544,514)
+	 * on this port if supported, by advertising FEC RS(544,514) if
 	 * FEC autonegotiation is enabled or force enabled otherwise.
+	 * In forced mode, this flag will only take effect if the speed is
+	 * PAM4.  If this flag and fec_rs544_1xn_enable are set, the
+	 * HWRM shall choose one of the RS544 modes.
 	 * When set to 0, then this flag shall be ignored.
-	 * If FEC RS544_2XN is not supported, then the HWRM shall ignore this
-	 * flag.
+	 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
+	 * this flag.
 	 */
-	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_ENABLE \
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \
 		UINT32_C(0x20000)
 	/*
-	 * When set to 1, then the HWRM shall disable FEC RS544_2XN
-	 * on this port if supported, by not advertising FEC RS544_2XN if
+	 * When set to 1, then the HWRM shall disable FEC RS(544,514)
+	 * on this port if supported, by not advertising FEC RS(544,514) if
 	 * FEC autonegotiation is enabled or force disabled otherwise.
 	 * When set to 0, then this flag shall be ignored.
-	 * If FEC RS544_2XN  is not supported, then the HWRM shall ignore this
-	 * flag.
+	 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
+	 * this flag.
 	 */
-	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_DISABLE \
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \
 		UINT32_C(0x40000)
+	/*
+	 * When set to 1, then the HWRM shall enable FEC RS272_1XN
+	 * on this port if supported, by advertising FEC RS272_1XN if
+	 * FEC autonegotiation is enabled or force enabled otherwise.
+	 * In forced mode, this flag will only take effect if the speed is
+	 * PAM4.  If this flag and fec_rs272_ieee_enable are set, the
+	 * HWRM shall choose one of the RS272 modes.  Note that RS272
+	 * and RS544 modes cannot be set at the same time in forced FEC mode.
+	 * When set to 0, then this flag shall be ignored.
+	 * If FEC RS272_1XN is not supported, then the HWRM shall ignore this
+	 * flag.
+	 */
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \
+		UINT32_C(0x80000)
+	/*
+	 * When set to 1, then the HWRM shall disable FEC RS272_1XN
+	 * on this port if supported, by not advertising FEC RS272_1XN if
+	 * FEC autonegotiation is enabled or force disabled otherwise.
+	 * When set to 0, then this flag shall be ignored.
+	 * If FEC RS272_1XN is not supported, then the HWRM shall ignore
+	 * this flag.
+	 */
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \
+		UINT32_C(0x100000)
+	/*
+	 * When set to 1, then the HWRM shall enable FEC RS(272,257)
+	 * on this port if supported, by advertising FEC RS(272,257) if
+	 * FEC autonegotiation is enabled or force enabled otherwise.
+	 * In forced mode, this flag will only take effect if the speed is
+	 * PAM4.  If this flag and fec_rs272_1xn_enable are set, the
+	 * HWRM shall choose one of the RS272 modes.  Note that RS272
+	 * and RS544 modes cannot be set at the same time in forced FEC mode.
+	 * When set to 0, then this flag shall be ignored.
+	 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
+	 * this flag.
+	 */
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \
+		UINT32_C(0x200000)
+	/*
+	 * When set to 1, then the HWRM shall disable FEC RS(272,257)
+	 * on this port if supported, by not advertising FEC RS(272,257) if
+	 * FEC autonegotiation is enabled or force disabled otherwise.
+	 * When set to 0, then this flag shall be ignored.
+	 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
+	 * this flag.
+	 */
+	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \
+		UINT32_C(0x400000)
 	uint32_t	enables;
 	/*
 	 * This bit must be '1' for the auto_mode field to be
@@ -15939,7 +17930,7 @@ struct hwrm_port_phy_qcfg_input {
 	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_port_phy_qcfg_output (size:832b/104B) */
+/* hwrm_port_phy_qcfg_output (size:768b/96B) */
 struct hwrm_port_phy_qcfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
@@ -15959,20 +17950,52 @@ struct hwrm_port_phy_qcfg_output {
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK    UINT32_C(0x2)
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
 		HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
+	uint8_t	active_fec_signal_mode;
 	/*
 	 * This value indicates the current link signaling mode of the
 	 * connection.
 	 */
-	uint8_t	link_signal_mode;
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \
+		UINT32_C(0xf)
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT                 0
 	/* NRZ signaling */
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_NRZ  UINT32_C(0x0)
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \
+		UINT32_C(0x0)
 	/* PAM4 signaling */
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_PAM4 UINT32_C(0x1)
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_LAST \
-		HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_PAM4
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \
+		UINT32_C(0x1)
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \
+		HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
+	/* This value indicates the current active FEC mode. */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \
+		UINT32_C(0xf0)
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT                  4
+	/* No active FEC */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \
+		(UINT32_C(0x0) << 4)
+	/* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \
+		(UINT32_C(0x1) << 4)
+	/* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \
+		(UINT32_C(0x2) << 4)
+	/* FEC RS544_1XN active, autonegoatiated or forced. */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \
+		(UINT32_C(0x3) << 4)
+	/* FEC RS(544,528) active, autonegoatiated or forced. */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \
+		(UINT32_C(0x4) << 4)
+	/* FEC RS272_1XN active, autonegotiated or forced. */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \
+		(UINT32_C(0x5) << 4)
+	/* FEC RS(272,257) active, autonegoatiated or forced. */
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \
+		(UINT32_C(0x6) << 4)
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \
+		HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
 	/*
 	 * This value indicates the current link speed of the connection.
-	 * The link_signal_mode field indicates if the link is using
+	 * The signal_mode field indicates if the link is using
 	 * NRZ or PAM4 signaling.
 	 */
 	uint16_t	link_speed;
@@ -16739,16 +18762,18 @@ struct hwrm_port_phy_qcfg_output {
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
 		UINT32_C(0x10)
 	/*
-	 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
-	 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
+	 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
+	 * NRZ) is supported on this port.
+	 * When set to 0, then FEC RS(528,418) is not supported on this port.
 	 */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
 		UINT32_C(0x20)
 	/*
-	 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this
-	 * port. This means that FEC CLAUSE 91 is either advertised if
-	 * FEC autonegotiation is enabled or FEC CLAUSE 91 is force enabled.
-	 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
+	 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
+	 * NRZ) is enabled on this port. This means that FEC RS(528,514) is
+	 * either advertised if FEC autonegotiation is enabled or FEC
+	 * RS(528,514) is force enabled.  When set to 0, then FEC RS(528,514)
+	 * is disabled if supported.
 	 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
 	 */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
@@ -16769,59 +18794,49 @@ struct hwrm_port_phy_qcfg_output {
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
 		UINT32_C(0x100)
 	/*
-	 * When set to 1, then FEC RS544_2XN is supported on this port.
-	 * When set to 0, then FEC RS544_2XN is not supported on this port.
+	 * When set to 1, then FEC RS(544,514) is supported on this port.
+	 * When set to 0, then FEC RS(544,514) is not supported on this port.
 	 */
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_SUPPORTED \
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \
 		UINT32_C(0x200)
 	/*
-	 * When set to 1, then RS544_2XN is enabled on this
-	 * port. This means that FEC RS544_2XN is either advertised if
-	 * FEC autonegotiation is enabled or FEC RS544_2XN is force enabled.
-	 * When set to 0, then FEC RS544_2XN is disabled if supported.
-	 * This flag should be ignored if FEC RS544_2XN is not supported on this port.
+	 * When set to 1, then RS(544,514) is enabled on this
+	 * port. This means that FEC RS(544,514) is either advertised if
+	 * FEC autonegotiation is enabled or FEC RS(544,514) is force
+	 * enabled.  When set to 0, then FEC RS(544,514) is disabled if supported.
+	 * This flag should be ignored if FEC RS(544,514) is not supported on this port.
 	 */
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ENABLED \
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \
 		UINT32_C(0x400)
 	/*
-	 * When set to 1, then FEC CLAUSE 74 (Fire Code) is active on this
-	 * port, either successfully autonegoatiated or forced.
-	 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not active.
-	 * This flag is only valid when link is up on this port.
-	 * At most only one active FEC flags (fec_clause74_active,
-	 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
+	 * When set to 1, then FEC RS272_1XN is supported on this port.
+	 * When set to 0, then FEC RS272_1XN is not supported on this port.
 	 */
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ACTIVE \
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \
 		UINT32_C(0x800)
 	/*
-	 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is active on this
-	 * port, either successfully autonegoatiated or forced.
-	 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not active.
-	 * This flag is only valid when link is up on this port.
-	 * At most only one active FEC flags (fec_clause74_active,
-	 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
+	 * When set to 1, then RS272_1XN is enabled on this
+	 * port. This means that FEC RS272_1XN is either advertised if
+	 * FEC autonegotiation is enabled or FEC RS272_1XN is force
+	 * enabled.  When set to 0, then FEC RS272_1XN is disabled if supported.
+	 * This flag should be ignored if FEC RS272_1XN is not supported on this port.
 	 */
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ACTIVE \
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \
 		UINT32_C(0x1000)
 	/*
-	 * When set to 1, then FEC RS544_1XN is active on this
-	 * port, either successfully autonegoatiated or forced.
-	 * When set to 0, then FEC RS544_1XN is not active.
-	 * This flag is only valid when link is up on this port.
-	 * At most only one active FEC flags (fec_clause74_active,
-	 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
+	 * When set to 1, then FEC RS(272,514) is supported on this port.
+	 * When set to 0, then FEC RS(272,514) is not supported on this port.
 	 */
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ACTIVE \
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \
 		UINT32_C(0x2000)
 	/*
-	 * When set to 1, then FEC RS544_2XN is active on this
-	 * port, either successfully autonegoatiated or forced.
-	 * When set to 0, then FEC RS544_2XN is not active.
-	 * This flag is only valid when link is up on this port.
-	 * At most only one active FEC flags (fec_clause74_active,
-	 * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.
+	 * When set to 1, then RS(272,257) is enabled on this
+	 * port. This means that FEC RS(272,257) is either advertised if
+	 * FEC autonegotiation is enabled or FEC RS(272,257) is force
+	 * enabled.  When set to 0, then FEC RS(272,257) is disabled if supported.
+	 * This flag should be ignored if FEC RS(272,257) is not supported on this port.
 	 */
-	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ACTIVE \
+	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \
 		UINT32_C(0x4000)
 	/*
 	 * This value is indicates the duplex of the current
@@ -16900,7 +18915,7 @@ struct hwrm_port_phy_qcfg_output {
 	 * The advertised PAM4 speeds for the port by the link partner.
 	 * Each advertised speed will be set to '1'.
 	 */
-	uint16_t	link_partner_pam4_adv_speeds;
+	uint8_t	link_partner_pam4_adv_speeds;
 	/* 50Gb link speed */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
 		UINT32_C(0x1)
@@ -16910,7 +18925,6 @@ struct hwrm_port_phy_qcfg_output {
 	/* 200Gb link speed */
 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
 		UINT32_C(0x4)
-	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -19110,7 +21124,7 @@ struct hwrm_port_lpbk_qstats_output {
  ************************/
 
 
-/* hwrm_port_ecn_qstats_input (size:192b/24B) */
+/* hwrm_port_ecn_qstats_input (size:256b/32B) */
 struct hwrm_port_ecn_qstats_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
@@ -19145,10 +21159,31 @@ struct hwrm_port_ecn_qstats_input {
 	 * multi-host mode.
 	 */
 	uint16_t	port_id;
-	uint8_t	unused_0[6];
+	/*
+	 * Size of the DMA buffer the caller has allocated for the firmware to
+	 * write into.
+	 */
+	uint16_t	ecn_stat_buf_size;
+	uint8_t	flags;
+	/* This value is not used to avoid backward compatibility issues. */
+	#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED       UINT32_C(0x0)
+	/*
+	 * This bit is set to 1 when request is for a counter mask,
+	 * representing the width of each of the stats counters, rather
+	 * than counters themselves.
+	 */
+	#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
+	#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
+		HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
+	uint8_t	unused_0[3];
+	/*
+	 * This is the host address where
+	 * ECN port statistics will be stored
+	 */
+	uint64_t	ecn_stat_host_addr;
 } __rte_packed;
 
-/* hwrm_port_ecn_qstats_output (size:384b/48B) */
+/* hwrm_port_ecn_qstats_output (size:128b/16B) */
 struct hwrm_port_ecn_qstats_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
@@ -19158,28 +21193,14 @@ struct hwrm_port_ecn_qstats_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Number of packets marked in CoS queue 0. */
-	uint32_t	mark_cnt_cos0;
-	/* Number of packets marked in CoS queue 1. */
-	uint32_t	mark_cnt_cos1;
-	/* Number of packets marked in CoS queue 2. */
-	uint32_t	mark_cnt_cos2;
-	/* Number of packets marked in CoS queue 3. */
-	uint32_t	mark_cnt_cos3;
-	/* Number of packets marked in CoS queue 4. */
-	uint32_t	mark_cnt_cos4;
-	/* Number of packets marked in CoS queue 5. */
-	uint32_t	mark_cnt_cos5;
-	/* Number of packets marked in CoS queue 6. */
-	uint32_t	mark_cnt_cos6;
-	/* Number of packets marked in CoS queue 7. */
-	uint32_t	mark_cnt_cos7;
+	/* Number of bytes of stats the firmware wrote to the DMA buffer. */
+	uint16_t	ecn_stat_buf_size;
 	/*
 	 * Bitmask that indicates which CoS queues have ECN marking enabled.
 	 * Bit i corresponds to CoS queue i.
 	 */
 	uint8_t	mark_en;
-	uint8_t	unused_0[6];
+	uint8_t	unused_0[4];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -19190,6 +21211,59 @@ struct hwrm_port_ecn_qstats_output {
 	uint8_t	valid;
 } __rte_packed;
 
+/* ECN mark statistics format */
+/* port_stats_ecn (size:512b/64B) */
+struct port_stats_ecn {
+	/*
+	 * Number of packets marked in CoS queue 0.
+	 * Or, if the driver requested counter masks, a mask to indicate the size
+	 * of the counter.
+	 */
+	uint64_t	mark_cnt_cos0;
+	/*
+	 * Number of packets marked in CoS queue 1.
+	 * Or, if the driver requested counter masks, a mask to indicate the size
+	 * of the counter.
+	 */
+	uint64_t	mark_cnt_cos1;
+	/*
+	 * Number of packets marked in CoS queue 2.
+	 * Or, if the driver requested counter masks, a mask to indicate the size
+	 * of the counter.
+	 */
+	uint64_t	mark_cnt_cos2;
+	/*
+	 * Number of packets marked in CoS queue 3.
+	 * Or, if the driver requested counter masks, a mask to indicate the size
+	 * of the counter.
+	 */
+	uint64_t	mark_cnt_cos3;
+	/*
+	 * Number of packets marked in CoS queue 4.
+	 * Or, if the driver requested counter masks, a mask to indicate the size
+	 * of the counter.
+	 */
+	uint64_t	mark_cnt_cos4;
+	/*
+	 * Number of packets marked in CoS queue 5.
+	 * Or, if the driver requested counter masks, a mask to indicate the size
+	 * of the counter.
+	 */
+	uint64_t	mark_cnt_cos5;
+	/*
+	 * Number of packets marked in CoS queue 6.
+	 * Or, if the driver requested counter masks, a mask to indicate the size
+	 * of the counter.
+	 */
+	uint64_t	mark_cnt_cos6;
+	/*
+	 * Number of packets marked in CoS queue 7.
+	 * Or, if the driver requested counter masks, a mask to indicate the size
+	 * of the counter.
+	 */
+	uint64_t	mark_cnt_cos7;
+} __rte_packed;
+
 /***********************
  * hwrm_port_clr_stats *
  ***********************/
@@ -19351,14 +21425,20 @@ struct hwrm_port_phy_qcaps_output {
 	 */
 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
 		UINT32_C(0x10)
+	/*
+	 * If set to 1, then this field indicates that the
+	 * local loopback is not supported on this controller.
+	 */
+	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \
+		UINT32_C(0x20)
 	/*
 	 * Reserved field. The HWRM shall set this field to 0.
 	 * An HWRM client shall ignore this field.
 	 */
 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
-		UINT32_C(0xe0)
+		UINT32_C(0xc0)
 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \
-		5
+		6
 	/* Number of front panel ports for this device. */
 	uint8_t	port_cnt;
 	/* Not supported or unknown */
@@ -21479,6 +23559,161 @@ struct hwrm_port_phy_mdio_bus_release_output {
 	uint8_t	valid;
 } __rte_packed;
 
+/************************
+ * hwrm_port_tx_fir_cfg *
+ ************************/
+
+
+/* hwrm_port_tx_fir_cfg_input (size:320b/40B) */
+struct hwrm_port_tx_fir_cfg_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* Modulation types of TX FIR: NRZ, PAM4. */
+	uint8_t	mod_type;
+	/* For NRZ */
+	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ  UINT32_C(0x0)
+	/* For PAM4 */
+	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
+	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \
+		HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4
+	/* The lane mask of the lane TX FIR will be configured. */
+	uint8_t	lane_mask;
+	uint8_t	unused_0[2];
+	/* Value1 of TX FIR, required for NRZ or PAM4. */
+	uint32_t	txfir_val_1;
+	/* Value2 of TX FIR, required for NRZ or PAM4. */
+	uint32_t	txfir_val_2;
+	/* Value3 of TX FIR, required for PAM4. */
+	uint32_t	txfir_val_3;
+	/* Value4 of TX FIR, required for PAM4. */
+	uint32_t	txfir_val_4;
+	uint8_t	unused_1[4];
+} __rte_packed;
+
+/* hwrm_port_tx_fir_cfg_output (size:128b/16B) */
+struct hwrm_port_tx_fir_cfg_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	unused[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_port_tx_fir_qcfg *
+ *************************/
+
+
+/* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */
+struct hwrm_port_tx_fir_qcfg_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* Modulation types of TX FIR: NRZ, PAM4. */
+	uint8_t	mod_type;
+	/* For NRZ */
+	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ  UINT32_C(0x0)
+	/* For PAM4 */
+	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
+	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \
+		HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4
+	/* The ID of the lane TX FIR will be queried. */
+	uint8_t	lane_id;
+	uint8_t	unused[6];
+} __rte_packed;
+
+/* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */
+struct hwrm_port_tx_fir_qcfg_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* Value1 of TX FIR, required for NRZ or PAM4. */
+	uint32_t	txfir_val_1;
+	/* Value2 of TX FIR, required for NRZ or PAM4. */
+	uint32_t	txfir_val_2;
+	/* Value3 of TX FIR, required for PAM4. */
+	uint32_t	txfir_val_3;
+	/* Value4 of TX FIR, required for PAM4. */
+	uint32_t	txfir_val_4;
+	uint8_t	unused[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
 /***********************
  * hwrm_queue_qportcfg *
  ***********************/
@@ -21642,8 +23877,10 @@ struct hwrm_queue_qportcfg_output {
 	 * that takes a queue id.
 	 * # IDs must always be queried by this command before any use
 	 * by the driver or software.
-	 * # Any driver or software should not make any assumptions about
-	 * queue IDs.
+	 * # The CoS queue index is obtained by applying modulo 10 to the
+	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+	 * The CoS queue index is used to reference port statistics for the
+	 * CoS queue.
 	 * # A value of 0xff indicates that the queue is not available.
 	 * # Available queues may not be in sequential order.
 	 */
@@ -21678,8 +23915,10 @@ struct hwrm_queue_qportcfg_output {
 	 * that takes a queue id.
 	 * # IDs must always be queried by this command before any use
 	 * by the driver or software.
-	 * # Any driver or software should not make any assumptions about
-	 * queue IDs.
+	 * # The CoS queue index is obtained by applying modulo 10 to the
+	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+	 * The CoS queue index is used to reference port statistics for the
+	 * CoS queue.
 	 * # A value of 0xff indicates that the queue is not available.
 	 * # Available queues may not be in sequential order.
 	 */
@@ -21714,8 +23953,10 @@ struct hwrm_queue_qportcfg_output {
 	 * that takes a queue id.
 	 * # IDs must always be queried by this command before any use
 	 * by the driver or software.
-	 * # Any driver or software should not make any assumptions about
-	 * queue IDs.
+	 * # The CoS queue index is obtained by applying modulo 10 to the
+	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+	 * The CoS queue index is used to reference port statistics for the
+	 * CoS queue.
 	 * # A value of 0xff indicates that the queue is not available.
 	 * # Available queues may not be in sequential order.
 	 */
@@ -21750,8 +23991,10 @@ struct hwrm_queue_qportcfg_output {
 	 * that takes a queue id.
 	 * # IDs must always be queried by this command before any use
 	 * by the driver or software.
-	 * # Any driver or software should not make any assumptions about
-	 * queue IDs.
+	 * # The CoS queue index is obtained by applying modulo 10 to the
+	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+	 * The CoS queue index is used to reference port statistics for the
+	 * CoS queue.
 	 * # A value of 0xff indicates that the queue is not available.
 	 * # Available queues may not be in sequential order.
 	 */
@@ -21786,8 +24029,10 @@ struct hwrm_queue_qportcfg_output {
 	 * that takes a queue id.
 	 * # IDs must always be queried by this command before any use
 	 * by the driver or software.
-	 * # Any driver or software should not make any assumptions about
-	 * queue IDs.
+	 * # The CoS queue index is obtained by applying modulo 10 to the
+	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+	 * The CoS queue index is used to reference port statistics for the
+	 * CoS queue.
 	 * # A value of 0xff indicates that the queue is not available.
 	 * # Available queues may not be in sequential order.
 	 */
@@ -21822,8 +24067,10 @@ struct hwrm_queue_qportcfg_output {
 	 * that takes a queue id.
 	 * # IDs must always be queried by this command before any use
 	 * by the driver or software.
-	 * # Any driver or software should not make any assumptions about
-	 * queue IDs.
+	 * # The CoS queue index is obtained by applying modulo 10 to the
+	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+	 * The CoS queue index is used to reference port statistics for the
+	 * CoS queue.
 	 * # A value of 0xff indicates that the queue is not available.
 	 * # Available queues may not be in sequential order.
 	 */
@@ -21858,8 +24105,10 @@ struct hwrm_queue_qportcfg_output {
 	 * that takes a queue id.
 	 * # IDs must always be queried by this command before any use
 	 * by the driver or software.
-	 * # Any driver or software should not make any assumptions about
-	 * queue IDs.
+	 * # The CoS queue index is obtained by applying modulo 10 to the
+	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+	 * The CoS queue index is used to reference port statistics for the
+	 * CoS queue.
 	 * # A value of 0xff indicates that the queue is not available.
 	 * # Available queues may not be in sequential order.
 	 */
@@ -21894,8 +24143,10 @@ struct hwrm_queue_qportcfg_output {
 	 * that takes a queue id.
 	 * # IDs must always be queried by this command before any use
 	 * by the driver or software.
-	 * # Any driver or software should not make any assumptions about
-	 * queue IDs.
+	 * # The CoS queue index is obtained by applying modulo 10 to the
+	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+	 * The CoS queue index is used to reference port statistics for the
+	 * CoS queue.
 	 * # A value of 0xff indicates that the queue is not available.
 	 * # Available queues may not be in sequential order.
 	 */
@@ -27251,6 +29502,12 @@ struct hwrm_ring_alloc_input {
 	 */
 	#define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
 		UINT32_C(0x200)
+	/*
+	 * This bit must be '1' for the mpc_chnls_type field to be
+	 * configured.
+	 */
+	#define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \
+		UINT32_C(0x400)
 	/* Ring Type. */
 	uint8_t	ring_type;
 	/* L2 Completion Ring (CR) */
@@ -27483,7 +29740,36 @@ struct hwrm_ring_alloc_input {
 	#define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL   UINT32_C(0x3)
 	#define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
 		HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
-	uint8_t	unused_4[3];
+	/* Midpath channel type */
+	uint8_t	mpc_chnls_type;
+	/*
+	 * Indicate the TX ring alloc MPC channel type is a MPC channel
+	 * with destination to the TX crypto engine block.
+	 */
+	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE     UINT32_C(0x0)
+	/*
+	 * Indicate the RX ring alloc MPC channel type is a MPC channel
+	 * with destination to the RX crypto engine block.
+	 */
+	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE     UINT32_C(0x1)
+	/*
+	 * Indicate the RX ring alloc MPC channel type is a MPC channel
+	 * with destination to the TX configurable flow processing block.
+	 */
+	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA  UINT32_C(0x2)
+	/*
+	 * Indicate the RX ring alloc MPC channel type is a MPC channel
+	 * with destination to the RX configurable flow processing block.
+	 */
+	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA  UINT32_C(0x3)
+	/*
+	 * Indicate the RX ring alloc MPC channel type is a MPC channel
+	 * with destination to the primate processor block.
+	 */
+	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
+	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \
+		HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE
+	uint8_t	unused_4[2];
 	/*
 	 * The cq_handle is specified when allocating a completion ring. For
 	 * devices that support NQs, this cq_handle will be included in the
@@ -35339,13 +37625,13 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**********************
- * hwrm_cfa_pair_info *
- **********************/
+/**************************
+ * hwrm_cfa_vf_pair_alloc *
+ **************************/
 
 
-/* hwrm_cfa_pair_info_input (size:448b/56B) */
-struct hwrm_cfa_pair_info_input {
+/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
+struct hwrm_cfa_vf_pair_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -35374,23 +37660,17 @@ struct hwrm_cfa_pair_info_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	flags;
-	/* If this flag is set, lookup by name else lookup by index. */
-	#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE      UINT32_C(0x1)
-	/* If this flag is set, lookup by PF id and VF id. */
-	#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE     UINT32_C(0x2)
-	/* Pair table index. */
-	uint16_t	pair_index;
-	/* Pair pf index. */
-	uint8_t	pair_pfid;
-	/* Pair vf index. */
-	uint8_t	pair_vfid;
-	/* Pair name (32 byte string). */
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_a_id;
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_b_id;
+	uint8_t	unused_0[4];
+	/* VF Pair name (32 byte string). */
 	char	pair_name[32];
 } __rte_packed;
 
-/* hwrm_cfa_pair_info_output (size:576b/72B) */
-struct hwrm_cfa_pair_info_output {
+/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
+struct hwrm_cfa_vf_pair_alloc_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -35399,56 +37679,6 @@ struct hwrm_cfa_pair_info_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Pair table index. */
-	uint16_t	next_pair_index;
-	/* Pair member a's fid. */
-	uint16_t	a_fid;
-	/* Logical host number. */
-	uint8_t	host_a_index;
-	/* Logical PF number. */
-	uint8_t	pf_a_index;
-	/* Pair member a's Linux logical VF number. */
-	uint16_t	vf_a_index;
-	/* Rx CFA code. */
-	uint16_t	rx_cfa_code_a;
-	/* Tx CFA action. */
-	uint16_t	tx_cfa_action_a;
-	/* Pair member b's fid. */
-	uint16_t	b_fid;
-	/* Logical host number. */
-	uint8_t	host_b_index;
-	/* Logical PF number. */
-	uint8_t	pf_b_index;
-	/* Pair member a's Linux logical VF number. */
-	uint16_t	vf_b_index;
-	/* Rx CFA code. */
-	uint16_t	rx_cfa_code_b;
-	/* Tx CFA action. */
-	uint16_t	tx_cfa_action_b;
-	/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
-	uint8_t	pair_mode;
-	/* Pair between VF on local host with PF or VF on specified host. */
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN   UINT32_C(0x0)
-	/* Pair between REP on local host with PF or VF on specified host. */
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN  UINT32_C(0x1)
-	/* Pair between REP on local host with REP on specified host. */
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
-	/* Pair for the proxy interface. */
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY   UINT32_C(0x3)
-	/* Pair for the PF interface. */
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR  UINT32_C(0x4)
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
-		HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
-	/* Pair state. */
-	uint8_t	pair_state;
-	/* Pair has been allocated */
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
-	/* Both pair members are active */
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE    UINT32_C(0x2)
-	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
-		HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
-	/* Pair name (32 byte string). */
-	char	pair_name[32];
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -35460,85 +37690,13 @@ struct hwrm_cfa_pair_info_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**********************
- * hwrm_cfa_vfr_alloc *
- **********************/
-
-
-/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
-struct hwrm_cfa_vfr_alloc_input {
-	/* The HWRM command request type. */
-	uint16_t	req_type;
-	/*
-	 * The completion ring to send the completion event on. This should
-	 * be the NQ ID returned from the `nq_alloc` HWRM command.
-	 */
-	uint16_t	cmpl_ring;
-	/*
-	 * The sequence ID is used by the driver for tracking multiple
-	 * commands. This ID is treated as opaque data by the firmware and
-	 * the value is returned in the `hwrm_resp_hdr` upon completion.
-	 */
-	uint16_t	seq_id;
-	/*
-	 * The target ID of the command:
-	 * * 0x0-0xFFF8 - The function ID
-	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
-	 * * 0xFFFD - Reserved for user-space HWRM interface
-	 * * 0xFFFF - HWRM
-	 */
-	uint16_t	target_id;
-	/*
-	 * A physical address pointer pointing to a host buffer that the
-	 * command's response data will be written. This can be either a host
-	 * physical address (HPA) or a guest physical address (GPA) and must
-	 * point to a physically contiguous block of memory.
-	 */
-	uint64_t	resp_addr;
-	/* Logical VF number (range: 0 -> MAX_VFS -1). */
-	uint16_t	vf_id;
-	/*
-	 * This field is reserved for the future use.
-	 * It shall be set to 0.
-	 */
-	uint16_t	reserved;
-	uint8_t	unused_0[4];
-	/* VF Representor name (32 byte string). */
-	char	vfr_name[32];
-} __rte_packed;
-
-/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
-struct hwrm_cfa_vfr_alloc_output {
-	/* The specific error status for the command. */
-	uint16_t	error_code;
-	/* The HWRM command request type. */
-	uint16_t	req_type;
-	/* The sequence ID from the original command. */
-	uint16_t	seq_id;
-	/* The length of the response data in number of bytes. */
-	uint16_t	resp_len;
-	/* Rx CFA code. */
-	uint16_t	rx_cfa_code;
-	/* Tx CFA action. */
-	uint16_t	tx_cfa_action;
-	uint8_t	unused_0[3];
-	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
-	 */
-	uint8_t	valid;
-} __rte_packed;
-
-/*********************
- * hwrm_cfa_vfr_free *
- *********************/
+/*************************
+ * hwrm_cfa_vf_pair_free *
+ *************************/
 
 
-/* hwrm_cfa_vfr_free_input (size:448b/56B) */
-struct hwrm_cfa_vfr_free_input {
+/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
+struct hwrm_cfa_vf_pair_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -35567,16 +37725,12 @@ struct hwrm_cfa_vfr_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* VF Representor name (32 byte string). */
-	char		vfr_name[32];
-	/* Logical VF number (range: 0 -> MAX_VFS -1). */
-	uint16_t	vf_id;
-	uint16_t	reserved;
-	uint8_t		unused_0[4];
+	/* VF Pair name (32 byte string). */
+	char	pair_name[32];
 } __rte_packed;
 
-/* hwrm_cfa_vfr_free_output (size:128b/16B) */
-struct hwrm_cfa_vfr_free_output {
+/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
+struct hwrm_cfa_vf_pair_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -35588,7 +37742,7 @@ struct hwrm_cfa_vfr_free_output {
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
+	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
 	 * When writing a command completion or response to an internal processor,
 	 * the order of writes has to be such that this field is written last.
@@ -35596,15 +37750,13 @@ struct hwrm_cfa_vfr_free_output {
 	uint8_t	valid;
 } __rte_packed;
 
+/*************************
+ * hwrm_cfa_vf_pair_info *
+ *************************/
 
 
-/***************************************
- * hwrm_cfa_redirect_query_tunnel_type *
- ***************************************/
-
-
-/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
-struct hwrm_cfa_redirect_query_tunnel_type_input {
+/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_vf_pair_info_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -35633,13 +37785,18 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* The source function id. */
-	uint16_t	src_fid;
-	uint8_t	unused_0[6];
+	uint32_t	flags;
+	/* If this flag is set, lookup by name else lookup by index. */
+	#define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE     UINT32_C(0x1)
+	/* vf pair table index. */
+	uint16_t	vf_pair_index;
+	uint8_t	unused_0[2];
+	/* VF Pair name (32 byte string). */
+	char	vf_pair_name[32];
 } __rte_packed;
 
-/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
-struct hwrm_cfa_redirect_query_tunnel_type_output {
+/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
+struct hwrm_cfa_vf_pair_info_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -35648,51 +37805,28 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Tunnel Mask. */
-	uint32_t	tunnel_mask;
-	/* Non-tunnel */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
-		UINT32_C(0x1)
-	/* Virtual eXtensible Local Area Network (VXLAN) */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
-		UINT32_C(0x2)
-	/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
-		UINT32_C(0x4)
-	/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
-		UINT32_C(0x8)
-	/* IP in IP */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
-		UINT32_C(0x10)
-	/* Generic Network Virtualization Encapsulation (Geneve) */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
-		UINT32_C(0x20)
-	/* Multi-Protocol Label Switching (MPLS) */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
-		UINT32_C(0x40)
-	/* Stateless Transport Tunnel (STT) */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
-		UINT32_C(0x80)
-	/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
-		UINT32_C(0x100)
-	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
-		UINT32_C(0x200)
-	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
-		UINT32_C(0x400)
-	/* Any tunneled traffic */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
-		UINT32_C(0x800)
-	/* Use fixed layer 2 ether type of 0xFFFF */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
-		UINT32_C(0x1000)
-	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
-	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
-		UINT32_C(0x2000)
-	uint8_t	unused_0[3];
+	/* vf pair table index. */
+	uint16_t	next_vf_pair_index;
+	/* vf pair member a's vf_fid. */
+	uint16_t	vf_a_fid;
+	/* vf pair member a's Linux logical VF number. */
+	uint16_t	vf_a_index;
+	/* vf pair member b's vf_fid. */
+	uint16_t	vf_b_fid;
+	/* vf pair member a's Linux logical VF number. */
+	uint16_t	vf_b_index;
+	/* vf pair state. */
+	uint8_t	pair_state;
+	/* Pair has been allocated */
+	#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
+	/* Both pair members are active */
+	#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE    UINT32_C(0x2)
+	#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
+		HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
+	uint8_t	unused_0[5];
+	/* VF Pair name (32 byte string). */
+	char	pair_name[32];
+	uint8_t	unused_1[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -35703,13 +37837,13 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*************************
- * hwrm_cfa_ctx_mem_rgtr *
- *************************/
+/***********************
+ * hwrm_cfa_pair_alloc *
+ ***********************/
 
 
-/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
-struct hwrm_cfa_ctx_mem_rgtr_input {
+/* hwrm_cfa_pair_alloc_input (size:576b/72B) */
+struct hwrm_cfa_pair_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -35738,44 +37872,104 @@ struct hwrm_cfa_ctx_mem_rgtr_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint16_t	flags;
-	/* Counter PBL indirect levels. */
-	uint8_t	page_level;
-	/* PBL pointer is physical start address. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
-	/* PBL pointer points to PTE table. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
-	/* PBL pointer points to PDE table with each entry pointing to PTE tables. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
-		HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
-	/* Page size. */
-	uint8_t	page_size;
-	/* 4KB page size. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K   UINT32_C(0x0)
-	/* 8KB page size. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K   UINT32_C(0x1)
-	/* 64KB page size. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K  UINT32_C(0x4)
-	/* 256KB page size. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
-	/* 1MB page size. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M   UINT32_C(0x8)
-	/* 2MB page size. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M   UINT32_C(0x9)
-	/* 4MB page size. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M   UINT32_C(0xa)
-	/* 1GB page size. */
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)
-	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
-		HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
-	uint32_t	unused_0;
-	/* Pointer to the PBL, or PDL depending on number of levels */
-	uint64_t	page_dir;
+	/*
+	 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
+	 *            5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
+	 */
+	uint16_t	pair_mode;
+	/* Pair between VF on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
+		UINT32_C(0x0)
+	/* Pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
+		UINT32_C(0x1)
+	/* Pair between REP on local host with REP on specified host. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
+		UINT32_C(0x2)
+	/* Pair for the proxy interface. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
+		UINT32_C(0x3)
+	/* Pair for the PF interface. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
+		UINT32_C(0x4)
+	/* Modify existing rep2fn pair and move pair to new PF. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
+		UINT32_C(0x5)
+	/* Modify exsiting rep2fn pairs paired with same PF and move pairs to new PF. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
+		UINT32_C(0x6)
+	/* Truflow pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
+		UINT32_C(0x7)
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
+		HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_a_id;
+	/* Logical Host (0xff-local host). */
+	uint8_t	host_b_id;
+	/* Logical PF (0xff-PF for command channel). */
+	uint8_t	pf_b_id;
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_b_id;
+	/* Loopback port (0xff-internal loopback), valid for mode-3. */
+	uint8_t	port_id;
+	/* Priority used for encap of loopback packets valid for mode-3. */
+	uint8_t	pri;
+	/* New PF for rep2fn modify, valid for mode 5. */
+	uint16_t	new_pf_fid;
+	uint32_t	enables;
+	/*
+	 * This bit must be '1' for the q_ab field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID      UINT32_C(0x1)
+	/*
+	 * This bit must be '1' for the q_ba field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID      UINT32_C(0x2)
+	/*
+	 * This bit must be '1' for the fc_ab field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID     UINT32_C(0x4)
+	/*
+	 * This bit must be '1' for the fc_ba field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID     UINT32_C(0x8)
+	/* VF Pair name (32 byte string). */
+	char	pair_name[32];
+	/*
+	 * The q_ab value specifies the logical index of the TX/RX CoS
+	 * queue to be assigned for traffic in the A to B direction of
+	 * the interface pair. The default value is 0.
+	 */
+	uint8_t	q_ab;
+	/*
+	 * The q_ba value specifies the logical index of the TX/RX CoS
+	 * queue to be assigned for traffic in the B to A direction of
+	 * the interface pair. The default value is 1.
+	 */
+	uint8_t	q_ba;
+	/*
+	 * Specifies whether RX ring flow control is disabled (0) or enabled
+	 * (1) in the A to B direction. The default value is 0, meaning that
+	 * packets will be dropped when the B-side RX rings are full.
+	 */
+	uint8_t	fc_ab;
+	/*
+	 * Specifies whether RX ring flow control is disabled (0) or enabled
+	 * (1) in the B to A direction. The default value is 1, meaning that
+	 * the RX CoS queue will be flow controlled when the A-side RX rings
+	 * are full.
+	 */
+	uint8_t	fc_ba;
+	uint8_t	unused_1[4];
 } __rte_packed;
 
-/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
-struct hwrm_cfa_ctx_mem_rgtr_output {
+/* hwrm_cfa_pair_alloc_output (size:192b/24B) */
+struct hwrm_cfa_pair_alloc_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -35784,12 +37978,15 @@ struct hwrm_cfa_ctx_mem_rgtr_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/*
-	 * Id/Handle to the recently register context memory. This handle is passed
-	 * to the CFA feature.
-	 */
-	uint16_t	ctx_id;
-	uint8_t	unused_0[5];
+	/* Only valid for modes 1 and 2. */
+	uint16_t	rx_cfa_code_a;
+	/* Only valid for modes 1 and 2. */
+	uint16_t	tx_cfa_action_a;
+	/* Only valid for mode 2. */
+	uint16_t	rx_cfa_code_b;
+	/* Only valid for mode 2. */
+	uint16_t	tx_cfa_action_b;
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -35800,13 +37997,13 @@ struct hwrm_cfa_ctx_mem_rgtr_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/***************************
- * hwrm_cfa_ctx_mem_unrgtr *
- ***************************/
+/**********************
+ * hwrm_cfa_pair_free *
+ **********************/
 
 
-/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
-struct hwrm_cfa_ctx_mem_unrgtr_input {
+/* hwrm_cfa_pair_free_input (size:448b/56B) */
+struct hwrm_cfa_pair_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -35835,16 +38032,40 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* VF Pair name (32 byte string). */
+	char	pair_name[32];
+	/* Logical PF (0xff-PF for command channel). */
+	uint8_t	pf_b_id;
+	uint8_t	unused_0[3];
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_id;
 	/*
-	 * Id/Handle to the recently register context memory. This handle is passed
-	 * to the CFA feature.
+	 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
+	 *            5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
 	 */
-	uint16_t	ctx_id;
-	uint8_t	unused_0[6];
+	uint16_t	pair_mode;
+	/* Pair between VF on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN          UINT32_C(0x0)
+	/* Pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN         UINT32_C(0x1)
+	/* Pair between REP on local host with REP on specified host. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP        UINT32_C(0x2)
+	/* Pair for the proxy interface. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY          UINT32_C(0x3)
+	/* Pair for the PF interface. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR         UINT32_C(0x4)
+	/* Modify existing rep2fn pair and move pair to new PF. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD     UINT32_C(0x5)
+	/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL  UINT32_C(0x6)
+	/* Truflow pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
+		HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
 } __rte_packed;
 
-/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
-struct hwrm_cfa_ctx_mem_unrgtr_output {
+/* hwrm_cfa_pair_free_output (size:128b/16B) */
+struct hwrm_cfa_pair_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -35864,13 +38085,13 @@ struct hwrm_cfa_ctx_mem_unrgtr_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*************************
- * hwrm_cfa_ctx_mem_qctx *
- *************************/
+/**********************
+ * hwrm_cfa_pair_info *
+ **********************/
 
 
-/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
-struct hwrm_cfa_ctx_mem_qctx_input {
+/* hwrm_cfa_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_pair_info_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -35899,16 +38120,23 @@ struct hwrm_cfa_ctx_mem_qctx_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/*
-	 * Id/Handle to the recently register context memory. This handle is passed
-	 * to the CFA feature.
-	 */
-	uint16_t	ctx_id;
-	uint8_t	unused_0[6];
+	uint32_t	flags;
+	/* If this flag is set, lookup by name else lookup by index. */
+	#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE      UINT32_C(0x1)
+	/* If this flag is set, lookup by PF id and VF id. */
+	#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE     UINT32_C(0x2)
+	/* Pair table index. */
+	uint16_t	pair_index;
+	/* Pair pf index. */
+	uint8_t	pair_pfid;
+	/* Pair vf index. */
+	uint8_t	pair_vfid;
+	/* Pair name (32 byte string). */
+	char	pair_name[32];
 } __rte_packed;
 
-/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
-struct hwrm_cfa_ctx_mem_qctx_output {
+/* hwrm_cfa_pair_info_output (size:576b/72B) */
+struct hwrm_cfa_pair_info_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -35917,41 +38145,57 @@ struct hwrm_cfa_ctx_mem_qctx_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint16_t	flags;
-	/* Counter PBL indirect levels. */
-	uint8_t	page_level;
-	/* PBL pointer is physical start address. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
-	/* PBL pointer points to PTE table. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
-	/* PBL pointer points to PDE table with each entry pointing to PTE tables. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
-		HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
-	/* Page size. */
-	uint8_t	page_size;
-	/* 4KB page size. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K   UINT32_C(0x0)
-	/* 8KB page size. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K   UINT32_C(0x1)
-	/* 64KB page size. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K  UINT32_C(0x4)
-	/* 256KB page size. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
-	/* 1MB page size. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M   UINT32_C(0x8)
-	/* 2MB page size. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M   UINT32_C(0x9)
-	/* 4MB page size. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M   UINT32_C(0xa)
-	/* 1GB page size. */
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G   UINT32_C(0x12)
-	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
-		HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
-	uint8_t	unused_0[4];
-	/* Pointer to the PBL, or PDL depending on number of levels */
-	uint64_t	page_dir;
-	uint8_t	unused_1[7];
+	/* Pair table index. */
+	uint16_t	next_pair_index;
+	/* Pair member a's fid. */
+	uint16_t	a_fid;
+	/* Logical host number. */
+	uint8_t	host_a_index;
+	/* Logical PF number. */
+	uint8_t	pf_a_index;
+	/* Pair member a's Linux logical VF number. */
+	uint16_t	vf_a_index;
+	/* Rx CFA code. */
+	uint16_t	rx_cfa_code_a;
+	/* Tx CFA action. */
+	uint16_t	tx_cfa_action_a;
+	/* Pair member b's fid. */
+	uint16_t	b_fid;
+	/* Logical host number. */
+	uint8_t	host_b_index;
+	/* Logical PF number. */
+	uint8_t	pf_b_index;
+	/* Pair member a's Linux logical VF number. */
+	uint16_t	vf_b_index;
+	/* Rx CFA code. */
+	uint16_t	rx_cfa_code_b;
+	/* Tx CFA action. */
+	uint16_t	tx_cfa_action_b;
+	/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
+	uint8_t	pair_mode;
+	/* Pair between VF on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN   UINT32_C(0x0)
+	/* Pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN  UINT32_C(0x1)
+	/* Pair between REP on local host with REP on specified host. */
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
+	/* Pair for the proxy interface. */
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY   UINT32_C(0x3)
+	/* Pair for the PF interface. */
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR  UINT32_C(0x4)
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
+		HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
+	/* Pair state. */
+	uint8_t	pair_state;
+	/* Pair has been allocated */
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
+	/* Both pair members are active */
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE    UINT32_C(0x2)
+	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
+		HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
+	/* Pair name (32 byte string). */
+	char	pair_name[32];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -35962,13 +38206,13 @@ struct hwrm_cfa_ctx_mem_qctx_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**************************
- * hwrm_cfa_ctx_mem_qcaps *
- **************************/
+/**********************
+ * hwrm_cfa_vfr_alloc *
+ **********************/
 
 
-/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
-struct hwrm_cfa_ctx_mem_qcaps_input {
+/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
+struct hwrm_cfa_vfr_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -35997,10 +38241,20 @@ struct hwrm_cfa_ctx_mem_qcaps_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_id;
+	/*
+	 * This field is reserved for the future use.
+	 * It shall be set to 0.
+	 */
+	uint16_t	reserved;
+	uint8_t	unused_0[4];
+	/* VF Representor name (32 byte string). */
+	char	vfr_name[32];
 } __rte_packed;
 
-/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
-struct hwrm_cfa_ctx_mem_qcaps_output {
+/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
+struct hwrm_cfa_vfr_alloc_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36009,9 +38263,11 @@ struct hwrm_cfa_ctx_mem_qcaps_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Indicates the maximum number of context memory which can be registered. */
-	uint16_t	max_entries;
-	uint8_t	unused_0[5];
+	/* Rx CFA code. */
+	uint16_t	rx_cfa_code;
+	/* Tx CFA action. */
+	uint16_t	tx_cfa_action;
+	uint8_t	unused_0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -36022,13 +38278,13 @@ struct hwrm_cfa_ctx_mem_qcaps_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**********************
- * hwrm_cfa_eem_qcaps *
- **********************/
+/*********************
+ * hwrm_cfa_vfr_free *
+ *********************/
 
 
-/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
-struct hwrm_cfa_eem_qcaps_input {
+/* hwrm_cfa_vfr_free_input (size:448b/56B) */
+struct hwrm_cfa_vfr_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36057,29 +38313,20 @@ struct hwrm_cfa_eem_qcaps_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	flags;
-	/*
-	 * When set to 1, indicates the configuration will apply to TX flows
-	 * which are to be offloaded.
-	 * Note if this bit is set then the path_rx bit can't be set.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
-		UINT32_C(0x1)
+	/* VF Representor name (32 byte string). */
+	char	vfr_name[32];
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_id;
 	/*
-	 * When set to 1, indicates the configuration will apply to RX flows
-	 * which are to be offloaded.
-	 * Note if this bit is set then the path_tx bit can't be set.
+	 * This field is reserved for the future use.
+	 * It shall be set to 0.
 	 */
-	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
-		UINT32_C(0x2)
-	/* When set to 1, all offloaded flows will be sent to EEM. */
-	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
-		UINT32_C(0x4)
-	uint32_t	unused_0;
+	uint16_t	reserved;
+	uint8_t	unused_0[4];
 } __rte_packed;
 
-/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
-struct hwrm_cfa_eem_qcaps_output {
+/* hwrm_cfa_vfr_free_output (size:128b/16B) */
+struct hwrm_cfa_vfr_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36088,87 +38335,7 @@ struct hwrm_cfa_eem_qcaps_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint32_t	flags;
-	/*
-	 * When set to 1, indicates the configuration will apply to TX flows
-	 * which are to be offloaded.
-	 * Note if this bit is set then the path_rx bit can't be set.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
-		UINT32_C(0x1)
-	/*
-	 * When set to 1, indicates the configuration will apply to RX flows
-	 * which are to be offloaded.
-	 * Note if this bit is set then the path_tx bit can't be set.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
-		UINT32_C(0x2)
-	/*
-	 * When set to 1, indicates the the FW supports the Centralized
-	 * Memory Model. The concept designates one entity for the
-	 * memory allocation while all others ‘subscribe’ to it.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
-		UINT32_C(0x4)
-	/*
-	 * When set to 1, indicates the the FW supports the Detached
-	 * Centralized Memory Model. The memory is allocated and managed
-	 * as a separate entity. All PFs and VFs will be granted direct
-	 * or semi-direct access to the allocated memory while none of
-	 * which can interfere with the management of the memory.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
-		UINT32_C(0x8)
-	uint32_t	unused_0;
-	uint32_t	supported;
-	/*
-	 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
-	 * If set to 0, EEM KEY0 table is not supported.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
-		UINT32_C(0x1)
-	/*
-	 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
-	 * If set to 0, EEM KEY1 table is not supported.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
-		UINT32_C(0x2)
-	/*
-	 * If set to 1, then EEM External Record table is supported.
-	 * If set to 0, EEM External Record table is not supported.
-	 * (This table includes action record, EFC pointers, encap pointers)
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
-		UINT32_C(0x4)
-	/*
-	 * If set to 1, then EEM External Flow Counters table is supported.
-	 * If set to 0, EEM External Flow Counters table is not supported.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
-		UINT32_C(0x8)
-	/*
-	 * If set to 1, then FID table used for implicit flow flush is supported.
-	 * If set to 0, then FID table used for implicit flow flush is not supported.
-	 */
-	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
-		UINT32_C(0x10)
-	/*
-	 * The maximum number of entries supported by EEM. When configuring the host memory
-	 * the number of numbers of entries that can supported are -
-	 *      32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
-	 * Any value that are not these values, the FW will round down to the closest support
-	 * number of entries.
-	 */
-	uint32_t	max_entries_supported;
-	/* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
-	uint16_t	key_entry_size;
-	/* The entry size in bytes of each entry in the EEM RECORD tables. */
-	uint16_t	record_entry_size;
-	/* The entry size in bytes of each entry in the EEM EFC tables. */
-	uint16_t	efc_entry_size;
-	/* The FID size in bytes of each entry in the EEM FID tables. */
-	uint16_t	fid_entry_size;
-	uint8_t	unused_1[7];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -36179,13 +38346,13 @@ struct hwrm_cfa_eem_qcaps_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/********************
- * hwrm_cfa_eem_cfg *
- ********************/
+/***************************************
+ * hwrm_cfa_redirect_query_tunnel_type *
+ ***************************************/
 
 
-/* hwrm_cfa_eem_cfg_input (size:384b/48B) */
-struct hwrm_cfa_eem_cfg_input {
+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
+struct hwrm_cfa_redirect_query_tunnel_type_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36214,65 +38381,66 @@ struct hwrm_cfa_eem_cfg_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	flags;
-	/*
-	 * When set to 1, indicates the configuration will apply to TX flows
-	 * which are to be offloaded.
-	 * Note if this bit is set then the path_rx bit can't be set.
-	 */
-	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
+	/* The source function id. */
+	uint16_t	src_fid;
+	uint8_t	unused_0[6];
+} __rte_packed;
+
+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
+struct hwrm_cfa_redirect_query_tunnel_type_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* Tunnel Mask. */
+	uint32_t	tunnel_mask;
+	/* Non-tunnel */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
 		UINT32_C(0x1)
-	/*
-	 * When set to 1, indicates the configuration will apply to RX flows
-	 * which are to be offloaded.
-	 * Note if this bit is set then the path_tx bit can't be set.
-	 */
-	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
+	/* Virtual eXtensible Local Area Network (VXLAN) */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
 		UINT32_C(0x2)
-	/* When set to 1, all offloaded flows will be sent to EEM. */
-	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
+	/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
 		UINT32_C(0x4)
-	/* When set to 1, secondary, 0 means primary. */
-	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
+	/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
 		UINT32_C(0x8)
-	/*
-	 * Group_id which used by Firmware to identify memory pools belonging
-	 * to certain group.
-	 */
-	uint16_t	group_id;
-	uint16_t	unused_0;
-	/*
-	 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
-	 * RECORD, EFC all have the same number of entries and all tables will be configured
-	 * using this value. Current minimum value is 32k. Current maximum value is 128M.
-	 */
-	uint32_t	num_entries;
-	uint32_t	unused_1;
-	/* Configured EEM with the given context if for KEY0 table. */
-	uint16_t	key0_ctx_id;
-	/* Configured EEM with the given context if for KEY1 table. */
-	uint16_t	key1_ctx_id;
-	/* Configured EEM with the given context if for RECORD table. */
-	uint16_t	record_ctx_id;
-	/* Configured EEM with the given context if for EFC table. */
-	uint16_t	efc_ctx_id;
-	/* Configured EEM with the given context if for EFC table. */
-	uint16_t	fid_ctx_id;
-	uint16_t	unused_2;
-	uint32_t	unused_3;
-} __rte_packed;
-
-/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
-struct hwrm_cfa_eem_cfg_output {
-	/* The specific error status for the command. */
-	uint16_t	error_code;
-	/* The HWRM command request type. */
-	uint16_t	req_type;
-	/* The sequence ID from the original command. */
-	uint16_t	seq_id;
-	/* The length of the response data in number of bytes. */
-	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/* IP in IP */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+		UINT32_C(0x10)
+	/* Generic Network Virtualization Encapsulation (Geneve) */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+		UINT32_C(0x20)
+	/* Multi-Protocol Label Switching (MPLS) */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+		UINT32_C(0x40)
+	/* Stateless Transport Tunnel (STT) */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
+		UINT32_C(0x80)
+	/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
+		UINT32_C(0x100)
+	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
+		UINT32_C(0x200)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
+		UINT32_C(0x400)
+	/* Any tunneled traffic */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
+		UINT32_C(0x800)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+		UINT32_C(0x1000)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+		UINT32_C(0x2000)
+	uint8_t	unused_0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -36283,13 +38451,13 @@ struct hwrm_cfa_eem_cfg_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*********************
- * hwrm_cfa_eem_qcfg *
- *********************/
+/*************************
+ * hwrm_cfa_ctx_mem_rgtr *
+ *************************/
 
 
-/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
-struct hwrm_cfa_eem_qcfg_input {
+/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_rgtr_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36318,16 +38486,44 @@ struct hwrm_cfa_eem_qcfg_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	flags;
-	/* When set to 1, indicates the configuration is the TX flow. */
-	#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX     UINT32_C(0x1)
-	/* When set to 1, indicates the configuration is the RX flow. */
-	#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX     UINT32_C(0x2)
+	uint16_t	flags;
+	/* Counter PBL indirect levels. */
+	uint8_t	page_level;
+	/* PBL pointer is physical start address. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+	/* PBL pointer points to PTE table. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+	/* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
+		HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
+	/* Page size. */
+	uint8_t	page_size;
+	/* 4KB page size. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K   UINT32_C(0x0)
+	/* 8KB page size. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K   UINT32_C(0x1)
+	/* 64KB page size. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K  UINT32_C(0x4)
+	/* 256KB page size. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+	/* 1MB page size. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M   UINT32_C(0x8)
+	/* 2MB page size. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M   UINT32_C(0x9)
+	/* 4MB page size. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M   UINT32_C(0xa)
+	/* 1GB page size. */
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)
+	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
+		HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
 	uint32_t	unused_0;
+	/* Pointer to the PBL, or PDL depending on number of levels */
+	uint64_t	page_dir;
 } __rte_packed;
 
-/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
-struct hwrm_cfa_eem_qcfg_output {
+/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_rgtr_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36336,29 +38532,12 @@ struct hwrm_cfa_eem_qcfg_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint32_t	flags;
-	/* When set to 1, indicates the configuration is the TX flow. */
-	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
-		UINT32_C(0x1)
-	/* When set to 1, indicates the configuration is the RX flow. */
-	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
-		UINT32_C(0x2)
-	/* When set to 1, all offloaded flows will be sent to EEM. */
-	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
-		UINT32_C(0x4)
-	/* The number of entries the FW has configured for EEM. */
-	uint32_t	num_entries;
-	/* Configured EEM with the given context if for KEY0 table. */
-	uint16_t	key0_ctx_id;
-	/* Configured EEM with the given context if for KEY1 table. */
-	uint16_t	key1_ctx_id;
-	/* Configured EEM with the given context if for RECORD table. */
-	uint16_t	record_ctx_id;
-	/* Configured EEM with the given context if for EFC table. */
-	uint16_t	efc_ctx_id;
-	/* Configured EEM with the given context if for EFC table. */
-	uint16_t	fid_ctx_id;
-	uint8_t	unused_2[5];
+	/*
+	 * Id/Handle to the recently register context memory. This handle is passed
+	 * to the CFA feature.
+	 */
+	uint16_t	ctx_id;
+	uint8_t	unused_0[5];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -36369,13 +38548,13 @@ struct hwrm_cfa_eem_qcfg_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*******************
- * hwrm_cfa_eem_op *
- *******************/
+/***************************
+ * hwrm_cfa_ctx_mem_unrgtr *
+ ***************************/
 
 
-/* hwrm_cfa_eem_op_input (size:192b/24B) */
-struct hwrm_cfa_eem_op_input {
+/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_unrgtr_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36404,49 +38583,16 @@ struct hwrm_cfa_eem_op_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	flags;
-	/*
-	 * When set to 1, indicates the host memory which is passed will be
-	 * used for the TX flow offload function specified in fid.
-	 * Note if this bit is set then the path_rx bit can't be set.
-	 */
-	#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX     UINT32_C(0x1)
-	/*
-	 * When set to 1, indicates the host memory which is passed will be
-	 * used for the RX flow offload function specified in fid.
-	 * Note if this bit is set then the path_tx bit can't be set.
-	 */
-	#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX     UINT32_C(0x2)
-	uint16_t	unused_0;
-	/* The number of EEM key table entries to be configured. */
-	uint16_t	op;
-	/* This value is reserved and should not be used. */
-	#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED    UINT32_C(0x0)
-	/*
-	 * To properly stop EEM and ensure there are no DMA's, the caller
-	 * must disable EEM for the given PF, using this call. This will
-	 * safely disable EEM and ensure that all DMA'ed to the
-	 * keys/records/efc have been completed.
-	 */
-	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
-	/*
-	 * Once the EEM host memory has been configured, EEM options have
-	 * been configured. Then the caller should enable EEM for the given
-	 * PF. Note once this call has been made, then the EEM mechanism
-	 * will be active and DMA's will occur as packets are processed.
-	 */
-	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE  UINT32_C(0x2)
 	/*
-	 * Clear EEM settings for the given PF so that the register values
-	 * are reset back to there initial state.
+	 * Id/Handle to the recently register context memory. This handle is passed
+	 * to the CFA feature.
 	 */
-	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
-	#define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
-		HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
+	uint16_t	ctx_id;
+	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_cfa_eem_op_output (size:128b/16B) */
-struct hwrm_cfa_eem_op_output {
+/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_unrgtr_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36466,13 +38612,13 @@ struct hwrm_cfa_eem_op_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/********************************
- * hwrm_cfa_adv_flow_mgnt_qcaps *
- ********************************/
+/*************************
+ * hwrm_cfa_ctx_mem_qctx *
+ *************************/
 
 
-/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
-struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_qctx_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36501,11 +38647,16 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	unused_0[4];
+	/*
+	 * Id/Handle to the recently register context memory. This handle is passed
+	 * to the CFA feature.
+	 */
+	uint16_t	ctx_id;
+	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
-struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_qctx_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36514,114 +38665,41 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint32_t	flags;
-	/*
-	 * Value of 1 to indicate firmware support 16-bit flow handle.
-	 * Value of 0 to indicate firmware not support 16-bit flow handle.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
-		UINT32_C(0x1)
-	/*
-	 * Value of 1 to indicate firmware support 64-bit flow handle.
-	 * Value of 0 to indicate firmware not support 64-bit flow handle.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
-		UINT32_C(0x2)
-	/*
-	 * Value of 1 to indicate firmware support flow batch delete operation through
-	 * HWRM_CFA_FLOW_FLUSH command.
-	 * Value of 0 to indicate that the firmware does not support flow batch delete
-	 * operation.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
-		UINT32_C(0x4)
-	/*
-	 * Value of 1 to indicate that the firmware support flow reset all operation through
-	 * HWRM_CFA_FLOW_FLUSH command.
-	 * Value of 0 indicates firmware does not support flow reset all operation.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
-		UINT32_C(0x8)
-	/*
-	 * Value of 1 to indicate that firmware supports use of FID as dest_id in
-	 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
-	 * Value of 0 indicates firmware does not support use of FID as dest_id.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
-		UINT32_C(0x10)
-	/*
-	 * Value of 1 to indicate that firmware supports TX EEM flows.
-	 * Value of 0 indicates firmware does not support TX EEM flows.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
-		UINT32_C(0x20)
-	/*
-	 * Value of 1 to indicate that firmware supports RX EEM flows.
-	 * Value of 0 indicates firmware does not support RX EEM flows.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
-		UINT32_C(0x40)
-	/*
-	 * Value of 1 to indicate that firmware supports the dynamic allocation of an
-	 * on-chip flow counter which can be used for EEM flows.
-	 * Value of 0 indicates firmware does not support the dynamic allocation of an
-	 * on-chip flow counter.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
-		UINT32_C(0x80)
-	/*
-	 * Value of 1 to indicate that firmware supports setting of
-	 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
-	 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
-		UINT32_C(0x100)
-	/*
-	 * Value of 1 to indicate that firmware supports untagged matching
-	 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
-	 * indicates firmware does not support untagged matching.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
-		UINT32_C(0x200)
-	/*
-	 * Value of 1 to indicate that firmware supports XDP filter. Value
-	 * of 0 indicates firmware does not support XDP filter.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
-		UINT32_C(0x400)
-	/*
-	 * Value of 1 to indicate that the firmware support L2 header source
-	 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
-	 * Value of 0 indicates firmware does not support L2 header source
-	 * fields matching.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
-		UINT32_C(0x800)
-	/*
-	 * If set to 1, firmware is capable of supporting ARP ethertype as
-	 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
-	 * RX direction. By default, this flag should be 0 for older version
-	 * of firmware.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
-		UINT32_C(0x1000)
-	/*
-	 * Value of 1 to indicate that firmware supports setting of
-	 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
-	 * command. Value of 0 indicates firmware does not support
-	 * rfs_ring_tbl_idx in dst_id field.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
-		UINT32_C(0x2000)
-	/*
-	 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
-	 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
-	 * direction. By default, this flag should be 0 for older version
-	 * of firmware.
-	 */
-	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
-		UINT32_C(0x4000)
-	uint8_t	unused_0[3];
+	uint16_t	flags;
+	/* Counter PBL indirect levels. */
+	uint8_t	page_level;
+	/* PBL pointer is physical start address. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+	/* PBL pointer points to PTE table. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+	/* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
+		HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
+	/* Page size. */
+	uint8_t	page_size;
+	/* 4KB page size. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K   UINT32_C(0x0)
+	/* 8KB page size. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K   UINT32_C(0x1)
+	/* 64KB page size. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K  UINT32_C(0x4)
+	/* 256KB page size. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+	/* 1MB page size. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M   UINT32_C(0x8)
+	/* 2MB page size. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M   UINT32_C(0x9)
+	/* 4MB page size. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M   UINT32_C(0xa)
+	/* 1GB page size. */
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G   UINT32_C(0x12)
+	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
+		HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
+	uint8_t	unused_0[4];
+	/* Pointer to the PBL, or PDL depending on number of levels */
+	uint64_t	page_dir;
+	uint8_t	unused_1[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -36632,13 +38710,13 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/******************
- * hwrm_cfa_tflib *
- ******************/
+/**************************
+ * hwrm_cfa_ctx_mem_qcaps *
+ **************************/
 
 
-/* hwrm_cfa_tflib_input (size:1024b/128B) */
-struct hwrm_cfa_tflib_input {
+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36667,18 +38745,10 @@ struct hwrm_cfa_tflib_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* TFLIB message type. */
-	uint16_t	tf_type;
-	/* TFLIB message subtype. */
-	uint16_t	tf_subtype;
-	/* unused. */
-	uint8_t	unused0[4];
-	/* TFLIB request data. */
-	uint32_t	tf_req[26];
 } __rte_packed;
 
-/* hwrm_cfa_tflib_output (size:5632b/704B) */
-struct hwrm_cfa_tflib_output {
+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36687,16 +38757,9 @@ struct hwrm_cfa_tflib_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* TFLIB message type. */
-	uint16_t	tf_type;
-	/* TFLIB message subtype. */
-	uint16_t	tf_subtype;
-	/* TFLIB response code */
-	uint32_t	tf_resp_code;
-	/* TFLIB response data. */
-	uint32_t	tf_resp[170];
-	/* unused. */
-	uint8_t	unused1[7];
+	/* Indicates the maximum number of context memory which can be registered. */
+	uint16_t	max_entries;
+	uint8_t	unused_0[5];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -36707,13 +38770,13 @@ struct hwrm_cfa_tflib_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/***********
- * hwrm_tf *
- ***********/
+/**************************
+ * hwrm_cfa_counter_qcaps *
+ **************************/
 
 
-/* hwrm_tf_input (size:1024b/128B) */
-struct hwrm_tf_input {
+/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_counter_qcaps_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36742,18 +38805,10 @@ struct hwrm_tf_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* TF message type. */
-	uint16_t	type;
-	/* TF message subtype. */
-	uint16_t	subtype;
-	/* unused. */
-	uint8_t	unused0[4];
-	/* TF request data. */
-	uint32_t	req[26];
 } __rte_packed;
 
-/* hwrm_tf_output (size:5632b/704B) */
-struct hwrm_tf_output {
+/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
+struct hwrm_cfa_counter_qcaps_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36762,34 +38817,63 @@ struct hwrm_tf_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* TF message type. */
-	uint16_t	type;
-	/* TF message subtype. */
-	uint16_t	subtype;
-	/* TF response code */
-	uint32_t	resp_code;
-	/* TF response data. */
-	uint32_t	resp[170];
-	/* unused. */
-	uint8_t	unused1[7];
+	uint32_t	flags;
+	/* Enumeration denoting the supported CFA counter format. */
+	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
+		UINT32_C(0x1)
+	/* CFA counter types are not supported. */
+	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
+		UINT32_C(0x0)
+	/* 64-bit packet counters followed by 64-bit byte counters format. */
+	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
+		UINT32_C(0x1)
+	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
+		HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
+	uint32_t	unused_0;
+	/* Minimum guaranteed number of flow counters supported for this function, in RX direction. */
+	uint32_t	min_rx_fc;
+	/* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */
+	uint32_t	max_rx_fc;
+	/* Minimum guaranteed number of flow counters supported for this function, in TX direction. */
+	uint32_t	min_tx_fc;
+	/* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */
+	uint32_t	max_tx_fc;
+	/* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */
+	uint32_t	min_rx_efc;
+	/* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */
+	uint32_t	max_rx_efc;
+	/* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */
+	uint32_t	min_tx_efc;
+	/* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */
+	uint32_t	max_tx_efc;
+	/* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */
+	uint32_t	min_rx_mdc;
+	/* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */
+	uint32_t	max_rx_mdc;
+	/* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */
+	uint32_t	min_tx_mdc;
+	/* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */
+	uint32_t	max_tx_mdc;
+	/* Maximum guaranteed number of flow counters which can be used during flow alloc. */
+	uint32_t	max_flow_alloc_fc;
+	uint8_t	unused_1[3];
 	/*
-	 * This field is used in Output records to indicate that the
-	 * output is completely written to RAM. This field should be
-	 * read as '1' to indicate that the output has been
-	 * completely written.  When writing a command completion or
-	 * response to an internal processor, the order of writes has
-	 * to be such that this field is written last.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/***********************
- * hwrm_tf_version_get *
- ***********************/
+/************************
+ * hwrm_cfa_counter_cfg *
+ ************************/
 
 
-/* hwrm_tf_version_get_input (size:128b/16B) */
-struct hwrm_tf_version_get_input {
+/* hwrm_cfa_counter_cfg_input (size:256b/32B) */
+struct hwrm_cfa_counter_cfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36818,44 +38902,90 @@ struct hwrm_tf_version_get_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-} __rte_packed;
-
-/* hwrm_tf_version_get_output (size:128b/16B) */
-struct hwrm_tf_version_get_output {
-	/* The specific error status for the command. */
-	uint16_t	error_code;
-	/* The HWRM command request type. */
-	uint16_t	req_type;
-	/* The sequence ID from the original command. */
-	uint16_t	seq_id;
-	/* The length of the response data in number of bytes. */
+	uint16_t	flags;
+	/* Enumeration denoting the configuration mode. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
+		UINT32_C(0x1)
+	/* Disable the configuration mode. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
+		UINT32_C(0x0)
+	/* Enable the configuration mode. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
+		UINT32_C(0x1)
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
+		HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
+	/* Enumeration denoting the RX, TX type of the resource. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
+		UINT32_C(0x2)
+	/* Tx path. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
+		(UINT32_C(0x0) << 1)
+	/* Rx path. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
+		(UINT32_C(0x1) << 1)
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
+	/* Enumeration denoting the data transfer mode. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
+		UINT32_C(0xc)
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT       2
+	/* Push mode. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
+		(UINT32_C(0x0) << 2)
+	/* Pull mode. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
+		(UINT32_C(0x1) << 2)
+	/* Pull on async update. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
+		(UINT32_C(0x2) << 2)
+	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
+		HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
+	uint16_t	counter_type;
+	/* Flow counters. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC  UINT32_C(0x0)
+	/* Extended flow counters. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
+	/* Meter drop counters. */
+	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
+	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
+		HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
+	/* Ctx memory handle to be used for the counter. */
+	uint16_t	ctx_id;
+	/* Counter update cadence hint (only in Push mode). */
+	uint16_t	update_tmr_ms;
+	/* Total number of entries. */
+	uint32_t	num_entries;
+	uint32_t	unused_0;
+} __rte_packed;
+
+/* hwrm_cfa_counter_cfg_output (size:128b/16B) */
+struct hwrm_cfa_counter_cfg_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Version Major number. */
-	uint8_t	major;
-	/* Version Minor number. */
-	uint8_t	minor;
-	/* Version Update number. */
-	uint8_t	update;
-	/* unused. */
-	uint8_t	unused0[4];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field is
-	 * written last.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/************************
- * hwrm_tf_session_open *
- ************************/
+/***************************
+ * hwrm_cfa_counter_qstats *
+ ***************************/
 
 
-/* hwrm_tf_session_open_input (size:640b/80B) */
-struct hwrm_tf_session_open_input {
+/* hwrm_cfa_counter_qstats_input (size:320b/40B) */
+struct hwrm_cfa_counter_qstats_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36884,12 +39014,27 @@ struct hwrm_tf_session_open_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Name of the session. */
-	uint8_t	session_name[64];
+	uint16_t	flags;
+	/* Enumeration denoting the RX, TX type of the resource. */
+	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH     UINT32_C(0x1)
+	/* Tx path. */
+	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)
+	/* Rx path. */
+	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)
+	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
+		HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
+	uint16_t	counter_type;
+	uint16_t	input_flow_ctx_id;
+	uint16_t	num_entries;
+	uint16_t	delta_time_ms;
+	uint16_t	meter_instance_id;
+	uint16_t	mdc_ctx_id;
+	uint8_t	unused_0[2];
+	uint64_t	expected_count;
 } __rte_packed;
 
-/* hwrm_tf_session_open_output (size:192b/24B) */
-struct hwrm_tf_session_open_output {
+/* hwrm_cfa_counter_qstats_output (size:128b/16B) */
+struct hwrm_cfa_counter_qstats_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36898,38 +39043,24 @@ struct hwrm_tf_session_open_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/*
-	 * Unique session identifier for the session created by the
-	 * firmware.
-	 */
-	uint32_t	fw_session_id;
-	/*
-	 * Unique session client identifier for the first client on
-	 * the newly created session.
-	 */
-	uint32_t	fw_session_client_id;
-	/* unused. */
-	uint32_t	unused0;
-	/* unused. */
-	uint8_t	unused1[3];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field is
-	 * written last.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/**************************
- * hwrm_tf_session_attach *
- **************************/
+/**********************
+ * hwrm_cfa_eem_qcaps *
+ **********************/
 
 
-/* hwrm_tf_session_attach_input (size:704b/88B) */
-struct hwrm_tf_session_attach_input {
+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcaps_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -36958,25 +39089,29 @@ struct hwrm_tf_session_attach_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	uint32_t	flags;
 	/*
-	 * Unique session identifier for the session that the attach
-	 * request want to attach to. This value originates from the
-	 * shared session memory that the attach request opened by
-	 * way of the 'attach name' that was passed in to the core
-	 * attach API.
-	 * The fw_session_id of the attach session includes PCIe bus
-	 * info to distinguish the PF and session info to identify
-	 * the associated TruFlow session.
+	 * When set to 1, indicates the configuration will apply to TX flows
+	 * which are to be offloaded.
+	 * Note if this bit is set then the path_rx bit can't be set.
 	 */
-	uint32_t	attach_fw_session_id;
-	/* unused. */
-	uint32_t	unused0;
-	/* Name of the session it self. */
-	uint8_t	session_name[64];
+	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
+		UINT32_C(0x1)
+	/*
+	 * When set to 1, indicates the configuration will apply to RX flows
+	 * which are to be offloaded.
+	 * Note if this bit is set then the path_tx bit can't be set.
+	 */
+	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
+		UINT32_C(0x2)
+	/* When set to 1, all offloaded flows will be sent to EEM. */
+	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
+		UINT32_C(0x4)
+	uint32_t	unused_0;
 } __rte_packed;
 
-/* hwrm_tf_session_attach_output (size:128b/16B) */
-struct hwrm_tf_session_attach_output {
+/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
+struct hwrm_cfa_eem_qcaps_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -36985,34 +39120,104 @@ struct hwrm_tf_session_attach_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	uint32_t	flags;
 	/*
-	 * Unique session identifier for the session created by the
-	 * firmware. It includes PCIe bus info to distinguish the PF
-	 * and session info to identify the associated TruFlow
-	 * session. This fw_session_id is unique to the attach
-	 * request.
+	 * When set to 1, indicates the configuration will apply to TX flows
+	 * which are to be offloaded.
+	 * Note if this bit is set then the path_rx bit can't be set.
 	 */
-	uint32_t	fw_session_id;
-	/* unused. */
-	uint8_t	unused0[3];
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
+		UINT32_C(0x1)
+	/*
+	 * When set to 1, indicates the configuration will apply to RX flows
+	 * which are to be offloaded.
+	 * Note if this bit is set then the path_tx bit can't be set.
+	 */
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
+		UINT32_C(0x2)
+	/*
+	 * When set to 1, indicates the the FW supports the Centralized
+	 * Memory Model. The concept designates one entity for the
+	 * memory allocation while all others ‘subscribe’ to it.
+	 */
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+		UINT32_C(0x4)
+	/*
+	 * When set to 1, indicates the the FW supports the Detached
+	 * Centralized Memory Model. The memory is allocated and managed
+	 * as a separate entity. All PFs and VFs will be granted direct
+	 * or semi-direct access to the allocated memory while none of
+	 * which can interfere with the management of the memory.
+	 */
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+		UINT32_C(0x8)
+	uint32_t	unused_0;
+	uint32_t	supported;
+	/*
+	 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
+	 * If set to 0, EEM KEY0 table is not supported.
+	 */
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
+		UINT32_C(0x1)
+	/*
+	 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
+	 * If set to 0, EEM KEY1 table is not supported.
+	 */
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
+		UINT32_C(0x2)
+	/*
+	 * If set to 1, then EEM External Record table is supported.
+	 * If set to 0, EEM External Record table is not supported.
+	 * (This table includes action record, EFC pointers, encap pointers)
+	 */
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
+		UINT32_C(0x4)
+	/*
+	 * If set to 1, then EEM External Flow Counters table is supported.
+	 * If set to 0, EEM External Flow Counters table is not supported.
+	 */
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
+		UINT32_C(0x8)
+	/*
+	 * If set to 1, then FID table used for implicit flow flush is supported.
+	 * If set to 0, then FID table used for implicit flow flush is not supported.
+	 */
+	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
+		UINT32_C(0x10)
+	/*
+	 * The maximum number of entries supported by EEM. When configuring the host memory
+	 * the number of numbers of entries that can supported are -
+	 *      32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
+	 * Any value that are not these values, the FW will round down to the closest support
+	 * number of entries.
+	 */
+	uint32_t	max_entries_supported;
+	/* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
+	uint16_t	key_entry_size;
+	/* The entry size in bytes of each entry in the EEM RECORD tables. */
+	uint16_t	record_entry_size;
+	/* The entry size in bytes of each entry in the EEM EFC tables. */
+	uint16_t	efc_entry_size;
+	/* The FID size in bytes of each entry in the EEM FID tables. */
+	uint16_t	fid_entry_size;
+	uint8_t	unused_1[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field is
-	 * written last.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/****************************
- * hwrm_tf_session_register *
- ****************************/
+/********************
+ * hwrm_cfa_eem_cfg *
+ ********************/
 
 
-/* hwrm_tf_session_register_input (size:704b/88B) */
-struct hwrm_tf_session_register_input {
+/* hwrm_cfa_eem_cfg_input (size:384b/48B) */
+struct hwrm_cfa_eem_cfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37041,23 +39246,56 @@ struct hwrm_tf_session_register_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	uint32_t	flags;
 	/*
-	 * Unique session identifier for the session that the
-	 * register request want to create a new client on. This
-	 * value originates from the first open request.
-	 * The fw_session_id of the attach session includes PCIe bus
-	 * info to distinguish the PF and session info to identify
-	 * the associated TruFlow session.
+	 * When set to 1, indicates the configuration will apply to TX flows
+	 * which are to be offloaded.
+	 * Note if this bit is set then the path_rx bit can't be set.
 	 */
-	uint32_t	fw_session_id;
-	/* unused. */
-	uint32_t	unused0;
-	/* Name of the session client. */
-	uint8_t	session_client_name[64];
+	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
+		UINT32_C(0x1)
+	/*
+	 * When set to 1, indicates the configuration will apply to RX flows
+	 * which are to be offloaded.
+	 * Note if this bit is set then the path_tx bit can't be set.
+	 */
+	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
+		UINT32_C(0x2)
+	/* When set to 1, all offloaded flows will be sent to EEM. */
+	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
+		UINT32_C(0x4)
+	/* When set to 1, secondary, 0 means primary. */
+	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
+		UINT32_C(0x8)
+	/*
+	 * Group_id which used by Firmware to identify memory pools belonging
+	 * to certain group.
+	 */
+	uint16_t	group_id;
+	uint16_t	unused_0;
+	/*
+	 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
+	 * RECORD, EFC all have the same number of entries and all tables will be configured
+	 * using this value. Current minimum value is 32k. Current maximum value is 128M.
+	 */
+	uint32_t	num_entries;
+	uint32_t	unused_1;
+	/* Configured EEM with the given context if for KEY0 table. */
+	uint16_t	key0_ctx_id;
+	/* Configured EEM with the given context if for KEY1 table. */
+	uint16_t	key1_ctx_id;
+	/* Configured EEM with the given context if for RECORD table. */
+	uint16_t	record_ctx_id;
+	/* Configured EEM with the given context if for EFC table. */
+	uint16_t	efc_ctx_id;
+	/* Configured EEM with the given context if for EFC table. */
+	uint16_t	fid_ctx_id;
+	uint16_t	unused_2;
+	uint32_t	unused_3;
 } __rte_packed;
 
-/* hwrm_tf_session_register_output (size:128b/16B) */
-struct hwrm_tf_session_register_output {
+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
+struct hwrm_cfa_eem_cfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37066,32 +39304,24 @@ struct hwrm_tf_session_register_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/*
-	 * Unique session client identifier for the session created
-	 * by the firmware. It includes the session the client it
-	 * attached to and session client info.
-	 */
-	uint32_t	fw_session_client_id;
-	/* unused. */
-	uint8_t	unused0[3];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field is
-	 * written last.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/******************************
- * hwrm_tf_session_unregister *
- ******************************/
+/*********************
+ * hwrm_cfa_eem_qcfg *
+ *********************/
 
 
-/* hwrm_tf_session_unregister_input (size:192b/24B) */
-struct hwrm_tf_session_unregister_input {
+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37120,20 +39350,16 @@ struct hwrm_tf_session_unregister_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/*
-	 * Unique session identifier for the session that the
-	 * unregister request want to close a session client on.
-	 */
-	uint32_t	fw_session_id;
-	/*
-	 * Unique session client identifier for the session that the
-	 * unregister request want to close.
-	 */
-	uint32_t	fw_session_client_id;
+	uint32_t	flags;
+	/* When set to 1, indicates the configuration is the TX flow. */
+	#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX     UINT32_C(0x1)
+	/* When set to 1, indicates the configuration is the RX flow. */
+	#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX     UINT32_C(0x2)
+	uint32_t	unused_0;
 } __rte_packed;
 
-/* hwrm_tf_session_unregister_output (size:128b/16B) */
-struct hwrm_tf_session_unregister_output {
+/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
+struct hwrm_cfa_eem_qcfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37142,26 +39368,46 @@ struct hwrm_tf_session_unregister_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* unused. */
-	uint8_t	unused0[7];
+	uint32_t	flags;
+	/* When set to 1, indicates the configuration is the TX flow. */
+	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
+		UINT32_C(0x1)
+	/* When set to 1, indicates the configuration is the RX flow. */
+	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
+		UINT32_C(0x2)
+	/* When set to 1, all offloaded flows will be sent to EEM. */
+	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
+		UINT32_C(0x4)
+	/* The number of entries the FW has configured for EEM. */
+	uint32_t	num_entries;
+	/* Configured EEM with the given context if for KEY0 table. */
+	uint16_t	key0_ctx_id;
+	/* Configured EEM with the given context if for KEY1 table. */
+	uint16_t	key1_ctx_id;
+	/* Configured EEM with the given context if for RECORD table. */
+	uint16_t	record_ctx_id;
+	/* Configured EEM with the given context if for EFC table. */
+	uint16_t	efc_ctx_id;
+	/* Configured EEM with the given context if for EFC table. */
+	uint16_t	fid_ctx_id;
+	uint8_t	unused_2[5];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field is
-	 * written last.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/*************************
- * hwrm_tf_session_close *
- *************************/
+/*******************
+ * hwrm_cfa_eem_op *
+ *******************/
 
 
-/* hwrm_tf_session_close_input (size:192b/24B) */
-struct hwrm_tf_session_close_input {
+/* hwrm_cfa_eem_op_input (size:192b/24B) */
+struct hwrm_cfa_eem_op_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37190,14 +39436,49 @@ struct hwrm_tf_session_close_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* unused. */
-	uint8_t	unused0[4];
+	uint32_t	flags;
+	/*
+	 * When set to 1, indicates the host memory which is passed will be
+	 * used for the TX flow offload function specified in fid.
+	 * Note if this bit is set then the path_rx bit can't be set.
+	 */
+	#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX     UINT32_C(0x1)
+	/*
+	 * When set to 1, indicates the host memory which is passed will be
+	 * used for the RX flow offload function specified in fid.
+	 * Note if this bit is set then the path_tx bit can't be set.
+	 */
+	#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX     UINT32_C(0x2)
+	uint16_t	unused_0;
+	/* The number of EEM key table entries to be configured. */
+	uint16_t	op;
+	/* This value is reserved and should not be used. */
+	#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED    UINT32_C(0x0)
+	/*
+	 * To properly stop EEM and ensure there are no DMA's, the caller
+	 * must disable EEM for the given PF, using this call. This will
+	 * safely disable EEM and ensure that all DMA'ed to the
+	 * keys/records/efc have been completed.
+	 */
+	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
+	/*
+	 * Once the EEM host memory has been configured, EEM options have
+	 * been configured. Then the caller should enable EEM for the given
+	 * PF. Note once this call has been made, then the EEM mechanism
+	 * will be active and DMA's will occur as packets are processed.
+	 */
+	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE  UINT32_C(0x2)
+	/*
+	 * Clear EEM settings for the given PF so that the register values
+	 * are reset back to there initial state.
+	 */
+	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
+	#define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
+		HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
 } __rte_packed;
 
-/* hwrm_tf_session_close_output (size:128b/16B) */
-struct hwrm_tf_session_close_output {
+/* hwrm_cfa_eem_op_output (size:128b/16B) */
+struct hwrm_cfa_eem_op_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37206,26 +39487,24 @@ struct hwrm_tf_session_close_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* unused. */
-	uint8_t	unused0[7];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field
-	 * is written last.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/************************
- * hwrm_tf_session_qcfg *
- ************************/
+/********************************
+ * hwrm_cfa_adv_flow_mgnt_qcaps *
+ ********************************/
 
 
-/* hwrm_tf_session_qcfg_input (size:192b/24B) */
-struct hwrm_tf_session_qcfg_input {
+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37254,14 +39533,11 @@ struct hwrm_tf_session_qcfg_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* unused. */
-	uint8_t	unused0[4];
+	uint32_t	unused_0[4];
 } __rte_packed;
 
-/* hwrm_tf_session_qcfg_output (size:128b/16B) */
-struct hwrm_tf_session_qcfg_output {
+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37270,74 +39546,131 @@ struct hwrm_tf_session_qcfg_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* RX action control settings flags. */
-	uint8_t	rx_act_flags;
+	uint32_t	flags;
 	/*
-	 * A value of 1 in this field indicates that Global Flow ID
-	 * reporting into cfa_code and cfa_metadata is enabled.
+	 * Value of 1 to indicate firmware support 16-bit flow handle.
+	 * Value of 0 to indicate firmware not support 16-bit flow handle.
 	 */
-	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
 		UINT32_C(0x1)
 	/*
-	 * A value of 1 in this field indicates that both inner and outer
-	 * are stripped and inner tag is passed.
-	 * Enabled.
+	 * Value of 1 to indicate firmware support 64-bit flow handle.
+	 * Value of 0 to indicate firmware not support 64-bit flow handle.
 	 */
-	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
 		UINT32_C(0x2)
 	/*
-	 * A value of 1 in this field indicates that the re-use of
-	 * existing tunnel L2 header SMAC is enabled for
-	 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
+	 * Value of 1 to indicate firmware support flow batch delete operation through
+	 * HWRM_CFA_FLOW_FLUSH command.
+	 * Value of 0 to indicate that the firmware does not support flow batch delete
+	 * operation.
 	 */
-	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
 		UINT32_C(0x4)
-	/* TX Action control settings flags. */
-	uint8_t	tx_act_flags;
-	/* Disabled. */
-	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
-		UINT32_C(0x1)
 	/*
-	 * When set to 1 any GRE tunnels will include the
-	 * optional Key field.
+	 * Value of 1 to indicate that the firmware support flow reset all operation through
+	 * HWRM_CFA_FLOW_FLUSH command.
+	 * Value of 0 indicates firmware does not support flow reset all operation.
 	 */
-	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
-		UINT32_C(0x2)
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
+		UINT32_C(0x8)
 	/*
-	 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
-	 * field of the outer header is inherited from the inner header
-	 * (if present) or the fixed value as taken from the encap
-	 * record.
+	 * Value of 1 to indicate that firmware supports use of FID as dest_id in
+	 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
+	 * Value of 0 indicates firmware does not support use of FID as dest_id.
 	 */
-	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
-		UINT32_C(0x4)
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
+		UINT32_C(0x10)
 	/*
-	 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
-	 * field of the outer header is inherited from the inner header
-	 * (if present) or the fixed value as taken from the encap record.
+	 * Value of 1 to indicate that firmware supports TX EEM flows.
+	 * Value of 0 indicates firmware does not support TX EEM flows.
 	 */
-	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
-		UINT32_C(0x8)
-	/* unused. */
-	uint8_t	unused0[5];
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
+		UINT32_C(0x20)
+	/*
+	 * Value of 1 to indicate that firmware supports RX EEM flows.
+	 * Value of 0 indicates firmware does not support RX EEM flows.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
+		UINT32_C(0x40)
+	/*
+	 * Value of 1 to indicate that firmware supports the dynamic allocation of an
+	 * on-chip flow counter which can be used for EEM flows.
+	 * Value of 0 indicates firmware does not support the dynamic allocation of an
+	 * on-chip flow counter.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
+		UINT32_C(0x80)
+	/*
+	 * Value of 1 to indicate that firmware supports setting of
+	 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
+	 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
+		UINT32_C(0x100)
+	/*
+	 * Value of 1 to indicate that firmware supports untagged matching
+	 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
+	 * indicates firmware does not support untagged matching.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
+		UINT32_C(0x200)
+	/*
+	 * Value of 1 to indicate that firmware supports XDP filter. Value
+	 * of 0 indicates firmware does not support XDP filter.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
+		UINT32_C(0x400)
+	/*
+	 * Value of 1 to indicate that the firmware support L2 header source
+	 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
+	 * Value of 0 indicates firmware does not support L2 header source
+	 * fields matching.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
+		UINT32_C(0x800)
+	/*
+	 * If set to 1, firmware is capable of supporting ARP ethertype as
+	 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
+	 * RX direction. By default, this flag should be 0 for older version
+	 * of firmware.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
+		UINT32_C(0x1000)
+	/*
+	 * Value of 1 to indicate that firmware supports setting of
+	 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
+	 * command. Value of 0 indicates firmware does not support
+	 * rfs_ring_tbl_idx in dst_id field.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
+		UINT32_C(0x2000)
+	/*
+	 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
+	 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
+	 * direction. By default, this flag should be 0 for older version
+	 * of firmware.
+	 */
+	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
+		UINT32_C(0x4000)
+	uint8_t	unused_0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field
-	 * is written last.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/******************************
- * hwrm_tf_session_resc_qcaps *
- ******************************/
+/******************
+ * hwrm_cfa_tflib *
+ ******************/
 
 
-/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
-struct hwrm_tf_session_resc_qcaps_input {
+/* hwrm_cfa_tflib_input (size:1024b/128B) */
+struct hwrm_cfa_tflib_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37366,36 +39699,18 @@ struct hwrm_tf_session_resc_qcaps_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint16_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
-	/*
-	 * Defines the size of the provided qcaps_addr array
-	 * buffer. The size should be set to the Resource Manager
-	 * provided max number of qcaps entries which is device
-	 * specific. Resource Manager gets the max size from HCAPI
-	 * RM.
-	 */
-	uint16_t	qcaps_size;
-	/*
-	 * This is the DMA address for the qcaps output data array
-	 * buffer. Array is of tf_rm_resc_req_entry type and is
-	 * device specific.
-	 */
-	uint64_t	qcaps_addr;
+	/* TFLIB message type. */
+	uint16_t	tf_type;
+	/* TFLIB message subtype. */
+	uint16_t	tf_subtype;
+	/* unused. */
+	uint8_t	unused0[4];
+	/* TFLIB request data. */
+	uint32_t	tf_req[26];
 } __rte_packed;
 
-/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
-struct hwrm_tf_session_resc_qcaps_output {
+/* hwrm_cfa_tflib_output (size:5632b/704B) */
+struct hwrm_cfa_tflib_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37404,55 +39719,33 @@ struct hwrm_tf_session_resc_qcaps_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Control flags. */
-	uint32_t	flags;
-	/* Session reservation strategy. */
-	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
-		UINT32_C(0x3)
-	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
-		0
-	/* Static partitioning. */
-	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
-		UINT32_C(0x0)
-	/* Strategy 1. */
-	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
-		UINT32_C(0x1)
-	/* Strategy 2. */
-	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
-		UINT32_C(0x2)
-	/* Strategy 3. */
-	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
-		UINT32_C(0x3)
-	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
-		HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
-	/*
-	 * Size of the returned qcaps_addr data array buffer. The
-	 * value cannot exceed the size defined by the input msg,
-	 * qcaps_size.
-	 */
-	uint16_t	size;
-	/* unused. */
-	uint16_t	unused0;
+	/* TFLIB message type. */
+	uint16_t	tf_type;
+	/* TFLIB message subtype. */
+	uint16_t	tf_subtype;
+	/* TFLIB response code */
+	uint32_t	tf_resp_code;
+	/* TFLIB response data. */
+	uint32_t	tf_resp[170];
 	/* unused. */
 	uint8_t	unused1[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field is
-	 * written last.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/******************************
- * hwrm_tf_session_resc_alloc *
- ******************************/
+/***********
+ * hwrm_tf *
+ ***********/
 
 
-/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
-struct hwrm_tf_session_resc_alloc_input {
+/* hwrm_tf_input (size:1024b/128B) */
+struct hwrm_tf_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37481,42 +39774,18 @@ struct hwrm_tf_session_resc_alloc_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint16_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
-	/*
-	 * Defines the array size of the provided req_addr and
-	 * resv_addr array buffers. Should be set to the number of
-	 * request entries.
-	 */
-	uint16_t	req_size;
-	/*
-	 * This is the DMA address for the request input data array
-	 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
-	 * array buffer is provided by the 'req_size' field in this
-	 * message.
-	 */
-	uint64_t	req_addr;
-	/*
-	 * This is the DMA address for the resc output data array
-	 * buffer. Array is of tf_rm_resc_entry type. Size of the array
-	 * buffer is provided by the 'req_size' field in this
-	 * message.
-	 */
-	uint64_t	resc_addr;
+	/* TF message type. */
+	uint16_t	type;
+	/* TF message subtype. */
+	uint16_t	subtype;
+	/* unused. */
+	uint8_t	unused0[4];
+	/* TF request data. */
+	uint32_t	req[26];
 } __rte_packed;
 
-/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
-struct hwrm_tf_session_resc_alloc_output {
+/* hwrm_tf_output (size:5632b/704B) */
+struct hwrm_tf_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37525,33 +39794,34 @@ struct hwrm_tf_session_resc_alloc_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/*
-	 * Size of the returned tf_rm_resc_entry data array. The value
-	 * cannot exceed the req_size defined by the input msg. The data
-	 * array is returned using the resv_addr specified DMA
-	 * address also provided by the input msg.
-	 */
-	uint16_t	size;
+	/* TF message type. */
+	uint16_t	type;
+	/* TF message subtype. */
+	uint16_t	subtype;
+	/* TF response code */
+	uint32_t	resp_code;
+	/* TF response data. */
+	uint32_t	resp[170];
 	/* unused. */
-	uint8_t	unused0[5];
+	uint8_t	unused1[7];
 	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM. This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field is
-	 * written last.
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/*****************************
- * hwrm_tf_session_resc_free *
- *****************************/
+/***********************
+ * hwrm_tf_version_get *
+ ***********************/
 
 
-/* hwrm_tf_session_resc_free_input (size:256b/32B) */
-struct hwrm_tf_session_resc_free_input {
+/* hwrm_tf_version_get_input (size:128b/16B) */
+struct hwrm_tf_version_get_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37580,34 +39850,10 @@ struct hwrm_tf_session_resc_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint16_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
-	/*
-	 * Defines the size, in bytes, of the provided free_addr
-	 * buffer.
-	 */
-	uint16_t	free_size;
-	/*
-	 * This is the DMA address for the free input data array
-	 * buffer.  Array is of tf_rm_resc_entry type. Size of the
-	 * buffer is provided by the 'free_size' field of this
-	 * message.
-	 */
-	uint64_t	free_addr;
 } __rte_packed;
 
-/* hwrm_tf_session_resc_free_output (size:128b/16B) */
-struct hwrm_tf_session_resc_free_output {
+/* hwrm_tf_version_get_output (size:128b/16B) */
+struct hwrm_tf_version_get_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37616,8 +39862,14 @@ struct hwrm_tf_session_resc_free_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/* Version Major number. */
+	uint8_t	major;
+	/* Version Minor number. */
+	uint8_t	minor;
+	/* Version Update number. */
+	uint8_t	update;
 	/* unused. */
-	uint8_t	unused0[7];
+	uint8_t	unused0[4];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -37629,13 +39881,13 @@ struct hwrm_tf_session_resc_free_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/******************************
- * hwrm_tf_session_resc_flush *
- ******************************/
+/************************
+ * hwrm_tf_session_open *
+ ************************/
 
 
-/* hwrm_tf_session_resc_flush_input (size:256b/32B) */
-struct hwrm_tf_session_resc_flush_input {
+/* hwrm_tf_session_open_input (size:640b/80B) */
+struct hwrm_tf_session_open_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37664,34 +39916,12 @@ struct hwrm_tf_session_resc_flush_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint16_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
-	/*
-	 * Defines the size, in bytes, of the provided flush_addr
-	 * buffer.
-	 */
-	uint16_t	flush_size;
-	/*
-	 * This is the DMA address for the flush input data array
-	 * buffer.  Array of tf_rm_resc_entry type. Size of the
-	 * buffer is provided by the 'flush_size' field in this
-	 * message.
-	 */
-	uint64_t	flush_addr;
+	/* Name of the session. */
+	uint8_t	session_name[64];
 } __rte_packed;
 
-/* hwrm_tf_session_resc_flush_output (size:128b/16B) */
-struct hwrm_tf_session_resc_flush_output {
+/* hwrm_tf_session_open_output (size:192b/24B) */
+struct hwrm_tf_session_open_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37700,8 +39930,20 @@ struct hwrm_tf_session_resc_flush_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/*
+	 * Unique session identifier for the session created by the
+	 * firmware.
+	 */
+	uint32_t	fw_session_id;
+	/*
+	 * Unique session client identifier for the first client on
+	 * the newly created session.
+	 */
+	uint32_t	fw_session_client_id;
 	/* unused. */
-	uint8_t	unused0[7];
+	uint32_t	unused0;
+	/* unused. */
+	uint8_t	unused1[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
@@ -37713,35 +39955,13 @@ struct hwrm_tf_session_resc_flush_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/* TruFlow RM capability of a resource. */
-/* tf_rm_resc_req_entry (size:64b/8B) */
-struct tf_rm_resc_req_entry {
-	/* Type of the resource, defined globally in HCAPI RM. */
-	uint32_t	type;
-	/* Minimum value. */
-	uint16_t	min;
-	/* Maximum value. */
-	uint16_t	max;
-} __rte_packed;
-
-/* TruFlow RM reservation information. */
-/* tf_rm_resc_entry (size:64b/8B) */
-struct tf_rm_resc_entry {
-	/* Type of the resource, defined globally in HCAPI RM. */
-	uint32_t	type;
-	/* Start offset. */
-	uint16_t	start;
-	/* Number of resources. */
-	uint16_t	stride;
-} __rte_packed;
-
-/************************
- * hwrm_tf_tbl_type_get *
- ************************/
+/**************************
+ * hwrm_tf_session_attach *
+ **************************/
 
 
-/* hwrm_tf_tbl_type_get_input (size:256b/32B) */
-struct hwrm_tf_tbl_type_get_input {
+/* hwrm_tf_session_attach_input (size:704b/88B) */
+struct hwrm_tf_session_attach_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37770,31 +39990,25 @@ struct hwrm_tf_tbl_type_get_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint16_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
-	/* unused. */
-	uint8_t	unused0[2];
 	/*
-	 * Type of the resource, defined globally in the
-	 * hwrm_tf_resc_type enum.
+	 * Unique session identifier for the session that the attach
+	 * request want to attach to. This value originates from the
+	 * shared session memory that the attach request opened by
+	 * way of the 'attach name' that was passed in to the core
+	 * attach API.
+	 * The fw_session_id of the attach session includes PCIe bus
+	 * info to distinguish the PF and session info to identify
+	 * the associated TruFlow session.
 	 */
-	uint32_t	type;
-	/* Index of the type to retrieve. */
-	uint32_t	index;
+	uint32_t	attach_fw_session_id;
+	/* unused. */
+	uint32_t	unused0;
+	/* Name of the session it self. */
+	uint8_t	session_name[64];
 } __rte_packed;
 
-/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
-struct hwrm_tf_tbl_type_get_output {
+/* hwrm_tf_session_attach_output (size:128b/16B) */
+struct hwrm_tf_session_attach_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37803,34 +40017,34 @@ struct hwrm_tf_tbl_type_get_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Response code. */
-	uint32_t	resp_code;
-	/* Response size. */
-	uint16_t	size;
-	/* unused */
-	uint16_t	unused0;
-	/* Response data. */
-	uint8_t	data[128];
-	/* unused */
-	uint8_t	unused1[7];
+	/*
+	 * Unique session identifier for the session created by the
+	 * firmware. It includes PCIe bus info to distinguish the PF
+	 * and session info to identify the associated TruFlow
+	 * session. This fw_session_id is unique to the attach
+	 * request.
+	 */
+	uint32_t	fw_session_id;
+	/* unused. */
+	uint8_t	unused0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
 	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field
-	 * is written last.
+	 * processor, the order of writes has to be such that this field is
+	 * written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/************************
- * hwrm_tf_tbl_type_set *
- ************************/
+/****************************
+ * hwrm_tf_session_register *
+ ****************************/
 
 
-/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
-struct hwrm_tf_tbl_type_set_input {
+/* hwrm_tf_session_register_input (size:704b/88B) */
+struct hwrm_tf_session_register_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37859,37 +40073,23 @@ struct hwrm_tf_tbl_type_set_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	/*
+	 * Unique session identifier for the session that the
+	 * register request want to create a new client on. This
+	 * value originates from the first open request.
+	 * The fw_session_id of the attach session includes PCIe bus
+	 * info to distinguish the PF and session info to identify
+	 * the associated TruFlow session.
+	 */
 	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint16_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
 	/* unused. */
-	uint8_t	unused0[2];
-	/*
-	 * Type of the resource, defined globally in the
-	 * hwrm_tf_resc_type enum.
-	 */
-	uint32_t	type;
-	/* Index of the type to retrieve. */
-	uint32_t	index;
-	/* Size of the data to set. */
-	uint16_t	size;
-	/* unused */
-	uint8_t	unused1[6];
-	/* Data to be set. */
-	uint8_t	data[88];
+	uint32_t	unused0;
+	/* Name of the session client. */
+	uint8_t	session_client_name[64];
 } __rte_packed;
 
-/* hwrm_tf_tbl_type_set_output (size:128b/16B) */
-struct hwrm_tf_tbl_type_set_output {
+/* hwrm_tf_session_register_output (size:128b/16B) */
+struct hwrm_tf_session_register_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37898,26 +40098,32 @@ struct hwrm_tf_tbl_type_set_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/*
+	 * Unique session client identifier for the session created
+	 * by the firmware. It includes the session the client it
+	 * attached to and session client info.
+	 */
+	uint32_t	fw_session_client_id;
 	/* unused. */
-	uint8_t	unused0[7];
+	uint8_t	unused0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
 	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field
-	 * is written last.
+	 * processor, the order of writes has to be such that this field is
+	 * written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/*************************
- * hwrm_tf_ctxt_mem_rgtr *
- *************************/
+/******************************
+ * hwrm_tf_session_unregister *
+ ******************************/
 
 
-/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
-struct hwrm_tf_ctxt_mem_rgtr_input {
+/* hwrm_tf_session_unregister_input (size:192b/24B) */
+struct hwrm_tf_session_unregister_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -37946,49 +40152,20 @@ struct hwrm_tf_ctxt_mem_rgtr_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Control flags. */
-	uint16_t	flags;
-	/* Counter PBL indirect levels. */
-	uint8_t	page_level;
-	/* PBL pointer is physical start address. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
-	/* PBL pointer points to PTE table. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
 	/*
-	 * PBL pointer points to PDE table with each entry pointing
-	 * to PTE tables.
+	 * Unique session identifier for the session that the
+	 * unregister request want to close a session client on.
 	 */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
-		HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
-	/* Page size. */
-	uint8_t	page_size;
-	/* 4KB page size. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K   UINT32_C(0x0)
-	/* 8KB page size. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K   UINT32_C(0x1)
-	/* 64KB page size. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K  UINT32_C(0x4)
-	/* 256KB page size. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
-	/* 1MB page size. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M   UINT32_C(0x8)
-	/* 2MB page size. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M   UINT32_C(0x9)
-	/* 4MB page size. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M   UINT32_C(0xa)
-	/* 1GB page size. */
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)
-	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
-		HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
-	/* unused. */
-	uint32_t	unused0;
-	/* Pointer to the PBL, or PDL depending on number of levels */
-	uint64_t	page_dir;
+	uint32_t	fw_session_id;
+	/*
+	 * Unique session client identifier for the session that the
+	 * unregister request want to close.
+	 */
+	uint32_t	fw_session_client_id;
 } __rte_packed;
 
-/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
-struct hwrm_tf_ctxt_mem_rgtr_output {
+/* hwrm_tf_session_unregister_output (size:128b/16B) */
+struct hwrm_tf_session_unregister_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -37997,31 +40174,26 @@ struct hwrm_tf_ctxt_mem_rgtr_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/*
-	 * Id/Handle to the recently register context memory. This
-	 * handle is passed to the TF session.
-	 */
-	uint16_t	ctx_id;
 	/* unused. */
-	uint8_t	unused0[5];
+	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the
-	 * output is completely written to RAM. This field should be
-	 * read as '1' to indicate that the output has been
-	 * completely written.  When writing a command completion or
-	 * response to an internal processor, the order of writes has
-	 * to be such that this field is written last.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field is
+	 * written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/***************************
- * hwrm_tf_ctxt_mem_unrgtr *
- ***************************/
+/*************************
+ * hwrm_tf_session_close *
+ *************************/
 
 
-/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
-struct hwrm_tf_ctxt_mem_unrgtr_input {
+/* hwrm_tf_session_close_input (size:192b/24B) */
+struct hwrm_tf_session_close_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38050,17 +40222,14 @@ struct hwrm_tf_ctxt_mem_unrgtr_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/*
-	 * Id/Handle to the recently register context memory. This
-	 * handle is passed to the TF session.
-	 */
-	uint16_t	ctx_id;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
 	/* unused. */
-	uint8_t	unused0[6];
+	uint8_t	unused0[4];
 } __rte_packed;
 
-/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
-struct hwrm_tf_ctxt_mem_unrgtr_output {
+/* hwrm_tf_session_close_output (size:128b/16B) */
+struct hwrm_tf_session_close_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38072,23 +40241,23 @@ struct hwrm_tf_ctxt_mem_unrgtr_output {
 	/* unused. */
 	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the
-	 * output is completely written to RAM. This field should be
-	 * read as '1' to indicate that the output has been
-	 * completely written.  When writing a command completion or
-	 * response to an internal processor, the order of writes has
-	 * to be such that this field is written last.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
 /************************
- * hwrm_tf_ext_em_qcaps *
+ * hwrm_tf_session_qcfg *
  ************************/
 
 
-/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
-struct hwrm_tf_ext_em_qcaps_input {
+/* hwrm_tf_session_qcfg_input (size:192b/24B) */
+struct hwrm_tf_session_qcfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38117,28 +40286,14 @@ struct hwrm_tf_ext_em_qcaps_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Control flags. */
-	uint32_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
-		UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
-		UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
-		UINT32_C(0x1)
-	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
-	/* When set to 1, all offloaded flows will be sent to EXT EM. */
-	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
-		UINT32_C(0x2)
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
 	/* unused. */
-	uint32_t	unused0;
+	uint8_t	unused0[4];
 } __rte_packed;
 
-/* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */
-struct hwrm_tf_ext_em_qcaps_output {
+/* hwrm_tf_session_qcfg_output (size:128b/16B) */
+struct hwrm_tf_session_qcfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38147,109 +40302,74 @@ struct hwrm_tf_ext_em_qcaps_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint32_t	flags;
+	/* RX action control settings flags. */
+	uint8_t	rx_act_flags;
 	/*
-	 * When set to 1, indicates the the FW supports the Centralized
-	 * Memory Model. The concept designates one entity for the
-	 * memory allocation while all others ‘subscribe’ to it.
+	 * A value of 1 in this field indicates that Global Flow ID
+	 * reporting into cfa_code and cfa_metadata is enabled.
 	 */
-	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
 		UINT32_C(0x1)
 	/*
-	 * When set to 1, indicates the the FW supports the Detached
-	 * Centralized Memory Model. The memory is allocated and managed
-	 * as a separate entity. All PFs and VFs will be granted direct
-	 * or semi-direct access to the allocated memory while none of
-	 * which can interfere with the management of the memory.
+	 * A value of 1 in this field indicates that both inner and outer
+	 * are stripped and inner tag is passed.
+	 * Enabled.
 	 */
-	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
 		UINT32_C(0x2)
-	/* unused. */
-	uint32_t	unused0;
-	/* Support flags. */
-	uint32_t	supported;
 	/*
-	 * If set to 1, then EXT EM KEY0 table is supported using
-	 * crc32 hash.
-	 * If set to 0, EXT EM KEY0 table is not supported.
+	 * A value of 1 in this field indicates that the re-use of
+	 * existing tunnel L2 header SMAC is enabled for
+	 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
 	 */
-	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
+	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
+		UINT32_C(0x4)
+	/* TX Action control settings flags. */
+	uint8_t	tx_act_flags;
+	/* Disabled. */
+	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
 		UINT32_C(0x1)
 	/*
-	 * If set to 1, then EXT EM KEY1 table is supported using
-	 * lookup3 hash.
-	 * If set to 0, EXT EM KEY1 table is not supported.
+	 * When set to 1 any GRE tunnels will include the
+	 * optional Key field.
 	 */
-	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
+	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
 		UINT32_C(0x2)
 	/*
-	 * If set to 1, then EXT EM External Record table is supported.
-	 * If set to 0, EXT EM External Record table is not
-	 * supported.  (This table includes action record, EFC
-	 * pointers, encap pointers)
+	 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
+	 * field of the outer header is inherited from the inner header
+	 * (if present) or the fixed value as taken from the encap
+	 * record.
 	 */
-	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
+	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
 		UINT32_C(0x4)
 	/*
-	 * If set to 1, then EXT EM External Flow Counters table is
-	 * supported.
-	 * If set to 0, EXT EM External Flow Counters table is not
-	 * supported.
+	 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
+	 * field of the outer header is inherited from the inner header
+	 * (if present) or the fixed value as taken from the encap record.
 	 */
-	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
+	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
 		UINT32_C(0x8)
-	/*
-	 * If set to 1, then FID table used for implicit flow flush
-	 * is supported.
-	 * If set to 0, then FID table used for implicit flow flush
-	 * is not supported.
-	 */
-	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
-		UINT32_C(0x10)
-	/*
-	 * The maximum number of entries supported by EXT EM. When
-	 * configuring the host memory the number of numbers of
-	 * entries that can supported are -
-	 *      32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
-	 *      128M entries.
-	 * Any value that are not these values, the FW will round
-	 * down to the closest support number of entries.
-	 */
-	uint32_t	max_entries_supported;
-	/*
-	 * The entry size in bytes of each entry in the EXT EM
-	 * KEY0/KEY1 tables.
-	 */
-	uint16_t	key_entry_size;
-	/*
-	 * The entry size in bytes of each entry in the EXT EM RECORD
-	 * tables.
-	 */
-	uint16_t	record_entry_size;
-	/* The entry size in bytes of each entry in the EXT EM EFC tables. */
-	uint16_t	efc_entry_size;
-	/* The FID size in bytes of each entry in the EXT EM FID tables. */
-	uint16_t	fid_entry_size;
 	/* unused. */
-	uint8_t	unused1[7];
+	uint8_t	unused0[5];
 	/*
-	 * This field is used in Output records to indicate that the
-	 * output is completely written to RAM. This field should be
-	 * read as '1' to indicate that the output has been
-	 * completely written.  When writing a command completion or
-	 * response to an internal processor, the order of writes has
-	 * to be such that this field is written last.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/*********************
- * hwrm_tf_ext_em_op *
- *********************/
+/******************************
+ * hwrm_tf_session_resc_qcaps *
+ ******************************/
 
 
-/* hwrm_tf_ext_em_op_input (size:192b/24B) */
-struct hwrm_tf_ext_em_op_input {
+/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
+struct hwrm_tf_session_resc_qcaps_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38278,51 +40398,36 @@ struct hwrm_tf_ext_em_op_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
 	/* Control flags. */
 	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR     UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
-	/* unused. */
-	uint16_t	unused0;
-	/* The number of EXT EM key table entries to be configured. */
-	uint16_t	op;
-	/* This value is reserved and should not be used. */
-	#define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED       UINT32_C(0x0)
-	/*
-	 * To properly stop EXT EM and ensure there are no DMA's,
-	 * the caller must disable EXT EM for the given PF, using
-	 * this call. This will safely disable EXT EM and ensure
-	 * that all DMA'ed to the keys/records/efc have been
-	 * completed.
-	 */
-	#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
 	/*
-	 * Once the EXT EM host memory has been configured, EXT EM
-	 * options have been configured. Then the caller should
-	 * enable EXT EM for the given PF. Note once this call has
-	 * been made, then the EXT EM mechanism will be active and
-	 * DMA's will occur as packets are processed.
+	 * Defines the size of the provided qcaps_addr array
+	 * buffer. The size should be set to the Resource Manager
+	 * provided max number of qcaps entries which is device
+	 * specific. Resource Manager gets the max size from HCAPI
+	 * RM.
 	 */
-	#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE  UINT32_C(0x2)
+	uint16_t	qcaps_size;
 	/*
-	 * Clear EXT EM settings for the given PF so that the
-	 * register values are reset back to their initial state.
+	 * This is the DMA address for the qcaps output data array
+	 * buffer. Array is of tf_rm_resc_req_entry type and is
+	 * device specific.
 	 */
-	#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
-	#define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
-		HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
-	/* unused. */
-	uint16_t	unused1;
+	uint64_t	qcaps_addr;
 } __rte_packed;
 
-/* hwrm_tf_ext_em_op_output (size:128b/16B) */
-struct hwrm_tf_ext_em_op_output {
+/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
+struct hwrm_tf_session_resc_qcaps_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38331,26 +40436,55 @@ struct hwrm_tf_ext_em_op_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/* Control flags. */
+	uint32_t	flags;
+	/* Session reservation strategy. */
+	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
+		UINT32_C(0x3)
+	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
+		0
+	/* Static partitioning. */
+	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
+		UINT32_C(0x0)
+	/* Strategy 1. */
+	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
+		UINT32_C(0x1)
+	/* Strategy 2. */
+	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
+		UINT32_C(0x2)
+	/* Strategy 3. */
+	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
+		UINT32_C(0x3)
+	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
+		HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
+	/*
+	 * Size of the returned qcaps_addr data array buffer. The
+	 * value cannot exceed the size defined by the input msg,
+	 * qcaps_size.
+	 */
+	uint16_t	size;
 	/* unused. */
-	uint8_t	unused0[7];
+	uint16_t	unused0;
+	/* unused. */
+	uint8_t	unused1[7];
 	/*
-	 * This field is used in Output records to indicate that the
-	 * output is completely written to RAM. This field should be
-	 * read as '1' to indicate that the output has been
-	 * completely written.  When writing a command completion or
-	 * response to an internal processor, the order of writes has
-	 * to be such that this field is written last.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field is
+	 * written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/**********************
- * hwrm_tf_ext_em_cfg *
- **********************/
+/******************************
+ * hwrm_tf_session_resc_alloc *
+ ******************************/
 
 
-/* hwrm_tf_ext_em_cfg_input (size:384b/48B) */
-struct hwrm_tf_ext_em_cfg_input {
+/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
+struct hwrm_tf_session_resc_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38379,65 +40513,42 @@ struct hwrm_tf_ext_em_cfg_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
 	/* Control flags. */
-	uint32_t	flags;
+	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
-		UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR     UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
-		UINT32_C(0x0)
+	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
-		UINT32_C(0x1)
-	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
-	/* When set to 1, all offloaded flows will be sent to EXT EM. */
-	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
-		UINT32_C(0x2)
-	/* When set to 1, secondary, 0 means primary. */
-	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
-		UINT32_C(0x4)
+	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
 	/*
-	 * Group_id which used by Firmware to identify memory pools belonging
-	 * to certain group.
+	 * Defines the array size of the provided req_addr and
+	 * resv_addr array buffers. Should be set to the number of
+	 * request entries.
 	 */
-	uint16_t	group_id;
+	uint16_t	req_size;
 	/*
-	 * Dynamically reconfigure EEM pending cache every 1/10th of second.
-	 * If set to 0 it will disable the EEM HW flush of the pending cache.
+	 * This is the DMA address for the request input data array
+	 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
+	 * array buffer is provided by the 'req_size' field in this
+	 * message.
 	 */
-	uint8_t	flush_interval;
-	/* unused. */
-	uint8_t	unused0;
+	uint64_t	req_addr;
 	/*
-	 * Configured EXT EM with the given number of entries. All
-	 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
-	 * same number of entries and all tables will be configured
-	 * using this value. Current minimum value is 32k. Current
-	 * maximum value is 128M.
+	 * This is the DMA address for the resc output data array
+	 * buffer. Array is of tf_rm_resc_entry type. Size of the array
+	 * buffer is provided by the 'req_size' field in this
+	 * message.
 	 */
-	uint32_t	num_entries;
-	/* unused. */
-	uint32_t	unused1;
-	/* Configured EXT EM with the given context if for KEY0 table. */
-	uint16_t	key0_ctx_id;
-	/* Configured EXT EM with the given context if for KEY1 table. */
-	uint16_t	key1_ctx_id;
-	/* Configured EXT EM with the given context if for RECORD table. */
-	uint16_t	record_ctx_id;
-	/* Configured EXT EM with the given context if for EFC table. */
-	uint16_t	efc_ctx_id;
-	/* Configured EXT EM with the given context if for EFC table. */
-	uint16_t	fid_ctx_id;
-	/* unused. */
-	uint16_t	unused2;
-	/* unused. */
-	uint32_t	unused3;
+	uint64_t	resc_addr;
 } __rte_packed;
 
-/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
-struct hwrm_tf_ext_em_cfg_output {
+/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
+struct hwrm_tf_session_resc_alloc_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38446,26 +40557,33 @@ struct hwrm_tf_ext_em_cfg_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/*
+	 * Size of the returned tf_rm_resc_entry data array. The value
+	 * cannot exceed the req_size defined by the input msg. The data
+	 * array is returned using the resv_addr specified DMA
+	 * address also provided by the input msg.
+	 */
+	uint16_t	size;
 	/* unused. */
-	uint8_t	unused0[7];
+	uint8_t	unused0[5];
 	/*
-	 * This field is used in Output records to indicate that the
-	 * output is completely written to RAM. This field should be
-	 * read as '1' to indicate that the output has been
-	 * completely written.  When writing a command completion or
-	 * response to an internal processor, the order of writes has
-	 * to be such that this field is written last.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field is
+	 * written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/***********************
- * hwrm_tf_ext_em_qcfg *
- ***********************/
+/*****************************
+ * hwrm_tf_session_resc_free *
+ *****************************/
 
 
-/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
-struct hwrm_tf_ext_em_qcfg_input {
+/* hwrm_tf_session_resc_free_input (size:256b/32B) */
+struct hwrm_tf_session_resc_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38494,22 +40612,34 @@ struct hwrm_tf_ext_em_qcfg_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
 	/* Control flags. */
-	uint32_t	flags;
+	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR     UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
-	/* unused. */
-	uint32_t	unused0;
-} __rte_packed;
-
-/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */
-struct hwrm_tf_ext_em_qcfg_output {
+	#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
+	/*
+	 * Defines the size, in bytes, of the provided free_addr
+	 * buffer.
+	 */
+	uint16_t	free_size;
+	/*
+	 * This is the DMA address for the free input data array
+	 * buffer.  Array is of tf_rm_resc_entry type. Size of the
+	 * buffer is provided by the 'free_size' field of this
+	 * message.
+	 */
+	uint64_t	free_addr;
+} __rte_packed;
+
+/* hwrm_tf_session_resc_free_output (size:128b/16B) */
+struct hwrm_tf_session_resc_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38518,54 +40648,26 @@ struct hwrm_tf_ext_em_qcfg_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Control flags. */
-	uint32_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
-		UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
-		UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
-		UINT32_C(0x1)
-	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
-		HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
-	/* When set to 1, all offloaded flows will be sent to EXT EM. */
-	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
-		UINT32_C(0x2)
-	/* The number of entries the FW has configured for EXT EM. */
-	uint32_t	num_entries;
-	/* Configured EXT EM with the given context if for KEY0 table. */
-	uint16_t	key0_ctx_id;
-	/* Configured EXT EM with the given context if for KEY1 table. */
-	uint16_t	key1_ctx_id;
-	/* Configured EXT EM with the given context if for RECORD table. */
-	uint16_t	record_ctx_id;
-	/* Configured EXT EM with the given context if for EFC table. */
-	uint16_t	efc_ctx_id;
-	/* Configured EXT EM with the given context if for EFC table. */
-	uint16_t	fid_ctx_id;
 	/* unused. */
-	uint8_t	unused0[5];
+	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the
-	 * output is completely written to RAM. This field should be
-	 * read as '1' to indicate that the output has been
-	 * completely written.  When writing a command completion or
-	 * response to an internal processor, the order of writes has
-	 * to be such that this field is written last.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field is
+	 * written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/*********************
- * hwrm_tf_em_insert *
- *********************/
+/******************************
+ * hwrm_tf_session_resc_flush *
+ ******************************/
 
 
-/* hwrm_tf_em_insert_input (size:832b/104B) */
-struct hwrm_tf_em_insert_input {
+/* hwrm_tf_session_resc_flush_input (size:256b/32B) */
+struct hwrm_tf_session_resc_flush_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38594,34 +40696,34 @@ struct hwrm_tf_em_insert_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware Session Id. */
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
 	uint32_t	fw_session_id;
-	/* Control Flags. */
+	/* Control flags. */
 	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR     UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
-	/* Reported match strength. */
-	uint16_t	strength;
-	/* Index to action. */
-	uint32_t	action_ptr;
-	/* Index of EM record. */
-	uint32_t	em_record_idx;
-	/* EM Key value. */
-	uint64_t	em_key[8];
-	/* Number of bits in em_key. */
-	uint16_t	em_key_bitlen;
-	/* unused. */
-	uint16_t	unused0[3];
+	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
+	/*
+	 * Defines the size, in bytes, of the provided flush_addr
+	 * buffer.
+	 */
+	uint16_t	flush_size;
+	/*
+	 * This is the DMA address for the flush input data array
+	 * buffer.  Array of tf_rm_resc_entry type. Size of the
+	 * buffer is provided by the 'flush_size' field in this
+	 * message.
+	 */
+	uint64_t	flush_addr;
 } __rte_packed;
 
-/* hwrm_tf_em_insert_output (size:128b/16B) */
-struct hwrm_tf_em_insert_output {
+/* hwrm_tf_session_resc_flush_output (size:128b/16B) */
+struct hwrm_tf_session_resc_flush_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38630,23 +40732,48 @@ struct hwrm_tf_em_insert_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* EM record pointer index. */
-	uint16_t	rptr_index;
-	/* EM record offset 0~3. */
-	uint8_t	rptr_entry;
-	/* Number of word entries consumed by the key. */
-	uint8_t	num_of_entries;
 	/* unused. */
-	uint32_t	unused0;
+	uint8_t	unused0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field is
+	 * written last.
+	 */
+	uint8_t	valid;
 } __rte_packed;
 
-/*********************
- * hwrm_tf_em_delete *
- *********************/
+/* TruFlow RM capability of a resource. */
+/* tf_rm_resc_req_entry (size:64b/8B) */
+struct tf_rm_resc_req_entry {
+	/* Type of the resource, defined globally in HCAPI RM. */
+	uint32_t	type;
+	/* Minimum value. */
+	uint16_t	min;
+	/* Maximum value. */
+	uint16_t	max;
+} __rte_packed;
 
+/* TruFlow RM reservation information. */
+/* tf_rm_resc_entry (size:64b/8B) */
+struct tf_rm_resc_entry {
+	/* Type of the resource, defined globally in HCAPI RM. */
+	uint32_t	type;
+	/* Start offset. */
+	uint16_t	start;
+	/* Number of resources. */
+	uint16_t	stride;
+} __rte_packed;
 
-/* hwrm_tf_em_delete_input (size:832b/104B) */
-struct hwrm_tf_em_delete_input {
+/************************
+ * hwrm_tf_tbl_type_get *
+ ************************/
+
+
+/* hwrm_tf_tbl_type_get_input (size:256b/32B) */
+struct hwrm_tf_tbl_type_get_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38675,32 +40802,31 @@ struct hwrm_tf_em_delete_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Session Id. */
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
 	uint32_t	fw_session_id;
 	/* Control flags. */
 	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
-	/* Unused0 */
-	uint16_t	unused0;
-	/* EM internal flow hanndle. */
-	uint64_t	flow_handle;
-	/* EM Key value */
-	uint64_t	em_key[8];
-	/* Number of bits in em_key. */
-	uint16_t	em_key_bitlen;
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
 	/* unused. */
-	uint16_t	unused1[3];
+	uint8_t	unused0[2];
+	/*
+	 * Type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
+	 */
+	uint32_t	type;
+	/* Index of the type to retrieve. */
+	uint32_t	index;
 } __rte_packed;
 
-/* hwrm_tf_em_delete_output (size:128b/16B) */
-struct hwrm_tf_em_delete_output {
+/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
+struct hwrm_tf_tbl_type_get_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38709,19 +40835,34 @@ struct hwrm_tf_em_delete_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Original stack allocation index. */
-	uint16_t	em_index;
-	/* unused. */
-	uint16_t	unused0[3];
+	/* Response code. */
+	uint32_t	resp_code;
+	/* Response size. */
+	uint16_t	size;
+	/* unused */
+	uint16_t	unused0;
+	/* Response data. */
+	uint8_t	data[128];
+	/* unused */
+	uint8_t	unused1[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
+	 */
+	uint8_t	valid;
 } __rte_packed;
 
-/********************
- * hwrm_tf_tcam_set *
- ********************/
+/************************
+ * hwrm_tf_tbl_type_set *
+ ************************/
 
 
-/* hwrm_tf_tcam_set_input (size:1024b/128B) */
-struct hwrm_tf_tcam_set_input {
+/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
+struct hwrm_tf_tbl_type_set_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38753,49 +40894,34 @@ struct hwrm_tf_tcam_set_input {
 	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
 	uint32_t	fw_session_id;
 	/* Control flags. */
-	uint32_t	flags;
+	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
-	/*
-	 * Indicate device data is being sent via DMA, the device
-	 * data is packing does not change.
-	 */
-	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA     UINT32_C(0x2)
+	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
+	/* unused. */
+	uint8_t	unused0[2];
 	/*
-	 * TCAM type of the resource, defined globally in the
+	 * Type of the resource, defined globally in the
 	 * hwrm_tf_resc_type enum.
 	 */
 	uint32_t	type;
-	/* Index of TCAM entry. */
-	uint16_t	idx;
-	/* Number of bytes in the TCAM key. */
-	uint8_t	key_size;
-	/* Number of bytes in the TCAM result. */
-	uint8_t	result_size;
-	/*
-	 * Offset from which the mask bytes start in the device data
-	 * array, key offset is always 0.
-	 */
-	uint8_t	mask_offset;
-	/* Offset from which the result bytes start in the device data array. */
-	uint8_t	result_offset;
-	/* unused. */
-	uint8_t	unused0[6];
-	/*
-	 * TCAM key located at offset 0, mask located at mask_offsec
-	 * and result at result_offsec for the device.
-	 */
-	uint8_t	dev_data[88];
+	/* Index of the type to retrieve. */
+	uint32_t	index;
+	/* Size of the data to set. */
+	uint16_t	size;
+	/* unused */
+	uint8_t	unused1[6];
+	/* Data to be set. */
+	uint8_t	data[88];
 } __rte_packed;
 
-/* hwrm_tf_tcam_set_output (size:128b/16B) */
-struct hwrm_tf_tcam_set_output {
+/* hwrm_tf_tbl_type_set_output (size:128b/16B) */
+struct hwrm_tf_tbl_type_set_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38807,23 +40933,23 @@ struct hwrm_tf_tcam_set_output {
 	/* unused. */
 	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the
-	 * output is completely written to RAM. This field should be
-	 * read as '1' to indicate that the output has been
-	 * completely written.  When writing a command completion or
-	 * response to an internal processor, the order of writes has
-	 * to be such that this field is written last.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/********************
- * hwrm_tf_tcam_get *
- ********************/
+/**************************
+ * hwrm_tf_ctxt_mem_alloc *
+ **************************/
 
 
-/* hwrm_tf_tcam_get_input (size:256b/32B) */
-struct hwrm_tf_tcam_get_input {
+/* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */
+struct hwrm_tf_ctxt_mem_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38852,31 +40978,14 @@ struct hwrm_tf_tcam_get_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint32_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
-	/*
-	 * TCAM type of the resource, defined globally in the
-	 * hwrm_tf_resc_type enum.
-	 */
-	uint32_t	type;
-	/* Index of a TCAM entry. */
-	uint16_t	idx;
+	/* Size in KB of memory to be allocated. */
+	uint32_t	mem_size;
 	/* unused. */
-	uint16_t	unused0;
+	uint32_t	unused0;
 } __rte_packed;
 
-/* hwrm_tf_tcam_get_output (size:2368b/296B) */
-struct hwrm_tf_tcam_get_output {
+/* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */
+struct hwrm_tf_ctxt_mem_alloc_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38885,23 +40994,49 @@ struct hwrm_tf_tcam_get_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Number of bytes in the TCAM key. */
-	uint8_t	key_size;
-	/* Number of bytes in the TCAM entry. */
-	uint8_t	result_size;
-	/* Offset from which the mask bytes start in the device data array. */
-	uint8_t	mask_offset;
-	/* Offset from which the result bytes start in the device data array. */
-	uint8_t	result_offset;
-	/* unused. */
-	uint8_t	unused0[4];
+	/* Pointer to the PBL, or PDL depending on number of levels */
+	uint64_t	page_dir;
+	/* Counter PBL indirect levels. */
+	uint8_t	page_level;
+	/* PBL pointer is physical start address. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+	/* PBL pointer points to PTE table. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
 	/*
-	 * TCAM key located at offset 0, mask located at mask_offsec
-	 * and result at result_offsec for the device.
+	 * PBL pointer points to PDE table with each entry pointing
+	 * to PTE tables.
 	 */
-	uint8_t	dev_data[272];
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \
+		HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2
+	/* Page size. */
+	uint8_t	page_size;
+	/* 4KB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K   UINT32_C(0x0)
+	/* 8KB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K   UINT32_C(0x1)
+	/* 64KB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K  UINT32_C(0x4)
+	/* 128KB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)
+	/* 256KB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+	/* 512KB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)
+	/* 1MB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M   UINT32_C(0x8)
+	/* 2MB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M   UINT32_C(0x9)
+	/* 4MB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M   UINT32_C(0xa)
+	/* 8MB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M   UINT32_C(0xb)
+	/* 1GB page size. */
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G   UINT32_C(0x12)
+	#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \
+		HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G
 	/* unused. */
-	uint8_t	unused1[7];
+	uint8_t	unused0[5];
 	/*
 	 * This field is used in Output records to indicate that the
 	 * output is completely written to RAM. This field should be
@@ -38913,13 +41048,13 @@ struct hwrm_tf_tcam_get_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*********************
- * hwrm_tf_tcam_move *
- *********************/
+/*************************
+ * hwrm_tf_ctxt_mem_free *
+ *************************/
 
 
-/* hwrm_tf_tcam_move_input (size:1024b/128B) */
-struct hwrm_tf_tcam_move_input {
+/* hwrm_tf_ctxt_mem_free_input (size:256b/32B) */
+struct hwrm_tf_ctxt_mem_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -38948,33 +41083,53 @@ struct hwrm_tf_tcam_move_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint32_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
+	/* Pointer to the PBL, or PDL depending on number of levels */
+	uint64_t	page_dir;
+	/* Counter PBL indirect levels. */
+	uint8_t	page_level;
+	/* PBL pointer is physical start address. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+	/* PBL pointer points to PTE table. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
 	/*
-	 * TCAM type of the resource, defined globally in the
-	 * hwrm_tf_resc_type enum.
+	 * PBL pointer points to PDE table with each entry pointing
+	 * to PTE tables.
 	 */
-	uint32_t	type;
-	/* Number of TCAM index pairs to be swapped for the device. */
-	uint16_t	count;
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \
+		HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2
+	/* Page size. */
+	uint8_t	page_size;
+	/* 4KB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K   UINT32_C(0x0)
+	/* 8KB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K   UINT32_C(0x1)
+	/* 64KB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K  UINT32_C(0x4)
+	/* 128KB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
+	/* 256KB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+	/* 512KB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
+	/* 1MB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M   UINT32_C(0x8)
+	/* 2MB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M   UINT32_C(0x9)
+	/* 4MB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M   UINT32_C(0xa)
+	/* 8MB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M   UINT32_C(0xb)
+	/* 1GB page size. */
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)
+	#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \
+		HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G
 	/* unused. */
-	uint16_t	unused0;
-	/* TCAM index pairs to be swapped for the device. */
-	uint16_t	idx_pairs[48];
+	uint8_t	unused0[6];
 } __rte_packed;
 
-/* hwrm_tf_tcam_move_output (size:128b/16B) */
-struct hwrm_tf_tcam_move_output {
+/* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */
+struct hwrm_tf_ctxt_mem_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -38996,13 +41151,13 @@ struct hwrm_tf_tcam_move_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*********************
- * hwrm_tf_tcam_free *
- *********************/
+/*************************
+ * hwrm_tf_ctxt_mem_rgtr *
+ *************************/
 
 
-/* hwrm_tf_tcam_free_input (size:1024b/128B) */
-struct hwrm_tf_tcam_free_input {
+/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
+struct hwrm_tf_ctxt_mem_rgtr_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39031,33 +41186,55 @@ struct hwrm_tf_tcam_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
 	/* Control flags. */
-	uint32_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
+	uint16_t	flags;
+	/* Counter PBL indirect levels. */
+	uint8_t	page_level;
+	/* PBL pointer is physical start address. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+	/* PBL pointer points to PTE table. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
 	/*
-	 * TCAM type of the resource, defined globally in the
-	 * hwrm_tf_resc_type enum.
+	 * PBL pointer points to PDE table with each entry pointing
+	 * to PTE tables.
 	 */
-	uint32_t	type;
-	/* Number of TCAM index to be deleted for the device. */
-	uint16_t	count;
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
+		HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
+	/* Page size. */
+	uint8_t	page_size;
+	/* 4KB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K   UINT32_C(0x0)
+	/* 8KB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K   UINT32_C(0x1)
+	/* 64KB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K  UINT32_C(0x4)
+	/* 128KB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
+	/* 256KB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+	/* 512KB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
+	/* 1MB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M   UINT32_C(0x8)
+	/* 2MB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M   UINT32_C(0x9)
+	/* 4MB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M   UINT32_C(0xa)
+	/* 8MB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M   UINT32_C(0xb)
+	/* 1GB page size. */
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)
+	#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
+		HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
 	/* unused. */
-	uint16_t	unused0;
-	/* TCAM index list to be deleted for the device. */
-	uint16_t	idx_list[48];
+	uint32_t	unused0;
+	/* Pointer to the PBL, or PDL depending on number of levels */
+	uint64_t	page_dir;
 } __rte_packed;
 
-/* hwrm_tf_tcam_free_output (size:128b/16B) */
-struct hwrm_tf_tcam_free_output {
+/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
+struct hwrm_tf_ctxt_mem_rgtr_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39066,8 +41243,13 @@ struct hwrm_tf_tcam_free_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/*
+	 * Id/Handle to the recently register context memory. This
+	 * handle is passed to the TF session.
+	 */
+	uint16_t	ctx_id;
 	/* unused. */
-	uint8_t	unused0[7];
+	uint8_t	unused0[5];
 	/*
 	 * This field is used in Output records to indicate that the
 	 * output is completely written to RAM. This field should be
@@ -39079,13 +41261,13 @@ struct hwrm_tf_tcam_free_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**************************
- * hwrm_tf_global_cfg_set *
- **************************/
+/***************************
+ * hwrm_tf_ctxt_mem_unrgtr *
+ ***************************/
 
 
-/* hwrm_tf_global_cfg_set_input (size:448b/56B) */
-struct hwrm_tf_global_cfg_set_input {
+/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
+struct hwrm_tf_ctxt_mem_unrgtr_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39114,34 +41296,17 @@ struct hwrm_tf_global_cfg_set_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
-	/* Control flags. */
-	uint32_t	flags;
-	/* Indicates the flow direction. */
-	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
-	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
-	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
-	/* Global Cfg type */
-	uint32_t	type;
-	/* Offset of the type */
-	uint32_t	offset;
-	/* Size of the data to set in bytes */
-	uint16_t	size;
-	/* unused. */
-	uint8_t	unused0[6];
-	/* Data to set */
-	uint8_t	data[8];
-	/* Mask of data to set, 0 indicates no mask */
-	uint8_t	mask[8];
+	/*
+	 * Id/Handle to the recently register context memory. This
+	 * handle is passed to the TF session.
+	 */
+	uint16_t	ctx_id;
+	/* unused. */
+	uint8_t	unused0[6];
 } __rte_packed;
 
-/* hwrm_tf_global_cfg_set_output (size:128b/16B) */
-struct hwrm_tf_global_cfg_set_output {
+/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
+struct hwrm_tf_ctxt_mem_unrgtr_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39163,13 +41328,13 @@ struct hwrm_tf_global_cfg_set_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**************************
- * hwrm_tf_global_cfg_get *
- **************************/
+/************************
+ * hwrm_tf_ext_em_qcaps *
+ ************************/
 
 
-/* hwrm_tf_global_cfg_get_input (size:320b/40B) */
-struct hwrm_tf_global_cfg_get_input {
+/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
+struct hwrm_tf_ext_em_qcaps_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39198,30 +41363,28 @@ struct hwrm_tf_global_cfg_get_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
 	/* Control flags. */
 	uint32_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
+		UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
+		UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
-	/* Global Cfg type */
-	uint32_t	type;
-	/* Offset of the type */
-	uint32_t	offset;
-	/* Size of the data to set in bytes */
-	uint16_t	size;
+	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
+		UINT32_C(0x1)
+	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
+	/* When set to 1, all offloaded flows will be sent to EXT EM. */
+	#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
+		UINT32_C(0x2)
 	/* unused. */
-	uint8_t	unused0[6];
+	uint32_t	unused0;
 } __rte_packed;
 
-/* hwrm_tf_global_cfg_get_output (size:256b/32B) */
-struct hwrm_tf_global_cfg_get_output {
+/* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */
+struct hwrm_tf_ext_em_qcaps_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39230,21 +41393,133 @@ struct hwrm_tf_global_cfg_get_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Size of the data read in bytes */
-	uint16_t	size;
+	uint32_t	flags;
+	/*
+	 * When set to 1, indicates the the FW supports the Centralized
+	 * Memory Model. The concept designates one entity for the
+	 * memory allocation while all others ‘subscribe’ to it.
+	 */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+		UINT32_C(0x1)
+	/*
+	 * When set to 1, indicates the the FW supports the Detached
+	 * Centralized Memory Model. The memory is allocated and managed
+	 * as a separate entity. All PFs and VFs will be granted direct
+	 * or semi-direct access to the allocated memory while none of
+	 * which can interfere with the management of the memory.
+	 */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+		UINT32_C(0x2)
+	/* When set to 1, indicates FW support for host based EEM memory. */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \
+		UINT32_C(0x4)
+	/* When set to 1, indicates FW support for on-chip based EEM memory. */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \
+		UINT32_C(0x8)
 	/* unused. */
-	uint8_t	unused0[6];
-	/* Data to set */
-	uint8_t	data[16];
+	uint32_t	unused0;
+	/* Support flags. */
+	uint32_t	supported;
+	/*
+	 * If set to 1, then EXT EM KEY0 table is supported using
+	 * crc32 hash.
+	 * If set to 0, EXT EM KEY0 table is not supported.
+	 */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
+		UINT32_C(0x1)
+	/*
+	 * If set to 1, then EXT EM KEY1 table is supported using
+	 * lookup3 hash.
+	 * If set to 0, EXT EM KEY1 table is not supported.
+	 */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
+		UINT32_C(0x2)
+	/*
+	 * If set to 1, then EXT EM External Record table is supported.
+	 * If set to 0, EXT EM External Record table is not
+	 * supported.  (This table includes action record, EFC
+	 * pointers, encap pointers)
+	 */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
+		UINT32_C(0x4)
+	/*
+	 * If set to 1, then EXT EM External Flow Counters table is
+	 * supported.
+	 * If set to 0, EXT EM External Flow Counters table is not
+	 * supported.
+	 */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
+		UINT32_C(0x8)
+	/*
+	 * If set to 1, then FID table used for implicit flow flush
+	 * is supported.
+	 * If set to 0, then FID table used for implicit flow flush
+	 * is not supported.
+	 */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
+		UINT32_C(0x10)
+	/*
+	 * If set to 1, then table scopes are supported.
+	 * If set to 0, then table scopes are not supported.
+	 */
+	#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \
+		UINT32_C(0x20)
+	/*
+	 * The maximum number of entries supported by EXT EM. When
+	 * configuring the host memory the number of numbers of
+	 * entries that can supported are -
+	 *      32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
+	 *      128M entries.
+	 * Any value that are not these values, the FW will round
+	 * down to the closest support number of entries.
+	 */
+	uint32_t	max_entries_supported;
+	/*
+	 * The entry size in bytes of each entry in the EXT EM
+	 * KEY0/KEY1 tables.
+	 */
+	uint16_t	key_entry_size;
+	/*
+	 * The entry size in bytes of each entry in the EXT EM RECORD
+	 * tables.
+	 */
+	uint16_t	record_entry_size;
+	/* The entry size in bytes of each entry in the EXT EM EFC tables. */
+	uint16_t	efc_entry_size;
+	/* The FID size in bytes of each entry in the EXT EM FID tables. */
+	uint16_t	fid_entry_size;
+	/* Maximum number of ctxt mem allocations allowed. */
+	uint32_t	max_ctxt_mem_allocs;
+	/*
+	 * Maximum number of static buckets that can be assigned to lookup
+	 * table scopes.
+	 */
+	uint32_t	max_static_buckets;
+	/*
+	 * Maximum number of all (static and dynamic) buckets that can
+	 * be assigned to lookup table scopes.
+	 */
+	uint32_t	max_total_buckets;
+	/* unused. */
+	uint8_t	unused1[3];
+	/*
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
+	 */
+	uint8_t	valid;
 } __rte_packed;
 
-/**********************
- * hwrm_tf_if_tbl_get *
- **********************/
+/*********************
+ * hwrm_tf_ext_em_op *
+ *********************/
 
 
-/* hwrm_tf_if_tbl_get_input (size:256b/32B) */
-struct hwrm_tf_if_tbl_get_input {
+/* hwrm_tf_ext_em_op_input (size:192b/24B) */
+struct hwrm_tf_ext_em_op_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39273,31 +41548,51 @@ struct hwrm_tf_if_tbl_get_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
 	/* Control flags. */
 	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR     UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
-	/* Size of the data to set. */
-	uint16_t	size;
+	#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
+	/* unused. */
+	uint16_t	unused0;
+	/* The number of EXT EM key table entries to be configured. */
+	uint16_t	op;
+	/* This value is reserved and should not be used. */
+	#define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED       UINT32_C(0x0)
 	/*
-	 * Type of the resource, defined globally in the
-	 * hwrm_tf_resc_type enum.
+	 * To properly stop EXT EM and ensure there are no DMA's,
+	 * the caller must disable EXT EM for the given PF, using
+	 * this call. This will safely disable EXT EM and ensure
+	 * that all DMA'ed to the keys/records/efc have been
+	 * completed.
 	 */
-	uint32_t	type;
-	/* Index of the type to retrieve. */
-	uint32_t	index;
+	#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
+	/*
+	 * Once the EXT EM host memory has been configured, EXT EM
+	 * options have been configured. Then the caller should
+	 * enable EXT EM for the given PF. Note once this call has
+	 * been made, then the EXT EM mechanism will be active and
+	 * DMA's will occur as packets are processed.
+	 */
+	#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE  UINT32_C(0x2)
+	/*
+	 * Clear EXT EM settings for the given PF so that the
+	 * register values are reset back to their initial state.
+	 */
+	#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
+	#define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
+		HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
+	/* unused. */
+	uint16_t	unused1;
 } __rte_packed;
 
-/* hwrm_tf_if_tbl_get_output (size:256b/32B) */
-struct hwrm_tf_if_tbl_get_output {
+/* hwrm_tf_ext_em_op_output (size:128b/16B) */
+struct hwrm_tf_ext_em_op_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39306,34 +41601,26 @@ struct hwrm_tf_if_tbl_get_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Response code. */
-	uint32_t	resp_code;
-	/* Response size. */
-	uint16_t	size;
-	/* unused */
-	uint16_t	unused0;
-	/* Response data. */
-	uint8_t	data[8];
-	/* unused */
-	uint8_t	unused1[7];
+	/* unused. */
+	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM. This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field
-	 * is written last.
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/***************************
- * hwrm_tf_if_tbl_type_set *
- ***************************/
+/**********************
+ * hwrm_tf_ext_em_cfg *
+ **********************/
 
 
-/* hwrm_tf_if_tbl_set_input (size:384b/48B) */
-struct hwrm_tf_if_tbl_set_input {
+/* hwrm_tf_ext_em_cfg_input (size:512b/64B) */
+struct hwrm_tf_ext_em_cfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39362,37 +41649,163 @@ struct hwrm_tf_if_tbl_set_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
-	uint32_t	fw_session_id;
 	/* Control flags. */
-	uint16_t	flags;
+	uint32_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
+		UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
+		UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates that tx flow. */
-	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
-	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
-		HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
+	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
+		UINT32_C(0x1)
+	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
+	/* When set to 1, all offloaded flows will be sent to EXT EM. */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
+		UINT32_C(0x2)
+	/* When set to 1, secondary, 0 means primary. */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
+		UINT32_C(0x4)
+	/*
+	 * Group_id which used by Firmware to identify memory pools belonging
+	 * to certain group.
+	 */
+	uint16_t	group_id;
+	/*
+	 * Dynamically reconfigure EEM pending cache every 1/10th of second.
+	 * If set to 0 it will disable the EEM HW flush of the pending cache.
+	 */
+	uint8_t	flush_interval;
 	/* unused. */
-	uint8_t	unused0[2];
+	uint8_t	unused0;
 	/*
-	 * Type of the resource, defined globally in the
-	 * hwrm_tf_resc_type enum.
+	 * Configured EXT EM with the given number of entries. All
+	 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
+	 * same number of entries and all tables will be configured
+	 * using this value. Current minimum value is 32k. Current
+	 * maximum value is 128M.
 	 */
-	uint32_t	type;
-	/* Index of the type to set. */
-	uint32_t	index;
-	/* Size of the data to set. */
-	uint16_t	size;
-	/* unused */
-	uint8_t	unused1[6];
-	/* Data to be set. */
-	uint8_t	data[8];
+	uint32_t	num_entries;
+	uint32_t	enables;
+	/*
+	 * This bit must be '1' for the group_id field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \
+		UINT32_C(0x1)
+	/*
+	 * This bit must be '1' for the flush_interval field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \
+		UINT32_C(0x2)
+	/*
+	 * This bit must be '1' for the num_entries field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \
+		UINT32_C(0x4)
+	/*
+	 * This bit must be '1' for the key0_ctx_id field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \
+		UINT32_C(0x8)
+	/*
+	 * This bit must be '1' for the key1_ctx_id field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \
+		UINT32_C(0x10)
+	/*
+	 * This bit must be '1' for the record_ctx_id field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \
+		UINT32_C(0x20)
+	/*
+	 * This bit must be '1' for the efc_ctx_id field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \
+		UINT32_C(0x40)
+	/*
+	 * This bit must be '1' for the fid_ctx_id field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \
+		UINT32_C(0x80)
+	/*
+	 * This bit must be '1' for the action_ctx_id field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \
+		UINT32_C(0x100)
+	/*
+	 * This bit must be '1' for the action_tbl_scope field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \
+		UINT32_C(0x200)
+	/*
+	 * This bit must be '1' for the lkup_ctx_id field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \
+		UINT32_C(0x400)
+	/*
+	 * This bit must be '1' for the lkup_tbl_scope field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \
+		UINT32_C(0x800)
+	/*
+	 * This bit must be '1' for the lkup_static_buckets field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \
+		UINT32_C(0x1000)
+	/*
+	 * This bit must be '1' for the lkup_dynamic_buckets field to be
+	 * configured.
+	 */
+	#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_DYNAMIC_BUCKETS \
+		UINT32_C(0x2000)
+	/* Configured EXT EM with the given context if for KEY0 table. */
+	uint16_t	key0_ctx_id;
+	/* Configured EXT EM with the given context if for KEY1 table. */
+	uint16_t	key1_ctx_id;
+	/* Configured EXT EM with the given context if for RECORD table. */
+	uint16_t	record_ctx_id;
+	/* Configured EXT EM with the given context if for EFC table. */
+	uint16_t	efc_ctx_id;
+	/* Configured EXT EM with the given context if for EFC table. */
+	uint16_t	fid_ctx_id;
+	/* Context id of action table scope. */
+	uint16_t	action_ctx_id;
+	/* Table scope id used for action record entries. */
+	uint16_t	action_tbl_scope;
+	/* Context id of lookup table scope. */
+	uint16_t	lkup_ctx_id;
+	/* Table scope id used for EM lookup entries. */
+	uint16_t	lkup_tbl_scope;
+	/* unused. */
+	uint16_t	unused1;
+	/*
+	 * Number of 32B static buckets to be allocated at the beginning
+	 * of table scope.
+	 */
+	uint32_t	lkup_static_buckets;
+	/* Number of 32B dynamic buckets to be allocated. */
+	uint32_t	lkup_dynamic_buckets;
+	/* unused. */
+	uint32_t	unused2;
 } __rte_packed;
 
-/* hwrm_tf_if_tbl_set_output (size:128b/16B) */
-struct hwrm_tf_if_tbl_set_output {
+/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
+struct hwrm_tf_ext_em_cfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39404,23 +41817,23 @@ struct hwrm_tf_if_tbl_set_output {
 	/* unused. */
 	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM. This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal
-	 * processor, the order of writes has to be such that this field
-	 * is written last.
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/******************************
- * hwrm_tunnel_dst_port_query *
- ******************************/
+/***********************
+ * hwrm_tf_ext_em_qcfg *
+ ***********************/
 
 
-/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
-struct hwrm_tunnel_dst_port_query_input {
+/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
+struct hwrm_tf_ext_em_qcfg_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39449,33 +41862,22 @@ struct hwrm_tunnel_dst_port_query_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Tunnel Type. */
-	uint8_t	tunnel_type;
-	/* Virtual eXtensible Local Area Network (VXLAN) */
-	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
-		UINT32_C(0x1)
-	/* Generic Network Virtualization Encapsulation (Geneve) */
-	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
-		UINT32_C(0x5)
-	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
-	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
-		UINT32_C(0x9)
-	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
-	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
-		UINT32_C(0xa)
-	/* Use fixed layer 2 ether type of 0xFFFF */
-	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
-		UINT32_C(0xb)
-	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
-	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
-		UINT32_C(0xc)
-	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
-		HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
-	uint8_t	unused_0[7];
+	/* Control flags. */
+	uint32_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
+	/* unused. */
+	uint32_t	unused0;
 } __rte_packed;
 
-/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
-struct hwrm_tunnel_dst_port_query_output {
+/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */
+struct hwrm_tf_ext_em_qcfg_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39484,42 +41886,123 @@ struct hwrm_tunnel_dst_port_query_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/* Control flags. */
+	uint32_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
+		UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
+		UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
+		UINT32_C(0x1)
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
+		HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
+	/* When set to 1, all offloaded flows will be sent to EXT EM. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
+		UINT32_C(0x2)
+	/* The number of entries the FW has configured for EXT EM. */
+	uint32_t	num_entries;
+	/* Configured EXT EM with the given context if for KEY0 table. */
+	uint16_t	key0_ctx_id;
+	/* Configured EXT EM with the given context if for KEY1 table. */
+	uint16_t	key1_ctx_id;
+	/* Configured EXT EM with the given context if for RECORD table. */
+	uint16_t	record_ctx_id;
+	/* Configured EXT EM with the given context if for EFC table. */
+	uint16_t	efc_ctx_id;
+	/* Configured EXT EM with the given context if for EFC table. */
+	uint16_t	fid_ctx_id;
+	/* unused. */
+	uint16_t	unused0;
+	uint32_t	supported;
+	/* This bit must be '1' for the group_id field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \
+		UINT32_C(0x1)
+	/* This bit must be '1' for the flush_interval field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \
+		UINT32_C(0x2)
+	/* This bit must be '1' for the num_entries field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \
+		UINT32_C(0x4)
+	/* This bit must be '1' for the key0_ctx_id field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \
+		UINT32_C(0x8)
+	/* This bit must be '1' for the key1_ctx_id field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \
+		UINT32_C(0x10)
+	/* This bit must be '1' for the record_ctx_id field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \
+		UINT32_C(0x20)
+	/* This bit must be '1' for the efc_ctx_id field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \
+		UINT32_C(0x40)
+	/* This bit must be '1' for the fid_ctx_id field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \
+		UINT32_C(0x80)
+	/* This bit must be '1' for the action_ctx_id field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \
+		UINT32_C(0x100)
+	/* This bit must be '1' for the action_tbl_scope field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \
+		UINT32_C(0x200)
+	/* This bit must be '1' for the lkup_ctx_id field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \
+		UINT32_C(0x400)
+	/* This bit must be '1' for the lkup_tbl_scope field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \
+		UINT32_C(0x800)
+	/* This bit must be '1' for the lkup_static_buckets field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \
+		UINT32_C(0x1000)
+	/* This bit must be '1' for the lkup_dynamic_buckets field is set. */
+	#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_DYNAMIC_BUCKETS \
+		UINT32_C(0x2000)
 	/*
-	 * This field represents the identifier of L4 destination port
-	 * used for the given tunnel type. This field is valid for
-	 * specific tunnel types that use layer 4 (e.g. UDP)
-	 * transports for tunneling.
+	 * Group id is used by firmware to identify memory pools belonging
+	 * to certain group.
 	 */
-	uint16_t	tunnel_dst_port_id;
+	uint16_t	group_id;
+	/* EEM pending cache flush interval in 1/10th of second. */
+	uint8_t	flush_interval;
+	/* unused. */
+	uint8_t	unused1;
+	/* Context id of action table scope. */
+	uint16_t	action_ctx_id;
+	/* Table scope id used for action record entries. */
+	uint16_t	action_tbl_scope;
+	/* Context id of lookup table scope. */
+	uint16_t	lkup_ctx_id;
+	/* Table scope id used for EM lookup entries. */
+	uint16_t	lkup_tbl_scope;
+	/*
+	 * Number of 32B static buckets to be allocated at the beginning
+	 * of table scope.
+	 */
+	uint32_t	lkup_static_buckets;
+	/* Number of 32B dynamic buckets to be allocated. */
+	uint32_t	lkup_dynamic_buckets;
+	/* unused. */
+	uint8_t	unused2[3];
 	/*
-	 * This field represents the value of L4 destination port
-	 * identified by tunnel_dst_port_id. This field is valid for
-	 * specific tunnel types that use layer 4 (e.g. UDP)
-	 * transports for tunneling.
-	 * This field is in network byte order.
-	 *
-	 * A value of 0 means that the destination port is not
-	 * configured.
-	 */
-	uint16_t	tunnel_dst_port_val;
-	uint8_t	unused_0[3];
-	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/******************************
- * hwrm_tunnel_dst_port_alloc *
- ******************************/
+/*********************
+ * hwrm_tf_em_insert *
+ *********************/
 
 
-/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
-struct hwrm_tunnel_dst_port_alloc_input {
+/* hwrm_tf_em_insert_input (size:832b/104B) */
+struct hwrm_tf_em_insert_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39548,45 +42031,34 @@ struct hwrm_tunnel_dst_port_alloc_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Tunnel Type. */
-	uint8_t	tunnel_type;
-	/* Virtual eXtensible Local Area Network (VXLAN) */
-	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
-		UINT32_C(0x1)
-	/* Generic Network Virtualization Encapsulation (Geneve) */
-	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
-		UINT32_C(0x5)
-	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
-	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
-		UINT32_C(0x9)
-	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
-	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
-		UINT32_C(0xa)
-	/* Use fixed layer 2 ether type of 0xFFFF */
-	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
-		UINT32_C(0xb)
-	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
-	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
-		UINT32_C(0xc)
-	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
-		HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
-	uint8_t	unused_0;
-	/*
-	 * This field represents the value of L4 destination port used
-	 * for the given tunnel type. This field is valid for
-	 * specific tunnel types that use layer 4 (e.g. UDP)
-	 * transports for tunneling.
-	 *
-	 * This field is in network byte order.
-	 *
-	 * A value of 0 shall fail the command.
-	 */
-	uint16_t	tunnel_dst_port_val;
-	uint8_t	unused_1[4];
+	/* Firmware Session Id. */
+	uint32_t	fw_session_id;
+	/* Control Flags. */
+	uint16_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
+	/* Reported match strength. */
+	uint16_t	strength;
+	/* Index to action. */
+	uint32_t	action_ptr;
+	/* Index of EM record. */
+	uint32_t	em_record_idx;
+	/* EM Key value. */
+	uint64_t	em_key[8];
+	/* Number of bits in em_key. */
+	uint16_t	em_key_bitlen;
+	/* unused. */
+	uint16_t	unused0[3];
 } __rte_packed;
 
-/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
-struct hwrm_tunnel_dst_port_alloc_output {
+/* hwrm_tf_em_insert_output (size:128b/16B) */
+struct hwrm_tf_em_insert_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39595,29 +42067,23 @@ struct hwrm_tunnel_dst_port_alloc_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/*
-	 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
-	 * types that has l4 destination port parameters.
-	 */
-	uint16_t	tunnel_dst_port_id;
-	uint8_t	unused_0[5];
-	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
-	 */
-	uint8_t	valid;
+	/* EM record pointer index. */
+	uint16_t	rptr_index;
+	/* EM record offset 0~3. */
+	uint8_t	rptr_entry;
+	/* Number of word entries consumed by the key. */
+	uint8_t	num_of_entries;
+	/* unused. */
+	uint32_t	unused0;
 } __rte_packed;
 
-/*****************************
- * hwrm_tunnel_dst_port_free *
- *****************************/
+/*********************
+ * hwrm_tf_em_delete *
+ *********************/
 
 
-/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
-struct hwrm_tunnel_dst_port_free_input {
+/* hwrm_tf_em_delete_input (size:832b/104B) */
+struct hwrm_tf_em_delete_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39646,39 +42112,32 @@ struct hwrm_tunnel_dst_port_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Tunnel Type. */
-	uint8_t	tunnel_type;
-	/* Virtual eXtensible Local Area Network (VXLAN) */
-	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
-		UINT32_C(0x1)
-	/* Generic Network Virtualization Encapsulation (Geneve) */
-	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
-		UINT32_C(0x5)
-	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
-	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
-		UINT32_C(0x9)
-	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
-	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
-		UINT32_C(0xa)
-	/* Use fixed layer 2 ether type of 0xFFFF */
-	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
-		UINT32_C(0xb)
-	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
-	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
-		UINT32_C(0xc)
-	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
-		HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
-	uint8_t	unused_0;
-	/*
-	 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
-	 * types that has l4 destination port parameters.
-	 */
-	uint16_t	tunnel_dst_port_id;
-	uint8_t	unused_1[4];
+	/* Session Id. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint16_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
+	/* Unused0 */
+	uint16_t	unused0;
+	/* EM internal flow hanndle. */
+	uint64_t	flow_handle;
+	/* EM Key value */
+	uint64_t	em_key[8];
+	/* Number of bits in em_key. */
+	uint16_t	em_key_bitlen;
+	/* unused. */
+	uint16_t	unused1[3];
 } __rte_packed;
 
-/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
-struct hwrm_tunnel_dst_port_free_output {
+/* hwrm_tf_em_delete_output (size:128b/16B) */
+struct hwrm_tf_em_delete_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39687,166 +42146,19 @@ struct hwrm_tunnel_dst_port_free_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_1[7];
-	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
-	 */
-	uint8_t	valid;
-} __rte_packed;
-
-/* Periodic statistics context DMA to host. */
-/* ctx_hw_stats (size:1280b/160B) */
-struct ctx_hw_stats {
-	/* Number of received unicast packets */
-	uint64_t	rx_ucast_pkts;
-	/* Number of received multicast packets */
-	uint64_t	rx_mcast_pkts;
-	/* Number of received broadcast packets */
-	uint64_t	rx_bcast_pkts;
-	/* Number of discarded packets on receive path */
-	uint64_t	rx_discard_pkts;
-	/* Number of packets on receive path with error */
-	uint64_t	rx_error_pkts;
-	/* Number of received bytes for unicast traffic */
-	uint64_t	rx_ucast_bytes;
-	/* Number of received bytes for multicast traffic */
-	uint64_t	rx_mcast_bytes;
-	/* Number of received bytes for broadcast traffic */
-	uint64_t	rx_bcast_bytes;
-	/* Number of transmitted unicast packets */
-	uint64_t	tx_ucast_pkts;
-	/* Number of transmitted multicast packets */
-	uint64_t	tx_mcast_pkts;
-	/* Number of transmitted broadcast packets */
-	uint64_t	tx_bcast_pkts;
-	/* Number of packets on transmit path with error */
-	uint64_t	tx_error_pkts;
-	/* Number of discarded packets on transmit path */
-	uint64_t	tx_discard_pkts;
-	/* Number of transmitted bytes for unicast traffic */
-	uint64_t	tx_ucast_bytes;
-	/* Number of transmitted bytes for multicast traffic */
-	uint64_t	tx_mcast_bytes;
-	/* Number of transmitted bytes for broadcast traffic */
-	uint64_t	tx_bcast_bytes;
-	/* Number of TPA packets */
-	uint64_t	tpa_pkts;
-	/* Number of TPA bytes */
-	uint64_t	tpa_bytes;
-	/* Number of TPA events */
-	uint64_t	tpa_events;
-	/* Number of TPA aborts */
-	uint64_t	tpa_aborts;
-} __rte_packed;
-
-/*
- * Extended periodic statistics context DMA to host. On cards that
- * support TPA v2, additional TPA related stats exist and can be retrieved
- * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
- */
-/* ctx_hw_stats_ext (size:1344b/168B) */
-struct ctx_hw_stats_ext {
-	/* Number of received unicast packets */
-	uint64_t	rx_ucast_pkts;
-	/* Number of received multicast packets */
-	uint64_t	rx_mcast_pkts;
-	/* Number of received broadcast packets */
-	uint64_t	rx_bcast_pkts;
-	/* Number of discarded packets on receive path */
-	uint64_t	rx_discard_pkts;
-	/* Number of packets on receive path with error */
-	uint64_t	rx_error_pkts;
-	/* Number of received bytes for unicast traffic */
-	uint64_t	rx_ucast_bytes;
-	/* Number of received bytes for multicast traffic */
-	uint64_t	rx_mcast_bytes;
-	/* Number of received bytes for broadcast traffic */
-	uint64_t	rx_bcast_bytes;
-	/* Number of transmitted unicast packets */
-	uint64_t	tx_ucast_pkts;
-	/* Number of transmitted multicast packets */
-	uint64_t	tx_mcast_pkts;
-	/* Number of transmitted broadcast packets */
-	uint64_t	tx_bcast_pkts;
-	/* Number of packets on transmit path with error */
-	uint64_t	tx_error_pkts;
-	/* Number of discarded packets on transmit path */
-	uint64_t	tx_discard_pkts;
-	/* Number of transmitted bytes for unicast traffic */
-	uint64_t	tx_ucast_bytes;
-	/* Number of transmitted bytes for multicast traffic */
-	uint64_t	tx_mcast_bytes;
-	/* Number of transmitted bytes for broadcast traffic */
-	uint64_t	tx_bcast_bytes;
-	/* Number of TPA eligible packets */
-	uint64_t	rx_tpa_eligible_pkt;
-	/* Number of TPA eligible bytes */
-	uint64_t	rx_tpa_eligible_bytes;
-	/* Number of TPA packets */
-	uint64_t	rx_tpa_pkt;
-	/* Number of TPA bytes */
-	uint64_t	rx_tpa_bytes;
-	/* Number of TPA errors */
-	uint64_t	rx_tpa_errors;
-} __rte_packed;
-
-/* Periodic Engine statistics context DMA to host. */
-/* ctx_eng_stats (size:512b/64B) */
-struct ctx_eng_stats {
-	/*
-	 * Count of data bytes into the Engine.
-	 * This includes any user supplied prefix,
-	 * but does not include any predefined
-	 * prefix data.
-	 */
-	uint64_t	eng_bytes_in;
-	/* Count of data bytes out of the Engine. */
-	uint64_t	eng_bytes_out;
-	/*
-	 * Count, in 4-byte (dword) units, of bytes
-	 * that are input as auxiliary data.
-	 * This includes the aux_cmd data.
-	 */
-	uint64_t	aux_bytes_in;
-	/*
-	 * Count, in 4-byte (dword) units, of bytes
-	 * that are output as auxiliary data.
-	 * This count is the buffer space for aux_data
-	 * output provided in the RQE, not the actual
-	 * aux_data written
-	 */
-	uint64_t	aux_bytes_out;
-	/* Count of number of commands executed. */
-	uint64_t	commands;
-	/*
-	 * Count of number of error commands.
-	 * These are the commands with a
-	 * non-zero status value.
-	 */
-	uint64_t	error_commands;
-	/*
-	 * Compression/Encryption Engine usage,
-	 * the unit is count of clock cycles
-	 */
-	uint64_t	cce_engine_usage;
-	/*
-	 * De-Compression/De-cryption Engine usage,
-	 * the unit is count of clock cycles
-	 */
-	uint64_t	cdd_engine_usage;
+	/* Original stack allocation index. */
+	uint16_t	em_index;
+	/* unused. */
+	uint16_t	unused0[3];
 } __rte_packed;
 
-/***********************
- * hwrm_stat_ctx_alloc *
- ***********************/
+/********************
+ * hwrm_tf_tcam_set *
+ ********************/
 
 
-/* hwrm_stat_ctx_alloc_input (size:256b/32B) */
-struct hwrm_stat_ctx_alloc_input {
+/* hwrm_tf_tcam_set_input (size:1024b/128B) */
+struct hwrm_tf_tcam_set_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39875,51 +42187,52 @@ struct hwrm_stat_ctx_alloc_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint32_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
 	/*
-	 * This is the address for statistic block.
-	 * > For new versions of the chip, this address should be 128B
-	 * > aligned.
-	 */
-	uint64_t	stats_dma_addr;
-	/*
-	 * The statistic block update period in ms.
-	 * e.g. 250ms, 500ms, 750ms, 1000ms.
-	 * If update_period_ms is 0, then the stats update
-	 * shall be never done and the DMA address shall not be used.
-	 * In this case, the stat block can only be read by
-	 * hwrm_stat_ctx_query command.
-	 * On Ethernet/L2 based devices:
-	 *   if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
-	 *       ctx_hw_stats_ext is used for DMA,
-	 *   else
-	 *       ctx_hw_stats is used for DMA.
+	 * Indicate device data is being sent via DMA, the device
+	 * data is packing does not change.
 	 */
-	uint32_t	update_period_ms;
+	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA     UINT32_C(0x2)
 	/*
-	 * This field is used to specify statistics context specific
-	 * configuration flags.
+	 * TCAM type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
 	 */
-	uint8_t	stat_ctx_flags;
+	uint32_t	type;
+	/* Index of TCAM entry. */
+	uint16_t	idx;
+	/* Number of bytes in the TCAM key. */
+	uint8_t	key_size;
+	/* Number of bytes in the TCAM result. */
+	uint8_t	result_size;
 	/*
-	 * When this bit is set to '1', the statistics context shall be
-	 * allocated for RoCE traffic only. In this case, traffic other
-	 * than offloaded RoCE traffic shall not be included in this
-	 * statistic context.
-	 * When this bit is set to '0', the statistics context shall be
-	 * used for network traffic or engine traffic.
+	 * Offset from which the mask bytes start in the device data
+	 * array, key offset is always 0.
 	 */
-	#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE     UINT32_C(0x1)
-	uint8_t	unused_0;
+	uint8_t	mask_offset;
+	/* Offset from which the result bytes start in the device data array. */
+	uint8_t	result_offset;
+	/* unused. */
+	uint8_t	unused0[6];
 	/*
-	 * This is the size of the structure (ctx_hw_stats or
-	 * ctx_hw_stats_ext) that the driver has allocated to be used
-	 * for the periodic DMA updates.
+	 * TCAM key located at offset 0, mask located at mask_offsec
+	 * and result at result_offsec for the device.
 	 */
-	uint16_t	stats_dma_length;
+	uint8_t	dev_data[88];
 } __rte_packed;
 
-/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
-struct hwrm_stat_ctx_alloc_output {
+/* hwrm_tf_tcam_set_output (size:128b/16B) */
+struct hwrm_tf_tcam_set_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39928,26 +42241,26 @@ struct hwrm_stat_ctx_alloc_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* This is the statistics context ID value. */
-	uint32_t	stat_ctx_id;
-	uint8_t	unused_0[3];
+	/* unused. */
+	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/**********************
- * hwrm_stat_ctx_free *
- **********************/
+/********************
+ * hwrm_tf_tcam_get *
+ ********************/
 
 
-/* hwrm_stat_ctx_free_input (size:192b/24B) */
-struct hwrm_stat_ctx_free_input {
+/* hwrm_tf_tcam_get_input (size:256b/32B) */
+struct hwrm_tf_tcam_get_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -39976,13 +42289,31 @@ struct hwrm_stat_ctx_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* ID of the statistics context that is being queried. */
-	uint32_t	stat_ctx_id;
-	uint8_t	unused_0[4];
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint32_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
+	/*
+	 * TCAM type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
+	 */
+	uint32_t	type;
+	/* Index of a TCAM entry. */
+	uint16_t	idx;
+	/* unused. */
+	uint16_t	unused0;
 } __rte_packed;
 
-/* hwrm_stat_ctx_free_output (size:128b/16B) */
-struct hwrm_stat_ctx_free_output {
+/* hwrm_tf_tcam_get_output (size:2368b/296B) */
+struct hwrm_tf_tcam_get_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -39991,26 +42322,41 @@ struct hwrm_stat_ctx_free_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* This is the statistics context ID value. */
-	uint32_t	stat_ctx_id;
-	uint8_t	unused_0[3];
+	/* Number of bytes in the TCAM key. */
+	uint8_t	key_size;
+	/* Number of bytes in the TCAM entry. */
+	uint8_t	result_size;
+	/* Offset from which the mask bytes start in the device data array. */
+	uint8_t	mask_offset;
+	/* Offset from which the result bytes start in the device data array. */
+	uint8_t	result_offset;
+	/* unused. */
+	uint8_t	unused0[4];
 	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * TCAM key located at offset 0, mask located at mask_offsec
+	 * and result at result_offsec for the device.
+	 */
+	uint8_t	dev_data[272];
+	/* unused. */
+	uint8_t	unused1[7];
+	/*
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/***********************
- * hwrm_stat_ctx_query *
- ***********************/
+/*********************
+ * hwrm_tf_tcam_move *
+ *********************/
 
 
-/* hwrm_stat_ctx_query_input (size:192b/24B) */
-struct hwrm_stat_ctx_query_input {
+/* hwrm_tf_tcam_move_input (size:1024b/128B) */
+struct hwrm_tf_tcam_move_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40039,20 +42385,33 @@ struct hwrm_stat_ctx_query_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* ID of the statistics context that is being queried. */
-	uint32_t	stat_ctx_id;
-	uint8_t	flags;
-	/*
-	 * This bit is set to 1 when request is for a counter mask,
-	 * representing the width of each of the stats counters, rather
-	 * than counters themselves.
-	 */
-	#define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK     UINT32_C(0x1)
-	uint8_t	unused_0[3];
-} __rte_packed;
-
-/* hwrm_stat_ctx_query_output (size:1408b/176B) */
-struct hwrm_stat_ctx_query_output {
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint32_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
+	/*
+	 * TCAM type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
+	 */
+	uint32_t	type;
+	/* Number of TCAM index pairs to be swapped for the device. */
+	uint16_t	count;
+	/* unused. */
+	uint16_t	unused0;
+	/* TCAM index pairs to be swapped for the device. */
+	uint16_t	idx_pairs[48];
+} __rte_packed;
+
+/* hwrm_tf_tcam_move_output (size:128b/16B) */
+struct hwrm_tf_tcam_move_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40061,64 +42420,26 @@ struct hwrm_stat_ctx_query_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Number of transmitted unicast packets */
-	uint64_t	tx_ucast_pkts;
-	/* Number of transmitted multicast packets */
-	uint64_t	tx_mcast_pkts;
-	/* Number of transmitted broadcast packets */
-	uint64_t	tx_bcast_pkts;
-	/* Number of transmitted packets with error */
-	uint64_t	tx_err_pkts;
-	/* Number of dropped packets on transmit path */
-	uint64_t	tx_drop_pkts;
-	/* Number of transmitted bytes for unicast traffic */
-	uint64_t	tx_ucast_bytes;
-	/* Number of transmitted bytes for multicast traffic */
-	uint64_t	tx_mcast_bytes;
-	/* Number of transmitted bytes for broadcast traffic */
-	uint64_t	tx_bcast_bytes;
-	/* Number of received unicast packets */
-	uint64_t	rx_ucast_pkts;
-	/* Number of received multicast packets */
-	uint64_t	rx_mcast_pkts;
-	/* Number of received broadcast packets */
-	uint64_t	rx_bcast_pkts;
-	/* Number of received packets with error */
-	uint64_t	rx_err_pkts;
-	/* Number of dropped packets on receive path */
-	uint64_t	rx_drop_pkts;
-	/* Number of received bytes for unicast traffic */
-	uint64_t	rx_ucast_bytes;
-	/* Number of received bytes for multicast traffic */
-	uint64_t	rx_mcast_bytes;
-	/* Number of received bytes for broadcast traffic */
-	uint64_t	rx_bcast_bytes;
-	/* Number of aggregated unicast packets */
-	uint64_t	rx_agg_pkts;
-	/* Number of aggregated unicast bytes */
-	uint64_t	rx_agg_bytes;
-	/* Number of aggregation events */
-	uint64_t	rx_agg_events;
-	/* Number of aborted aggregations */
-	uint64_t	rx_agg_aborts;
-	uint8_t	unused_0[7];
+	/* unused. */
+	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/***************************
- * hwrm_stat_ext_ctx_query *
- ***************************/
+/*********************
+ * hwrm_tf_tcam_free *
+ *********************/
 
 
-/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
-struct hwrm_stat_ext_ctx_query_input {
+/* hwrm_tf_tcam_free_input (size:1024b/128B) */
+struct hwrm_tf_tcam_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40147,21 +42468,33 @@ struct hwrm_stat_ext_ctx_query_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* ID of the extended statistics context that is being queried. */
-	uint32_t	stat_ctx_id;
-	uint8_t	flags;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint32_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
 	/*
-	 * This bit is set to 1 when request is for a counter mask,
-	 * representing the width of each of the stats counters, rather
-	 * than counters themselves.
+	 * TCAM type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
 	 */
-	#define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
-		UINT32_C(0x1)
-	uint8_t	unused_0[3];
+	uint32_t	type;
+	/* Number of TCAM index to be deleted for the device. */
+	uint16_t	count;
+	/* unused. */
+	uint16_t	unused0;
+	/* TCAM index list to be deleted for the device. */
+	uint16_t	idx_list[48];
 } __rte_packed;
 
-/* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */
-struct hwrm_stat_ext_ctx_query_output {
+/* hwrm_tf_tcam_free_output (size:128b/16B) */
+struct hwrm_tf_tcam_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40170,66 +42503,26 @@ struct hwrm_stat_ext_ctx_query_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Number of received unicast packets */
-	uint64_t	rx_ucast_pkts;
-	/* Number of received multicast packets */
-	uint64_t	rx_mcast_pkts;
-	/* Number of received broadcast packets */
-	uint64_t	rx_bcast_pkts;
-	/* Number of discarded packets on receive path */
-	uint64_t	rx_discard_pkts;
-	/* Number of packets on receive path with error */
-	uint64_t	rx_error_pkts;
-	/* Number of received bytes for unicast traffic */
-	uint64_t	rx_ucast_bytes;
-	/* Number of received bytes for multicast traffic */
-	uint64_t	rx_mcast_bytes;
-	/* Number of received bytes for broadcast traffic */
-	uint64_t	rx_bcast_bytes;
-	/* Number of transmitted unicast packets */
-	uint64_t	tx_ucast_pkts;
-	/* Number of transmitted multicast packets */
-	uint64_t	tx_mcast_pkts;
-	/* Number of transmitted broadcast packets */
-	uint64_t	tx_bcast_pkts;
-	/* Number of packets on transmit path with error */
-	uint64_t	tx_error_pkts;
-	/* Number of discarded packets on transmit path */
-	uint64_t	tx_discard_pkts;
-	/* Number of transmitted bytes for unicast traffic */
-	uint64_t	tx_ucast_bytes;
-	/* Number of transmitted bytes for multicast traffic */
-	uint64_t	tx_mcast_bytes;
-	/* Number of transmitted bytes for broadcast traffic */
-	uint64_t	tx_bcast_bytes;
-	/* Number of TPA eligible packets */
-	uint64_t	rx_tpa_eligible_pkt;
-	/* Number of TPA eligible bytes */
-	uint64_t	rx_tpa_eligible_bytes;
-	/* Number of TPA packets */
-	uint64_t	rx_tpa_pkt;
-	/* Number of TPA bytes */
-	uint64_t	rx_tpa_bytes;
-	/* Number of TPA errors */
-	uint64_t	rx_tpa_errors;
-	uint8_t	unused_0[7];
+	/* unused. */
+	uint8_t	unused0[7];
 	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/***************************
- * hwrm_stat_ctx_eng_query *
- ***************************/
+/**************************
+ * hwrm_tf_global_cfg_set *
+ **************************/
 
 
-/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
-struct hwrm_stat_ctx_eng_query_input {
+/* hwrm_tf_global_cfg_set_input (size:448b/56B) */
+struct hwrm_tf_global_cfg_set_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40258,13 +42551,34 @@ struct hwrm_stat_ctx_eng_query_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* ID of the statistics context that is being queried. */
-	uint32_t	stat_ctx_id;
-	uint8_t	unused_0[4];
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint32_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
+	/* Global Cfg type */
+	uint32_t	type;
+	/* Offset of the type */
+	uint32_t	offset;
+	/* Size of the data to set in bytes */
+	uint16_t	size;
+	/* unused. */
+	uint8_t	unused0[6];
+	/* Data to set */
+	uint8_t	data[8];
+	/* Mask of data to set, 0 indicates no mask */
+	uint8_t	mask[8];
 } __rte_packed;
 
-/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
-struct hwrm_stat_ctx_eng_query_output {
+/* hwrm_tf_global_cfg_set_output (size:128b/16B) */
+struct hwrm_tf_global_cfg_set_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40273,65 +42587,26 @@ struct hwrm_stat_ctx_eng_query_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/* unused. */
+	uint8_t	unused0[7];
 	/*
-	 * Count of data bytes into the Engine.
-	 * This includes any user supplied prefix,
-	 * but does not include any predefined
-	 * prefix data.
-	 */
-	uint64_t	eng_bytes_in;
-	/* Count of data bytes out of the Engine. */
-	uint64_t	eng_bytes_out;
-	/*
-	 * Count, in 4-byte (dword) units, of bytes
-	 * that are input as auxiliary data.
-	 * This includes the aux_cmd data.
-	 */
-	uint64_t	aux_bytes_in;
-	/*
-	 * Count, in 4-byte (dword) units, of bytes
-	 * that are output as auxiliary data.
-	 * This count is the buffer space for aux_data
-	 * output provided in the RQE, not the actual
-	 * aux_data written
-	 */
-	uint64_t	aux_bytes_out;
-	/* Count of number of commands executed. */
-	uint64_t	commands;
-	/*
-	 * Count of number of error commands.
-	 * These are the commands with a
-	 * non-zero status value.
-	 */
-	uint64_t	error_commands;
-	/*
-	 * Compression/Encryption Engine usage,
-	 * the unit is count of clock cycles
-	 */
-	uint64_t	cce_engine_usage;
-	/*
-	 * De-Compression/De-cryption Engine usage,
-	 * the unit is count of clock cycles
-	 */
-	uint64_t	cdd_engine_usage;
-	uint8_t	unused_0[7];
-	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * This field is used in Output records to indicate that the
+	 * output is completely written to RAM. This field should be
+	 * read as '1' to indicate that the output has been
+	 * completely written.  When writing a command completion or
+	 * response to an internal processor, the order of writes has
+	 * to be such that this field is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/***************************
- * hwrm_stat_ctx_clr_stats *
- ***************************/
+/**************************
+ * hwrm_tf_global_cfg_get *
+ **************************/
 
 
-/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
-struct hwrm_stat_ctx_clr_stats_input {
+/* hwrm_tf_global_cfg_get_input (size:320b/40B) */
+struct hwrm_tf_global_cfg_get_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40360,13 +42635,30 @@ struct hwrm_stat_ctx_clr_stats_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* ID of the statistics context that is being queried. */
-	uint32_t	stat_ctx_id;
-	uint8_t	unused_0[4];
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint32_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
+	/* Global Cfg type */
+	uint32_t	type;
+	/* Offset of the type */
+	uint32_t	offset;
+	/* Size of the data to set in bytes */
+	uint16_t	size;
+	/* unused. */
+	uint8_t	unused0[6];
 } __rte_packed;
 
-/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
-struct hwrm_stat_ctx_clr_stats_output {
+/* hwrm_tf_global_cfg_get_output (size:256b/32B) */
+struct hwrm_tf_global_cfg_get_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40375,24 +42667,21 @@ struct hwrm_stat_ctx_clr_stats_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
-	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
-	 */
-	uint8_t	valid;
+	/* Size of the data read in bytes */
+	uint16_t	size;
+	/* unused. */
+	uint8_t	unused0[6];
+	/* Data to set */
+	uint8_t	data[16];
 } __rte_packed;
 
-/********************
- * hwrm_pcie_qstats *
- ********************/
+/**********************
+ * hwrm_tf_if_tbl_get *
+ **********************/
 
 
-/* hwrm_pcie_qstats_input (size:256b/32B) */
-struct hwrm_pcie_qstats_input {
+/* hwrm_tf_if_tbl_get_input (size:256b/32B) */
+struct hwrm_tf_if_tbl_get_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40421,22 +42710,31 @@ struct hwrm_pcie_qstats_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint16_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
+	/* Size of the data to set. */
+	uint16_t	size;
 	/*
-	 * The size of PCIe statistics block in bytes.
-	 * Firmware will DMA the PCIe statistics to
-	 * the host with this field size in the response.
-	 */
-	uint16_t	pcie_stat_size;
-	uint8_t	unused_0[6];
-	/*
-	 * This is the host address where
-	 * PCIe statistics will be stored
+	 * Type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
 	 */
-	uint64_t	pcie_stat_host_addr;
+	uint32_t	type;
+	/* Index of the type to retrieve. */
+	uint32_t	index;
 } __rte_packed;
 
-/* hwrm_pcie_qstats_output (size:128b/16B) */
-struct hwrm_pcie_qstats_output {
+/* hwrm_tf_if_tbl_get_output (size:256b/32B) */
+struct hwrm_tf_if_tbl_get_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40445,62 +42743,34 @@ struct hwrm_pcie_qstats_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* The size of PCIe statistics block in bytes. */
-	uint16_t	pcie_stat_size;
-	uint8_t	unused_0[5];
+	/* Response code. */
+	uint32_t	resp_code;
+	/* Response size. */
+	uint16_t	size;
+	/* unused */
+	uint16_t	unused0;
+	/* Response data. */
+	uint8_t	data[8];
+	/* unused */
+	uint8_t	unused1[7];
 	/*
 	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
+	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/* PCIe Statistics Formats */
-/* pcie_ctx_hw_stats (size:768b/96B) */
-struct pcie_ctx_hw_stats {
-	/* Number of physical layer receiver errors */
-	uint64_t	pcie_pl_signal_integrity;
-	/* Number of DLLP CRC errors detected by Data Link Layer */
-	uint64_t	pcie_dl_signal_integrity;
-	/*
-	 * Number of TLP LCRC and sequence number errors detected
-	 * by Data Link Layer
-	 */
-	uint64_t	pcie_tl_signal_integrity;
-	/* Number of times LTSSM entered Recovery state */
-	uint64_t	pcie_link_integrity;
-	/* Report number of TLP bits that have been transmitted in Mbps */
-	uint64_t	pcie_tx_traffic_rate;
-	/* Report number of TLP bits that have been received in Mbps */
-	uint64_t	pcie_rx_traffic_rate;
-	/* Number of DLLP bytes that have been transmitted */
-	uint64_t	pcie_tx_dllp_statistics;
-	/* Number of DLLP bytes that have been received */
-	uint64_t	pcie_rx_dllp_statistics;
-	/*
-	 * Number of times spent in each phase of gen3
-	 * equalization
-	 */
-	uint64_t	pcie_equalization_time;
-	/* Records the last 16 transitions of the LTSSM */
-	uint32_t	pcie_ltssm_histogram[4];
-	/*
-	 * Record the last 8 reasons on why LTSSM transitioned
-	 * to Recovery
-	 */
-	uint64_t	pcie_recovery_histogram;
-} __rte_packed;
-
-/**********************
- * hwrm_exec_fwd_resp *
- **********************/
+/***************************
+ * hwrm_tf_if_tbl_type_set *
+ ***************************/
 
 
-/* hwrm_exec_fwd_resp_input (size:1024b/128B) */
-struct hwrm_exec_fwd_resp_input {
+/* hwrm_tf_if_tbl_set_input (size:384b/48B) */
+struct hwrm_tf_if_tbl_set_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40529,26 +42799,37 @@ struct hwrm_exec_fwd_resp_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint16_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
+	/* unused. */
+	uint8_t	unused0[2];
 	/*
-	 * This is an encapsulated request. This request should
-	 * be executed by the HWRM and the response should be
-	 * provided in the response buffer inside the encapsulated
-	 * request.
-	 */
-	uint32_t	encap_request[26];
-	/*
-	 * This value indicates the target id of the response to
-	 * the encapsulated request.
-	 * 0x0 - 0xFFF8 - Used for function ids
-	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
-	 * 0xFFFF - HWRM
+	 * Type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
 	 */
-	uint16_t	encap_resp_target_id;
-	uint8_t	unused_0[6];
+	uint32_t	type;
+	/* Index of the type to set. */
+	uint32_t	index;
+	/* Size of the data to set. */
+	uint16_t	size;
+	/* unused */
+	uint8_t	unused1[6];
+	/* Data to be set. */
+	uint8_t	data[8];
 } __rte_packed;
 
-/* hwrm_exec_fwd_resp_output (size:128b/16B) */
-struct hwrm_exec_fwd_resp_output {
+/* hwrm_tf_if_tbl_set_output (size:128b/16B) */
+struct hwrm_tf_if_tbl_set_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40557,24 +42838,26 @@ struct hwrm_exec_fwd_resp_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/* unused. */
+	uint8_t	unused0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
+	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/************************
- * hwrm_reject_fwd_resp *
- ************************/
+/*****************************
+ * hwrm_tf_tbl_type_bulk_get *
+ *****************************/
 
 
-/* hwrm_reject_fwd_resp_input (size:1024b/128B) */
-struct hwrm_reject_fwd_resp_input {
+/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
+struct hwrm_tf_tbl_type_bulk_get_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40603,26 +42886,37 @@ struct hwrm_reject_fwd_resp_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+	uint32_t	fw_session_id;
+	/* Control flags. */
+	uint16_t	flags;
+	/* Indicates the flow direction. */
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	/* If this bit set to 0, then it indicates rx flow. */
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	/* If this bit is set to 1, then it indicates that tx flow. */
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
+		HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
+	/* unused. */
+	uint8_t	unused0[2];
 	/*
-	 * This is an encapsulated request. This request should
-	 * be rejected by the HWRM and the error response should be
-	 * provided in the response buffer inside the encapsulated
-	 * request.
+	 * Type of the resource, defined globally in the
+	 * hwrm_tf_resc_type enum.
 	 */
-	uint32_t	encap_request[26];
-	/*
-	 * This value indicates the target id of the response to
-	 * the encapsulated request.
-	 * 0x0 - 0xFFF8 - Used for function ids
-	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
-	 * 0xFFFF - HWRM
-	 */
-	uint16_t	encap_resp_target_id;
-	uint8_t	unused_0[6];
+	uint32_t	type;
+	/* Starting index of the type to retrieve. */
+	uint32_t	start_index;
+	/* Number of entries to retrieve. */
+	uint32_t	num_entries;
+	/* Number of entries to retrieve. */
+	uint32_t	unused1;
+	/* Host memory where data will be stored. */
+	uint64_t	host_addr;
 } __rte_packed;
 
-/* hwrm_reject_fwd_resp_output (size:128b/16B) */
-struct hwrm_reject_fwd_resp_output {
+/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
+struct hwrm_tf_tbl_type_bulk_get_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40631,24 +42925,30 @@ struct hwrm_reject_fwd_resp_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/* Response code. */
+	uint32_t	resp_code;
+	/* Response size. */
+	uint16_t	size;
+	/* unused */
+	uint8_t	unused0;
 	/*
 	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
+	 * is completely written to RAM. This field should be read as '1'
 	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * When writing a command completion or response to an internal
+	 * processor, the order of writes has to be such that this field
+	 * is written last.
 	 */
 	uint8_t	valid;
 } __rte_packed;
 
-/*****************
- * hwrm_fwd_resp *
- *****************/
+/******************************
+ * hwrm_tunnel_dst_port_query *
+ ******************************/
 
 
-/* hwrm_fwd_resp_input (size:1024b/128B) */
-struct hwrm_fwd_resp_input {
+/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
+struct hwrm_tunnel_dst_port_query_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40677,41 +42977,33 @@ struct hwrm_fwd_resp_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/*
-	 * This value indicates the target id of the encapsulated
-	 * response.
-	 * 0x0 - 0xFFF8 - Used for function ids
-	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
-	 * 0xFFFF - HWRM
-	 */
-	uint16_t	encap_resp_target_id;
-	/*
-	 * This value indicates the completion ring the encapsulated
-	 * response will be optionally completed on.  If the value is
-	 * -1, then no CR completion shall be generated for the
-	 * encapsulated response. Any other value must be a
-	 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
-	 * is provided, then a CR completion shall be generated for
-	 * the encapsulated response.
-	 */
-	uint16_t	encap_resp_cmpl_ring;
-	/* This field indicates the length of encapsulated response. */
-	uint16_t	encap_resp_len;
-	uint8_t	unused_0;
-	uint8_t	unused_1;
-	/*
-	 * This is the host address where the encapsulated response
-	 * will be written.
-	 * This area must be 16B aligned and must be cleared to zero
-	 * before the original request is made.
-	 */
-	uint64_t	encap_resp_addr;
-	/* This is an encapsulated response. */
-	uint32_t	encap_resp[24];
+	/* Tunnel Type. */
+	uint8_t	tunnel_type;
+	/* Virtual eXtensible Local Area Network (VXLAN) */
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
+		UINT32_C(0x1)
+	/* Generic Network Virtualization Encapsulation (Geneve) */
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
+		UINT32_C(0x5)
+	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
+	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
+		HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+	uint8_t	unused_0[7];
 } __rte_packed;
 
-/* hwrm_fwd_resp_output (size:128b/16B) */
-struct hwrm_fwd_resp_output {
+/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
+struct hwrm_tunnel_dst_port_query_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40720,7 +43012,25 @@ struct hwrm_fwd_resp_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/*
+	 * This field represents the identifier of L4 destination port
+	 * used for the given tunnel type. This field is valid for
+	 * specific tunnel types that use layer 4 (e.g. UDP)
+	 * transports for tunneling.
+	 */
+	uint16_t	tunnel_dst_port_id;
+	/*
+	 * This field represents the value of L4 destination port
+	 * identified by tunnel_dst_port_id. This field is valid for
+	 * specific tunnel types that use layer 4 (e.g. UDP)
+	 * transports for tunneling.
+	 * This field is in network byte order.
+	 *
+	 * A value of 0 means that the destination port is not
+	 * configured.
+	 */
+	uint16_t	tunnel_dst_port_val;
+	uint8_t	unused_0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -40731,13 +43041,13 @@ struct hwrm_fwd_resp_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*****************************
- * hwrm_fwd_async_event_cmpl *
- *****************************/
+/******************************
+ * hwrm_tunnel_dst_port_alloc *
+ ******************************/
 
 
-/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
-struct hwrm_fwd_async_event_cmpl_input {
+/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
+struct hwrm_tunnel_dst_port_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40766,22 +43076,45 @@ struct hwrm_fwd_async_event_cmpl_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Tunnel Type. */
+	uint8_t	tunnel_type;
+	/* Virtual eXtensible Local Area Network (VXLAN) */
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+		UINT32_C(0x1)
+	/* Generic Network Virtualization Encapsulation (Geneve) */
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+		UINT32_C(0x5)
+	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
+	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+		HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+	uint8_t	unused_0;
 	/*
-	 * This value indicates the target id of the encapsulated
-	 * asynchronous event.
-	 * 0x0 - 0xFFF8 - Used for function ids
-	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
-	 * 0xFFFF - Broadcast to all children VFs (only applicable when
-	 * a PF is the requester)
+	 * This field represents the value of L4 destination port used
+	 * for the given tunnel type. This field is valid for
+	 * specific tunnel types that use layer 4 (e.g. UDP)
+	 * transports for tunneling.
+	 *
+	 * This field is in network byte order.
+	 *
+	 * A value of 0 shall fail the command.
 	 */
-	uint16_t	encap_async_event_target_id;
-	uint8_t	unused_0[6];
-	/* This is an encapsulated asynchronous event completion. */
-	uint32_t	encap_async_event_cmpl[4];
+	uint16_t	tunnel_dst_port_val;
+	uint8_t	unused_1[4];
 } __rte_packed;
 
-/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
-struct hwrm_fwd_async_event_cmpl_output {
+/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
+struct hwrm_tunnel_dst_port_alloc_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40790,7 +43123,12 @@ struct hwrm_fwd_async_event_cmpl_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/*
+	 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
+	 * types that has l4 destination port parameters.
+	 */
+	uint16_t	tunnel_dst_port_id;
+	uint8_t	unused_0[5];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -40801,13 +43139,13 @@ struct hwrm_fwd_async_event_cmpl_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**************************
- * hwrm_nvm_raw_write_blk *
- **************************/
+/*****************************
+ * hwrm_tunnel_dst_port_free *
+ *****************************/
 
 
-/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
-struct hwrm_nvm_raw_write_blk_input {
+/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
+struct hwrm_tunnel_dst_port_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40836,22 +43174,39 @@ struct hwrm_nvm_raw_write_blk_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* Tunnel Type. */
+	uint8_t	tunnel_type;
+	/* Virtual eXtensible Local Area Network (VXLAN) */
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
+		UINT32_C(0x1)
+	/* Generic Network Virtualization Encapsulation (Geneve) */
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
+		UINT32_C(0x5)
+	/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+		UINT32_C(0x9)
+	/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+		UINT32_C(0xa)
+	/* Use fixed layer 2 ether type of 0xFFFF */
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+		UINT32_C(0xb)
+	/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+		UINT32_C(0xc)
+	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
+		HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+	uint8_t	unused_0;
 	/*
-	 * 64-bit Host Source Address.
-	 * This is the location of the source data to be written.
-	 */
-	uint64_t	host_src_addr;
-	/*
-	 * 32-bit Destination Address.
-	 * This is the NVRAM byte-offset where the source data will be written to.
+	 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
+	 * types that has l4 destination port parameters.
 	 */
-	uint32_t	dest_addr;
-	/* Length of data to be written, in bytes. */
-	uint32_t	len;
+	uint16_t	tunnel_dst_port_id;
+	uint8_t	unused_1[4];
 } __rte_packed;
 
-/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
-struct hwrm_nvm_raw_write_blk_output {
+/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
+struct hwrm_tunnel_dst_port_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40860,7 +43215,7 @@ struct hwrm_nvm_raw_write_blk_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	uint8_t	unused_1[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -40871,84 +43226,157 @@ struct hwrm_nvm_raw_write_blk_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*****************
- * hwrm_nvm_read *
- *****************/
+/* Periodic statistics context DMA to host. */
+/* ctx_hw_stats (size:1280b/160B) */
+struct ctx_hw_stats {
+	/* Number of received unicast packets */
+	uint64_t	rx_ucast_pkts;
+	/* Number of received multicast packets */
+	uint64_t	rx_mcast_pkts;
+	/* Number of received broadcast packets */
+	uint64_t	rx_bcast_pkts;
+	/* Number of discarded packets on receive path */
+	uint64_t	rx_discard_pkts;
+	/* Number of packets on receive path with error */
+	uint64_t	rx_error_pkts;
+	/* Number of received bytes for unicast traffic */
+	uint64_t	rx_ucast_bytes;
+	/* Number of received bytes for multicast traffic */
+	uint64_t	rx_mcast_bytes;
+	/* Number of received bytes for broadcast traffic */
+	uint64_t	rx_bcast_bytes;
+	/* Number of transmitted unicast packets */
+	uint64_t	tx_ucast_pkts;
+	/* Number of transmitted multicast packets */
+	uint64_t	tx_mcast_pkts;
+	/* Number of transmitted broadcast packets */
+	uint64_t	tx_bcast_pkts;
+	/* Number of packets on transmit path with error */
+	uint64_t	tx_error_pkts;
+	/* Number of discarded packets on transmit path */
+	uint64_t	tx_discard_pkts;
+	/* Number of transmitted bytes for unicast traffic */
+	uint64_t	tx_ucast_bytes;
+	/* Number of transmitted bytes for multicast traffic */
+	uint64_t	tx_mcast_bytes;
+	/* Number of transmitted bytes for broadcast traffic */
+	uint64_t	tx_bcast_bytes;
+	/* Number of TPA packets */
+	uint64_t	tpa_pkts;
+	/* Number of TPA bytes */
+	uint64_t	tpa_bytes;
+	/* Number of TPA events */
+	uint64_t	tpa_events;
+	/* Number of TPA aborts */
+	uint64_t	tpa_aborts;
+} __rte_packed;
 
+/*
+ * Extended periodic statistics context DMA to host. On cards that
+ * support TPA v2, additional TPA related stats exist and can be retrieved
+ * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
+ */
+/* ctx_hw_stats_ext (size:1408b/176B) */
+struct ctx_hw_stats_ext {
+	/* Number of received unicast packets */
+	uint64_t	rx_ucast_pkts;
+	/* Number of received multicast packets */
+	uint64_t	rx_mcast_pkts;
+	/* Number of received broadcast packets */
+	uint64_t	rx_bcast_pkts;
+	/* Number of discarded packets on receive path */
+	uint64_t	rx_discard_pkts;
+	/* Number of packets on receive path with error */
+	uint64_t	rx_error_pkts;
+	/* Number of received bytes for unicast traffic */
+	uint64_t	rx_ucast_bytes;
+	/* Number of received bytes for multicast traffic */
+	uint64_t	rx_mcast_bytes;
+	/* Number of received bytes for broadcast traffic */
+	uint64_t	rx_bcast_bytes;
+	/* Number of transmitted unicast packets */
+	uint64_t	tx_ucast_pkts;
+	/* Number of transmitted multicast packets */
+	uint64_t	tx_mcast_pkts;
+	/* Number of transmitted broadcast packets */
+	uint64_t	tx_bcast_pkts;
+	/* Number of packets on transmit path with error */
+	uint64_t	tx_error_pkts;
+	/* Number of discarded packets on transmit path */
+	uint64_t	tx_discard_pkts;
+	/* Number of transmitted bytes for unicast traffic */
+	uint64_t	tx_ucast_bytes;
+	/* Number of transmitted bytes for multicast traffic */
+	uint64_t	tx_mcast_bytes;
+	/* Number of transmitted bytes for broadcast traffic */
+	uint64_t	tx_bcast_bytes;
+	/* Number of TPA eligible packets */
+	uint64_t	rx_tpa_eligible_pkt;
+	/* Number of TPA eligible bytes */
+	uint64_t	rx_tpa_eligible_bytes;
+	/* Number of TPA packets */
+	uint64_t	rx_tpa_pkt;
+	/* Number of TPA bytes */
+	uint64_t	rx_tpa_bytes;
+	/* Number of TPA errors */
+	uint64_t	rx_tpa_errors;
+	/* Number of TPA events */
+	uint64_t	rx_tpa_events;
+} __rte_packed;
 
-/* hwrm_nvm_read_input (size:320b/40B) */
-struct hwrm_nvm_read_input {
-	/* The HWRM command request type. */
-	uint16_t	req_type;
+/* Periodic Engine statistics context DMA to host. */
+/* ctx_eng_stats (size:512b/64B) */
+struct ctx_eng_stats {
 	/*
-	 * The completion ring to send the completion event on. This should
-	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 * Count of data bytes into the Engine.
+	 * This includes any user supplied prefix,
+	 * but does not include any predefined
+	 * prefix data.
 	 */
-	uint16_t	cmpl_ring;
+	uint64_t	eng_bytes_in;
+	/* Count of data bytes out of the Engine. */
+	uint64_t	eng_bytes_out;
 	/*
-	 * The sequence ID is used by the driver for tracking multiple
-	 * commands. This ID is treated as opaque data by the firmware and
-	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 * Count, in 4-byte (dword) units, of bytes
+	 * that are input as auxiliary data.
+	 * This includes the aux_cmd data.
 	 */
-	uint16_t	seq_id;
+	uint64_t	aux_bytes_in;
 	/*
-	 * The target ID of the command:
-	 * * 0x0-0xFFF8 - The function ID
-	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
-	 * * 0xFFFD - Reserved for user-space HWRM interface
-	 * * 0xFFFF - HWRM
+	 * Count, in 4-byte (dword) units, of bytes
+	 * that are output as auxiliary data.
+	 * This count is the buffer space for aux_data
+	 * output provided in the RQE, not the actual
+	 * aux_data written
 	 */
-	uint16_t	target_id;
+	uint64_t	aux_bytes_out;
+	/* Count of number of commands executed. */
+	uint64_t	commands;
 	/*
-	 * A physical address pointer pointing to a host buffer that the
-	 * command's response data will be written. This can be either a host
-	 * physical address (HPA) or a guest physical address (GPA) and must
-	 * point to a physically contiguous block of memory.
+	 * Count of number of error commands.
+	 * These are the commands with a
+	 * non-zero status value.
 	 */
-	uint64_t	resp_addr;
+	uint64_t	error_commands;
 	/*
-	 * 64-bit Host Destination Address.
-	 * This is the host address where the data will be written to.
+	 * Compression/Encryption Engine usage,
+	 * the unit is count of clock cycles
 	 */
-	uint64_t	host_dest_addr;
-	/* The 0-based index of the directory entry. */
-	uint16_t	dir_idx;
-	uint8_t	unused_0[2];
-	/* The NVRAM byte-offset to read from. */
-	uint32_t	offset;
-	/* The length of the data to be read, in bytes. */
-	uint32_t	len;
-	uint8_t	unused_1[4];
-} __rte_packed;
-
-/* hwrm_nvm_read_output (size:128b/16B) */
-struct hwrm_nvm_read_output {
-	/* The specific error status for the command. */
-	uint16_t	error_code;
-	/* The HWRM command request type. */
-	uint16_t	req_type;
-	/* The sequence ID from the original command. */
-	uint16_t	seq_id;
-	/* The length of the response data in number of bytes. */
-	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	uint64_t	cce_engine_usage;
 	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
+	 * De-Compression/De-cryption Engine usage,
+	 * the unit is count of clock cycles
 	 */
-	uint8_t	valid;
+	uint64_t	cdd_engine_usage;
 } __rte_packed;
 
-/*********************
- * hwrm_nvm_raw_dump *
- *********************/
+/***********************
+ * hwrm_stat_ctx_alloc *
+ ***********************/
 
 
-/* hwrm_nvm_raw_dump_input (size:256b/32B) */
-struct hwrm_nvm_raw_dump_input {
+/* hwrm_stat_ctx_alloc_input (size:256b/32B) */
+struct hwrm_stat_ctx_alloc_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -40978,18 +43406,50 @@ struct hwrm_nvm_raw_dump_input {
 	 */
 	uint64_t	resp_addr;
 	/*
-	 * 64-bit Host Destination Address.
-	 * This is the host address where the data will be written to.
+	 * This is the address for statistic block.
+	 * > For new versions of the chip, this address should be 128B
+	 * > aligned.
 	 */
-	uint64_t	host_dest_addr;
-	/* 32-bit NVRAM byte-offset to read from. */
-	uint32_t	offset;
-	/* Total length of NVRAM contents to be read, in bytes. */
-	uint32_t	len;
+	uint64_t	stats_dma_addr;
+	/*
+	 * The statistic block update period in ms.
+	 * e.g. 250ms, 500ms, 750ms, 1000ms.
+	 * If update_period_ms is 0, then the stats update
+	 * shall be never done and the DMA address shall not be used.
+	 * In this case, the stat block can only be read by
+	 * hwrm_stat_ctx_query command.
+	 * On Ethernet/L2 based devices:
+	 *   if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
+	 *       ctx_hw_stats_ext is used for DMA,
+	 *   else
+	 *       ctx_hw_stats is used for DMA.
+	 */
+	uint32_t	update_period_ms;
+	/*
+	 * This field is used to specify statistics context specific
+	 * configuration flags.
+	 */
+	uint8_t	stat_ctx_flags;
+	/*
+	 * When this bit is set to '1', the statistics context shall be
+	 * allocated for RoCE traffic only. In this case, traffic other
+	 * than offloaded RoCE traffic shall not be included in this
+	 * statistic context.
+	 * When this bit is set to '0', the statistics context shall be
+	 * used for network traffic or engine traffic.
+	 */
+	#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE     UINT32_C(0x1)
+	uint8_t	unused_0;
+	/*
+	 * This is the size of the structure (ctx_hw_stats or
+	 * ctx_hw_stats_ext) that the driver has allocated to be used
+	 * for the periodic DMA updates.
+	 */
+	uint16_t	stats_dma_length;
 } __rte_packed;
 
-/* hwrm_nvm_raw_dump_output (size:128b/16B) */
-struct hwrm_nvm_raw_dump_output {
+/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
+struct hwrm_stat_ctx_alloc_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -40998,7 +43458,9 @@ struct hwrm_nvm_raw_dump_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/* This is the statistics context ID value. */
+	uint32_t	stat_ctx_id;
+	uint8_t	unused_0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -41009,13 +43471,13 @@ struct hwrm_nvm_raw_dump_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/****************************
- * hwrm_nvm_get_dir_entries *
- ****************************/
+/**********************
+ * hwrm_stat_ctx_free *
+ **********************/
 
 
-/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
-struct hwrm_nvm_get_dir_entries_input {
+/* hwrm_stat_ctx_free_input (size:192b/24B) */
+struct hwrm_stat_ctx_free_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41044,15 +43506,13 @@ struct hwrm_nvm_get_dir_entries_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/*
-	 * 64-bit Host Destination Address.
-	 * This is the host address where the directory will be written.
-	 */
-	uint64_t	host_dest_addr;
+	/* ID of the statistics context that is being queried. */
+	uint32_t	stat_ctx_id;
+	uint8_t	unused_0[4];
 } __rte_packed;
 
-/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
-struct hwrm_nvm_get_dir_entries_output {
+/* hwrm_stat_ctx_free_output (size:128b/16B) */
+struct hwrm_stat_ctx_free_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41061,7 +43521,9 @@ struct hwrm_nvm_get_dir_entries_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/* This is the statistics context ID value. */
+	uint32_t	stat_ctx_id;
+	uint8_t	unused_0[3];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -41072,13 +43534,13 @@ struct hwrm_nvm_get_dir_entries_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*************************
- * hwrm_nvm_get_dir_info *
- *************************/
+/***********************
+ * hwrm_stat_ctx_query *
+ ***********************/
 
 
-/* hwrm_nvm_get_dir_info_input (size:128b/16B) */
-struct hwrm_nvm_get_dir_info_input {
+/* hwrm_stat_ctx_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_query_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41107,10 +43569,20 @@ struct hwrm_nvm_get_dir_info_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-} __rte_packed;
-
-/* hwrm_nvm_get_dir_info_output (size:192b/24B) */
-struct hwrm_nvm_get_dir_info_output {
+	/* ID of the statistics context that is being queried. */
+	uint32_t	stat_ctx_id;
+	uint8_t	flags;
+	/*
+	 * This bit is set to 1 when request is for a counter mask,
+	 * representing the width of each of the stats counters, rather
+	 * than counters themselves.
+	 */
+	#define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK     UINT32_C(0x1)
+	uint8_t	unused_0[3];
+} __rte_packed;
+
+/* hwrm_stat_ctx_query_output (size:1408b/176B) */
+struct hwrm_stat_ctx_query_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41119,10 +43591,46 @@ struct hwrm_nvm_get_dir_info_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Number of directory entries in the directory. */
-	uint32_t	entries;
-	/* Size of each directory entry, in bytes. */
-	uint32_t	entry_length;
+	/* Number of transmitted unicast packets */
+	uint64_t	tx_ucast_pkts;
+	/* Number of transmitted multicast packets */
+	uint64_t	tx_mcast_pkts;
+	/* Number of transmitted broadcast packets */
+	uint64_t	tx_bcast_pkts;
+	/* Number of packets discarded in transmit path */
+	uint64_t	tx_discard_pkts;
+	/* Number of packets in transmit path with error */
+	uint64_t	tx_error_pkts;
+	/* Number of transmitted bytes for unicast traffic */
+	uint64_t	tx_ucast_bytes;
+	/* Number of transmitted bytes for multicast traffic */
+	uint64_t	tx_mcast_bytes;
+	/* Number of transmitted bytes for broadcast traffic */
+	uint64_t	tx_bcast_bytes;
+	/* Number of received unicast packets */
+	uint64_t	rx_ucast_pkts;
+	/* Number of received multicast packets */
+	uint64_t	rx_mcast_pkts;
+	/* Number of received broadcast packets */
+	uint64_t	rx_bcast_pkts;
+	/* Number of packets discarded in receive path */
+	uint64_t	rx_discard_pkts;
+	/* Number of packets in receive path with errors */
+	uint64_t	rx_error_pkts;
+	/* Number of received bytes for unicast traffic */
+	uint64_t	rx_ucast_bytes;
+	/* Number of received bytes for multicast traffic */
+	uint64_t	rx_mcast_bytes;
+	/* Number of received bytes for broadcast traffic */
+	uint64_t	rx_bcast_bytes;
+	/* Number of aggregated unicast packets */
+	uint64_t	rx_agg_pkts;
+	/* Number of aggregated unicast bytes */
+	uint64_t	rx_agg_bytes;
+	/* Number of aggregation events */
+	uint64_t	rx_agg_events;
+	/* Number of aborted aggregations */
+	uint64_t	rx_agg_aborts;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -41134,13 +43642,13 @@ struct hwrm_nvm_get_dir_info_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/******************
- * hwrm_nvm_write *
- ******************/
+/***************************
+ * hwrm_stat_ext_ctx_query *
+ ***************************/
 
 
-/* hwrm_nvm_write_input (size:384b/48B) */
-struct hwrm_nvm_write_input {
+/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
+struct hwrm_stat_ext_ctx_query_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41169,49 +43677,21 @@ struct hwrm_nvm_write_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/* ID of the extended statistics context that is being queried. */
+	uint32_t	stat_ctx_id;
+	uint8_t	flags;
 	/*
-	 * 64-bit Host Source Address.
-	 * This is where the source data is.
-	 */
-	uint64_t	host_src_addr;
-	/* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
-	uint16_t	dir_type;
-	/*
-	 * Directory ordinal.
-	 * The 0-based instance of the combined Directory Entry Type and Extension.
-	 */
-	uint16_t	dir_ordinal;
-	/* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
-	uint16_t	dir_ext;
-	/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
-	uint16_t	dir_attr;
-	/*
-	 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
-	 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
-	 */
-	uint32_t	dir_data_length;
-	/* Option. */
-	uint16_t	option;
-	uint16_t	flags;
-	/*
-	 * When this bit is '1', the original active image
-	 * will not be removed. TBD: what purpose is this?
+	 * This bit is set to 1 when request is for a counter mask,
+	 * representing the width of each of the stats counters, rather
+	 * than counters themselves.
 	 */
-	#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
+	#define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
 		UINT32_C(0x1)
-	/*
-	 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
-	 * If this value is less than the specified data length, it will be ignored.
-	 * The response will contain the actual allocated item length, which may be greater than the requested item length.
-	 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
-	 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
-	 */
-	uint32_t	dir_item_length;
-	uint32_t	unused_0;
+	uint8_t	unused_0[3];
 } __rte_packed;
 
-/* hwrm_nvm_write_output (size:128b/16B) */
-struct hwrm_nvm_write_output {
+/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
+struct hwrm_stat_ext_ctx_query_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41220,14 +43700,51 @@ struct hwrm_nvm_write_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/*
-	 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
-	 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
-	 */
-	uint32_t	dir_item_length;
-	/* The directory index of the created or modified item. */
-	uint16_t	dir_idx;
-	uint8_t	unused_0;
+	/* Number of received unicast packets */
+	uint64_t	rx_ucast_pkts;
+	/* Number of received multicast packets */
+	uint64_t	rx_mcast_pkts;
+	/* Number of received broadcast packets */
+	uint64_t	rx_bcast_pkts;
+	/* Number of discarded packets on receive path */
+	uint64_t	rx_discard_pkts;
+	/* Number of packets on receive path with error */
+	uint64_t	rx_error_pkts;
+	/* Number of received bytes for unicast traffic */
+	uint64_t	rx_ucast_bytes;
+	/* Number of received bytes for multicast traffic */
+	uint64_t	rx_mcast_bytes;
+	/* Number of received bytes for broadcast traffic */
+	uint64_t	rx_bcast_bytes;
+	/* Number of transmitted unicast packets */
+	uint64_t	tx_ucast_pkts;
+	/* Number of transmitted multicast packets */
+	uint64_t	tx_mcast_pkts;
+	/* Number of transmitted broadcast packets */
+	uint64_t	tx_bcast_pkts;
+	/* Number of packets on transmit path with error */
+	uint64_t	tx_error_pkts;
+	/* Number of discarded packets on transmit path */
+	uint64_t	tx_discard_pkts;
+	/* Number of transmitted bytes for unicast traffic */
+	uint64_t	tx_ucast_bytes;
+	/* Number of transmitted bytes for multicast traffic */
+	uint64_t	tx_mcast_bytes;
+	/* Number of transmitted bytes for broadcast traffic */
+	uint64_t	tx_bcast_bytes;
+	/* Number of TPA eligible packets */
+	uint64_t	rx_tpa_eligible_pkt;
+	/* Number of TPA eligible bytes */
+	uint64_t	rx_tpa_eligible_bytes;
+	/* Number of TPA packets */
+	uint64_t	rx_tpa_pkt;
+	/* Number of TPA bytes */
+	uint64_t	rx_tpa_bytes;
+	/* Number of TPA errors */
+	uint64_t	rx_tpa_errors;
+	/* Number of TPA events */
+	uint64_t	rx_tpa_events;
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -41238,31 +43755,13 @@ struct hwrm_nvm_write_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/* hwrm_nvm_write_cmd_err (size:64b/8B) */
-struct hwrm_nvm_write_cmd_err {
-	/*
-	 * command specific error codes that goes to
-	 * the cmd_err field in Common HWRM Error Response.
-	 */
-	uint8_t	code;
-	/* Unknown error */
-	#define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN  UINT32_C(0x0)
-	/* Unable to complete operation due to fragmentation */
-	#define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
-	/* nvm is completely full. */
-	#define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
-	#define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
-		HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
-	uint8_t	unused_0[7];
-} __rte_packed;
-
-/*******************
- * hwrm_nvm_modify *
- *******************/
+/***************************
+ * hwrm_stat_ctx_eng_query *
+ ***************************/
 
 
-/* hwrm_nvm_modify_input (size:320b/40B) */
-struct hwrm_nvm_modify_input {
+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_eng_query_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41291,42 +43790,13 @@ struct hwrm_nvm_modify_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/*
-	 * 64-bit Host Source Address.
-	 * This is where the modified data is.
-	 */
-	uint64_t	host_src_addr;
-	/* 16-bit directory entry index. */
-	uint16_t	dir_idx;
-	uint16_t	flags;
-	/*
-	 * This flag indicates the sender wants to modify a continuous NVRAM
-	 * area using a batch of this HWRM requests. The offset of a request
-	 * must be continuous to the end of previous request's. Firmware does
-	 * not update the directory entry until receiving the last request,
-	 * which is indicated by the batch_last flag.
-	 * This flag is set usually when a sender does not have a block of
-	 * memory that is big enough to hold the entire NVRAM data for send
-	 * at one time.
-	 */
-	#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE     UINT32_C(0x1)
-	/*
-	 * This flag can be used only when the batch_mode flag is set.
-	 * It indicates this request is the last of batch requests.
-	 */
-	#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST     UINT32_C(0x2)
-	/* 32-bit NVRAM byte-offset to modify content from. */
-	uint32_t	offset;
-	/*
-	 * Length of data to be modified, in bytes. The length shall
-	 * be non-zero.
-	 */
-	uint32_t	len;
-	uint8_t	unused_1[4];
+	/* ID of the statistics context that is being queried. */
+	uint32_t	stat_ctx_id;
+	uint8_t	unused_0[4];
 } __rte_packed;
 
-/* hwrm_nvm_modify_output (size:128b/16B) */
-struct hwrm_nvm_modify_output {
+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
+struct hwrm_stat_ctx_eng_query_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41335,6 +43805,47 @@ struct hwrm_nvm_modify_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/*
+	 * Count of data bytes into the Engine.
+	 * This includes any user supplied prefix,
+	 * but does not include any predefined
+	 * prefix data.
+	 */
+	uint64_t	eng_bytes_in;
+	/* Count of data bytes out of the Engine. */
+	uint64_t	eng_bytes_out;
+	/*
+	 * Count, in 4-byte (dword) units, of bytes
+	 * that are input as auxiliary data.
+	 * This includes the aux_cmd data.
+	 */
+	uint64_t	aux_bytes_in;
+	/*
+	 * Count, in 4-byte (dword) units, of bytes
+	 * that are output as auxiliary data.
+	 * This count is the buffer space for aux_data
+	 * output provided in the RQE, not the actual
+	 * aux_data written
+	 */
+	uint64_t	aux_bytes_out;
+	/* Count of number of commands executed. */
+	uint64_t	commands;
+	/*
+	 * Count of number of error commands.
+	 * These are the commands with a
+	 * non-zero status value.
+	 */
+	uint64_t	error_commands;
+	/*
+	 * Compression/Encryption Engine usage,
+	 * the unit is count of clock cycles
+	 */
+	uint64_t	cce_engine_usage;
+	/*
+	 * De-Compression/De-cryption Engine usage,
+	 * the unit is count of clock cycles
+	 */
+	uint64_t	cdd_engine_usage;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -41347,12 +43858,12 @@ struct hwrm_nvm_modify_output {
 } __rte_packed;
 
 /***************************
- * hwrm_nvm_find_dir_entry *
+ * hwrm_stat_ctx_clr_stats *
  ***************************/
 
 
-/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
-struct hwrm_nvm_find_dir_entry_input {
+/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
+struct hwrm_stat_ctx_clr_stats_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41381,42 +43892,13 @@ struct hwrm_nvm_find_dir_entry_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	enables;
-	/*
-	 * This bit must be '1' for the dir_idx_valid field to be
-	 * configured.
-	 */
-	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
-		UINT32_C(0x1)
-	/* Directory Entry Index */
-	uint16_t	dir_idx;
-	/* Directory Entry (Image) Type */
-	uint16_t	dir_type;
-	/*
-	 * Directory ordinal.
-	 * The instance of this Directory Type
-	 */
-	uint16_t	dir_ordinal;
-	/* The Directory Entry Extension flags. */
-	uint16_t	dir_ext;
-	/* This value indicates the search option using dir_ordinal. */
-	uint8_t	opt_ordinal;
-	/* This value indicates the search option using dir_ordinal. */
-	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
-	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
-	/* Equal to specified ordinal value. */
-	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ    UINT32_C(0x0)
-	/* Greater than or equal to specified ordinal value */
-	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE    UINT32_C(0x1)
-	/* Greater than specified ordinal value */
-	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT    UINT32_C(0x2)
-	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
-		HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
-	uint8_t	unused_0[3];
+	/* ID of the statistics context that is being queried. */
+	uint32_t	stat_ctx_id;
+	uint8_t	unused_0[4];
 } __rte_packed;
 
-/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
-struct hwrm_nvm_find_dir_entry_output {
+/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
+struct hwrm_stat_ctx_clr_stats_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41425,19 +43907,6 @@ struct hwrm_nvm_find_dir_entry_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Allocated NVRAM for this directory entry, in bytes. */
-	uint32_t	dir_item_length;
-	/* Size of the stored data for this directory entry, in bytes. */
-	uint32_t	dir_data_length;
-	/*
-	 * Firmware version.
-	 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
-	 */
-	uint32_t	fw_ver;
-	/* Directory ordinal. */
-	uint16_t	dir_ordinal;
-	/* Directory Entry Index */
-	uint16_t	dir_idx;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -41449,13 +43918,13 @@ struct hwrm_nvm_find_dir_entry_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/****************************
- * hwrm_nvm_erase_dir_entry *
- ****************************/
+/********************
+ * hwrm_pcie_qstats *
+ ********************/
 
 
-/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
-struct hwrm_nvm_erase_dir_entry_input {
+/* hwrm_pcie_qstats_input (size:256b/32B) */
+struct hwrm_pcie_qstats_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41484,13 +43953,22 @@ struct hwrm_nvm_erase_dir_entry_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Directory Entry Index */
-	uint16_t	dir_idx;
+	/*
+	 * The size of PCIe statistics block in bytes.
+	 * Firmware will DMA the PCIe statistics to
+	 * the host with this field size in the response.
+	 */
+	uint16_t	pcie_stat_size;
 	uint8_t	unused_0[6];
+	/*
+	 * This is the host address where
+	 * PCIe statistics will be stored
+	 */
+	uint64_t	pcie_stat_host_addr;
 } __rte_packed;
 
-/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
-struct hwrm_nvm_erase_dir_entry_output {
+/* hwrm_pcie_qstats_output (size:128b/16B) */
+struct hwrm_pcie_qstats_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41499,7 +43977,9 @@ struct hwrm_nvm_erase_dir_entry_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	unused_0[7];
+	/* The size of PCIe statistics block in bytes. */
+	uint16_t	pcie_stat_size;
+	uint8_t	unused_0[5];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -41510,13 +43990,49 @@ struct hwrm_nvm_erase_dir_entry_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*************************
- * hwrm_nvm_get_dev_info *
- *************************/
+/* PCIe Statistics Formats */
+/* pcie_ctx_hw_stats (size:768b/96B) */
+struct pcie_ctx_hw_stats {
+	/* Number of physical layer receiver errors */
+	uint64_t	pcie_pl_signal_integrity;
+	/* Number of DLLP CRC errors detected by Data Link Layer */
+	uint64_t	pcie_dl_signal_integrity;
+	/*
+	 * Number of TLP LCRC and sequence number errors detected
+	 * by Data Link Layer
+	 */
+	uint64_t	pcie_tl_signal_integrity;
+	/* Number of times LTSSM entered Recovery state */
+	uint64_t	pcie_link_integrity;
+	/* Report number of TLP bits that have been transmitted in Mbps */
+	uint64_t	pcie_tx_traffic_rate;
+	/* Report number of TLP bits that have been received in Mbps */
+	uint64_t	pcie_rx_traffic_rate;
+	/* Number of DLLP bytes that have been transmitted */
+	uint64_t	pcie_tx_dllp_statistics;
+	/* Number of DLLP bytes that have been received */
+	uint64_t	pcie_rx_dllp_statistics;
+	/*
+	 * Number of times spent in each phase of gen3
+	 * equalization
+	 */
+	uint64_t	pcie_equalization_time;
+	/* Records the last 16 transitions of the LTSSM */
+	uint32_t	pcie_ltssm_histogram[4];
+	/*
+	 * Record the last 8 reasons on why LTSSM transitioned
+	 * to Recovery
+	 */
+	uint64_t	pcie_recovery_histogram;
+} __rte_packed;
 
+/**********************
+ * hwrm_exec_fwd_resp *
+ **********************/
 
-/* hwrm_nvm_get_dev_info_input (size:128b/16B) */
-struct hwrm_nvm_get_dev_info_input {
+
+/* hwrm_exec_fwd_resp_input (size:1024b/128B) */
+struct hwrm_exec_fwd_resp_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41545,10 +44061,26 @@ struct hwrm_nvm_get_dev_info_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/*
+	 * This is an encapsulated request. This request should
+	 * be executed by the HWRM and the response should be
+	 * provided in the response buffer inside the encapsulated
+	 * request.
+	 */
+	uint32_t	encap_request[26];
+	/*
+	 * This value indicates the target id of the response to
+	 * the encapsulated request.
+	 * 0x0 - 0xFFF8 - Used for function ids
+	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
+	 * 0xFFFF - HWRM
+	 */
+	uint16_t	encap_resp_target_id;
+	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_nvm_get_dev_info_output (size:256b/32B) */
-struct hwrm_nvm_get_dev_info_output {
+/* hwrm_exec_fwd_resp_output (size:128b/16B) */
+struct hwrm_exec_fwd_resp_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41557,23 +44089,7 @@ struct hwrm_nvm_get_dev_info_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Manufacturer ID. */
-	uint16_t	manufacturer_id;
-	/* Device ID. */
-	uint16_t	device_id;
-	/* Sector size of the NVRAM device. */
-	uint32_t	sector_size;
-	/* Total size, in bytes of the NVRAM device. */
-	uint32_t	nvram_size;
-	uint32_t	reserved_size;
-	/* Available size that can be used, in bytes.  Available size is the NVRAM size take away the used size and reserved size. */
-	uint32_t	available_size;
-	/* This field represents the major version of NVM cfg */
-	uint8_t	nvm_cfg_ver_maj;
-	/* This field represents the minor version of NVM cfg */
-	uint8_t	nvm_cfg_ver_min;
-	/* This field represents the update version of NVM cfg */
-	uint8_t	nvm_cfg_ver_upd;
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -41584,13 +44100,13 @@ struct hwrm_nvm_get_dev_info_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**************************
- * hwrm_nvm_mod_dir_entry *
- **************************/
+/************************
+ * hwrm_reject_fwd_resp *
+ ************************/
 
 
-/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
-struct hwrm_nvm_mod_dir_entry_input {
+/* hwrm_reject_fwd_resp_input (size:1024b/128B) */
+struct hwrm_reject_fwd_resp_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41619,32 +44135,26 @@ struct hwrm_nvm_mod_dir_entry_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	enables;
 	/*
-	 * This bit must be '1' for the checksum field to be
-	 * configured.
-	 */
-	#define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM     UINT32_C(0x1)
-	/* Directory Entry Index */
-	uint16_t	dir_idx;
-	/*
-	 * Directory ordinal.
-	 * The (0-based) instance of this Directory Type.
+	 * This is an encapsulated request. This request should
+	 * be rejected by the HWRM and the error response should be
+	 * provided in the response buffer inside the encapsulated
+	 * request.
 	 */
-	uint16_t	dir_ordinal;
-	/* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
-	uint16_t	dir_ext;
-	/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
-	uint16_t	dir_attr;
+	uint32_t	encap_request[26];
 	/*
-	 * If valid, then this field updates the checksum
-	 * value of the content in the directory entry.
+	 * This value indicates the target id of the response to
+	 * the encapsulated request.
+	 * 0x0 - 0xFFF8 - Used for function ids
+	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
+	 * 0xFFFF - HWRM
 	 */
-	uint32_t	checksum;
+	uint16_t	encap_resp_target_id;
+	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
-struct hwrm_nvm_mod_dir_entry_output {
+/* hwrm_reject_fwd_resp_output (size:128b/16B) */
+struct hwrm_reject_fwd_resp_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41664,13 +44174,13 @@ struct hwrm_nvm_mod_dir_entry_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**************************
- * hwrm_nvm_verify_update *
- **************************/
+/*****************
+ * hwrm_fwd_resp *
+ *****************/
 
 
-/* hwrm_nvm_verify_update_input (size:192b/24B) */
-struct hwrm_nvm_verify_update_input {
+/* hwrm_fwd_resp_input (size:1024b/128B) */
+struct hwrm_fwd_resp_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41699,26 +44209,41 @@ struct hwrm_nvm_verify_update_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* Directory Entry Type, to be verified. */
-	uint16_t	dir_type;
 	/*
-	 * Directory ordinal.
-	 * The instance of the Directory Type to be verified.
+	 * This value indicates the target id of the encapsulated
+	 * response.
+	 * 0x0 - 0xFFF8 - Used for function ids
+	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
+	 * 0xFFFF - HWRM
 	 */
-	uint16_t	dir_ordinal;
+	uint16_t	encap_resp_target_id;
 	/*
-	 * The Directory Entry Extension flags.
-	 * The "UPDATE" extension flag must be set in this value.
-	 * A corresponding directory entry with the same type and ordinal values but *without*
-	 * the "UPDATE" extension flag must also exist. The other flags of the extension must
-	 * be identical between the active and update entries.
+	 * This value indicates the completion ring the encapsulated
+	 * response will be optionally completed on.  If the value is
+	 * -1, then no CR completion shall be generated for the
+	 * encapsulated response. Any other value must be a
+	 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
+	 * is provided, then a CR completion shall be generated for
+	 * the encapsulated response.
 	 */
-	uint16_t	dir_ext;
-	uint8_t	unused_0[2];
+	uint16_t	encap_resp_cmpl_ring;
+	/* This field indicates the length of encapsulated response. */
+	uint16_t	encap_resp_len;
+	uint8_t	unused_0;
+	uint8_t	unused_1;
+	/*
+	 * This is the host address where the encapsulated response
+	 * will be written.
+	 * This area must be 16B aligned and must be cleared to zero
+	 * before the original request is made.
+	 */
+	uint64_t	encap_resp_addr;
+	/* This is an encapsulated response. */
+	uint32_t	encap_resp[24];
 } __rte_packed;
 
-/* hwrm_nvm_verify_update_output (size:128b/16B) */
-struct hwrm_nvm_verify_update_output {
+/* hwrm_fwd_resp_output (size:128b/16B) */
+struct hwrm_fwd_resp_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41738,13 +44263,13 @@ struct hwrm_nvm_verify_update_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/***************************
- * hwrm_nvm_install_update *
- ***************************/
+/*****************************
+ * hwrm_fwd_async_event_cmpl *
+ *****************************/
 
 
-/* hwrm_nvm_install_update_input (size:192b/24B) */
-struct hwrm_nvm_install_update_input {
+/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
+struct hwrm_fwd_async_event_cmpl_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41774,56 +44299,21 @@ struct hwrm_nvm_install_update_input {
 	 */
 	uint64_t	resp_addr;
 	/*
-	 * Installation type. If the value 3 through 0xffff is used,
-	 * only packaged items with that type value will be installed and
-	 * conditional installation directives for those packaged items
-	 * will be over-ridden (i.e. 'create' or 'replace' will be treated
-	 * as 'install').
-	 */
-	uint32_t	install_type;
-	/*
-	 * Perform a normal package installation. Conditional installation
-	 * directives (e.g. 'create' and 'replace') of packaged items
-	 * will be followed.
-	 */
-	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
-	/*
-	 * Install all packaged items regardless of installation directive
-	 * (i.e. treat all packaged items as though they have an installation
-	 * directive of 'install').
-	 */
-	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
-		UINT32_C(0xffffffff)
-	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
-		HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
-	uint16_t	flags;
-	/* If set to 1, then securely erase all unused locations in persistent storage. */
-	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
-		UINT32_C(0x1)
-	/*
-	 * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
-	 * When combined with erase_unused_space then unspecified images will be securely erased.
-	 */
-	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
-		UINT32_C(0x2)
-	/*
-	 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
-	 * Allow additional time for this command to complete if this bit is set to 1.
-	 */
-	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
-		UINT32_C(0x4)
-	/*
-	 * If set to 1, FW will verify the package in the "UPDATE" NVM item
-	 * without installing it. This flag is for FW internal use only.
-	 * Users should not set this flag. The request will otherwise fail.
+	 * This value indicates the target id of the encapsulated
+	 * asynchronous event.
+	 * 0x0 - 0xFFF8 - Used for function ids
+	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
+	 * 0xFFFF - Broadcast to all children VFs (only applicable when
+	 * a PF is the requester)
 	 */
-	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
-		UINT32_C(0x8)
-	uint8_t	unused_0[2];
+	uint16_t	encap_async_event_target_id;
+	uint8_t	unused_0[6];
+	/* This is an encapsulated asynchronous event completion. */
+	uint32_t	encap_async_event_cmpl[4];
 } __rte_packed;
 
-/* hwrm_nvm_install_update_output (size:192b/24B) */
-struct hwrm_nvm_install_update_output {
+/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
+struct hwrm_fwd_async_event_cmpl_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41832,55 +44322,7 @@ struct hwrm_nvm_install_update_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/*
-	 * Bit-mask of successfully installed items.
-	 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
-	 * A value of 0 indicates that no items were successfully installed.
-	 */
-	uint64_t	installed_items;
-	/* result is 8 b */
-	uint8_t	result;
-	/* There was no problem with the package installation. */
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
-		HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
-	/* problem_item is 8 b */
-	uint8_t	problem_item;
-	/* There was no problem with any packaged items. */
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
-		UINT32_C(0x0)
-	/* There was a problem with the NVM package itself. */
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
-		UINT32_C(0xff)
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
-		HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
-	/* reset_required is 8 b */
-	uint8_t	reset_required;
-	/*
-	 * No reset is required for installed/updated firmware or
-	 * microcode to take effect.
-	 */
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
-		UINT32_C(0x0)
-	/*
-	 * A PCIe reset (e.g. system reboot) is
-	 * required for newly installed/updated firmware or
-	 * microcode to take effect.
-	 */
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
-		UINT32_C(0x1)
-	/*
-	 * A controller power reset (e.g. system power-cycle) is
-	 * required for newly installed/updated firmware or
-	 * microcode to take effect. Some newly installed/updated
-	 * firmware or microcode may still take effect upon the
-	 * next PCIe reset.
-	 */
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
-		UINT32_C(0x2)
-	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
-		HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
-	uint8_t	unused_0[4];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -41891,31 +44333,13 @@ struct hwrm_nvm_install_update_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
-struct hwrm_nvm_install_update_cmd_err {
-	/*
-	 * command specific error codes that goes to
-	 * the cmd_err field in Common HWRM Error Response.
-	 */
-	uint8_t	code;
-	/* Unknown error */
-	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN  UINT32_C(0x0)
-	/* Unable to complete operation due to fragmentation */
-	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
-	/* nvm is completely full. */
-	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
-	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
-		HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
-	uint8_t	unused_0[7];
-} __rte_packed;
-
-/******************
- * hwrm_nvm_flush *
- ******************/
+/**************************
+ * hwrm_nvm_raw_write_blk *
+ **************************/
 
 
-/* hwrm_nvm_flush_input (size:128b/16B) */
-struct hwrm_nvm_flush_input {
+/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
+struct hwrm_nvm_raw_write_blk_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -41944,10 +44368,22 @@ struct hwrm_nvm_flush_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/*
+	 * 64-bit Host Source Address.
+	 * This is the location of the source data to be written.
+	 */
+	uint64_t	host_src_addr;
+	/*
+	 * 32-bit Destination Address.
+	 * This is the NVRAM byte-offset where the source data will be written to.
+	 */
+	uint32_t	dest_addr;
+	/* Length of data to be written, in bytes. */
+	uint32_t	len;
 } __rte_packed;
 
-/* hwrm_nvm_flush_output (size:128b/16B) */
-struct hwrm_nvm_flush_output {
+/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
+struct hwrm_nvm_raw_write_blk_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -41967,29 +44403,13 @@ struct hwrm_nvm_flush_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/* hwrm_nvm_flush_cmd_err (size:64b/8B) */
-struct hwrm_nvm_flush_cmd_err {
-	/*
-	 * command specific error codes that goes to
-	 * the cmd_err field in Common HWRM Error Response.
-	 */
-	uint8_t	code;
-	/* Unknown error */
-	#define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
-	/* flush could not be performed */
-	#define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL    UINT32_C(0x1)
-	#define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
-		HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
-	uint8_t	unused_0[7];
-} __rte_packed;
-
-/*************************
- * hwrm_nvm_get_variable *
- *************************/
+/*****************
+ * hwrm_nvm_read *
+ *****************/
 
 
-/* hwrm_nvm_get_variable_input (size:320b/40B) */
-struct hwrm_nvm_get_variable_input {
+/* hwrm_nvm_read_input (size:320b/40B) */
+struct hwrm_nvm_read_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -42019,49 +44439,22 @@ struct hwrm_nvm_get_variable_input {
 	 */
 	uint64_t	resp_addr;
 	/*
-	 * This is the host address where
-	 * nvm variable will be stored
-	 */
-	uint64_t	dest_data_addr;
-	/* size of data in bits */
-	uint16_t	data_len;
-	/* nvm cfg option number */
-	uint16_t	option_num;
-	/* reserved. */
-	#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0    UINT32_C(0x0)
-	/* reserved. */
-	#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
-		UINT32_C(0xffff)
-	#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
-		HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
-	/*
-	 * Number of dimensions for this nvm configuration variable.
-	 * This value indicates how many of the indexN values to use.
-	 * A value of 0 means that none of the indexN values are valid.
-	 * A value of 1 requires at index0 is valued, a value of 2
-	 * requires that index0 and index1 are valid, and so forth
-	 */
-	uint16_t	dimensions;
-	/* index for the 1st dimensions */
-	uint16_t	index_0;
-	/* index for the 2nd dimensions */
-	uint16_t	index_1;
-	/* index for the 3rd dimensions */
-	uint16_t	index_2;
-	/* index for the 4th dimensions */
-	uint16_t	index_3;
-	uint8_t	flags;
-	/*
-	 * When this bit is set to 1, the factory default value will be returned,
-	 * 0 returns the operational value.
+	 * 64-bit Host Destination Address.
+	 * This is the host address where the data will be written to.
 	 */
-	#define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
-		UINT32_C(0x1)
-	uint8_t	unused_0;
+	uint64_t	host_dest_addr;
+	/* The 0-based index of the directory entry. */
+	uint16_t	dir_idx;
+	uint8_t	unused_0[2];
+	/* The NVRAM byte-offset to read from. */
+	uint32_t	offset;
+	/* The length of the data to be read, in bytes. */
+	uint32_t	len;
+	uint8_t	unused_1[4];
 } __rte_packed;
 
-/* hwrm_nvm_get_variable_output (size:128b/16B) */
-struct hwrm_nvm_get_variable_output {
+/* hwrm_nvm_read_output (size:128b/16B) */
+struct hwrm_nvm_read_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -42070,25 +44463,7 @@ struct hwrm_nvm_get_variable_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* size of data of the actual variable retrieved in bits */
-	uint16_t	data_len;
-	/*
-	 * option_num is the option number for the data retrieved.  It is possible in the
-	 * future that the option number returned would be different than requested.  This
-	 * condition could occur if an option is deprecated and a new option id is defined
-	 * with similar characteristics, but has a slightly different definition.  This
-	 * also makes it convenient for the caller to identify the variable result with
-	 * the option id from the response.
-	 */
-	uint16_t	option_num;
-	/* reserved. */
-	#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0    UINT32_C(0x0)
-	/* reserved. */
-	#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
-		UINT32_C(0xffff)
-	#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
-		HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
-	uint8_t	unused_0[3];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -42099,33 +44474,13 @@ struct hwrm_nvm_get_variable_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
-struct hwrm_nvm_get_variable_cmd_err {
-	/*
-	 * command specific error codes that goes to
-	 * the cmd_err field in Common HWRM Error Response.
-	 */
-	uint8_t	code;
-	/* Unknown error */
-	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN       UINT32_C(0x0)
-	/* variable does not exist */
-	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
-	/* configuration is corrupted and the variable cannot be saved */
-	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   UINT32_C(0x2)
-	/* length specified is too small */
-	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
-	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
-		HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
-	uint8_t	unused_0[7];
-} __rte_packed;
-
-/*************************
- * hwrm_nvm_set_variable *
- *************************/
+/*********************
+ * hwrm_nvm_raw_dump *
+ *********************/
 
 
-/* hwrm_nvm_set_variable_input (size:320b/40B) */
-struct hwrm_nvm_set_variable_input {
+/* hwrm_nvm_raw_dump_input (size:256b/32B) */
+struct hwrm_nvm_raw_dump_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -42155,70 +44510,18 @@ struct hwrm_nvm_set_variable_input {
 	 */
 	uint64_t	resp_addr;
 	/*
-	 * This is the host address where
-	 * nvm variable will be copied from
-	 */
-	uint64_t	src_data_addr;
-	/* size of data in bits */
-	uint16_t	data_len;
-	/* nvm cfg option number */
-	uint16_t	option_num;
-	/* reserved. */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0    UINT32_C(0x0)
-	/* reserved. */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
-		UINT32_C(0xffff)
-	#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
-		HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
-	/*
-	 * Number of dimensions for this nvm configuration variable.
-	 * This value indicates how many of the indexN values to use.
-	 * A value of 0 means that none of the indexN values are valid.
-	 * A value of 1 requires at index0 is valued, a value of 2
-	 * requires that index0 and index1 are valid, and so forth
+	 * 64-bit Host Destination Address.
+	 * This is the host address where the data will be written to.
 	 */
-	uint16_t	dimensions;
-	/* index for the 1st dimensions */
-	uint16_t	index_0;
-	/* index for the 2nd dimensions */
-	uint16_t	index_1;
-	/* index for the 3rd dimensions */
-	uint16_t	index_2;
-	/* index for the 4th dimensions */
-	uint16_t	index_3;
-	uint8_t	flags;
-	/* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
-		UINT32_C(0x1)
-	/* encryption method */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
-		UINT32_C(0xe)
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT           1
-	/* No encryption. */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
-		(UINT32_C(0x0) << 1)
-	/* one-way encryption. */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
-		(UINT32_C(0x1) << 1)
-	/* symmetric AES256 encryption. */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
-		(UINT32_C(0x2) << 1)
-	/* SHA1 digest appended to plaintext contents, for authentication */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
-		(UINT32_C(0x3) << 1)
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
-		HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
-		UINT32_C(0x70)
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT         4
-	/* When this bit is 1, update the factory default region */
-	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
-		UINT32_C(0x80)
-	uint8_t	unused_0;
+	uint64_t	host_dest_addr;
+	/* 32-bit NVRAM byte-offset to read from. */
+	uint32_t	offset;
+	/* Total length of NVRAM contents to be read, in bytes. */
+	uint32_t	len;
 } __rte_packed;
 
-/* hwrm_nvm_set_variable_output (size:128b/16B) */
-struct hwrm_nvm_set_variable_output {
+/* hwrm_nvm_raw_dump_output (size:128b/16B) */
+struct hwrm_nvm_raw_dump_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -42238,31 +44541,13 @@ struct hwrm_nvm_set_variable_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
-struct hwrm_nvm_set_variable_cmd_err {
-	/*
-	 * command specific error codes that goes to
-	 * the cmd_err field in Common HWRM Error Response.
-	 */
-	uint8_t	code;
-	/* Unknown error */
-	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN       UINT32_C(0x0)
-	/* variable does not exist */
-	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
-	/* configuration is corrupted and the variable cannot be saved */
-	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   UINT32_C(0x2)
-	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
-		HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
-	uint8_t	unused_0[7];
-} __rte_packed;
-
 /****************************
- * hwrm_nvm_validate_option *
+ * hwrm_nvm_get_dir_entries *
  ****************************/
 
 
-/* hwrm_nvm_validate_option_input (size:320b/40B) */
-struct hwrm_nvm_validate_option_input {
+/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
+struct hwrm_nvm_get_dir_entries_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -42292,43 +44577,14 @@ struct hwrm_nvm_validate_option_input {
 	 */
 	uint64_t	resp_addr;
 	/*
-	 * This is the host address where
-	 * nvm variable will be copied from
-	 */
-	uint64_t	src_data_addr;
-	/* size of data in bits */
-	uint16_t	data_len;
-	/* nvm cfg option number */
-	uint16_t	option_num;
-	/* reserved. */
-	#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
-		UINT32_C(0x0)
-	/* reserved. */
-	#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
-		UINT32_C(0xffff)
-	#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
-		HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
-	/*
-	 * Number of dimensions for this nvm configuration variable.
-	 * This value indicates how many of the indexN values to use.
-	 * A value of 0 means that none of the indexN values are valid.
-	 * A value of 1 requires at index0 is valued, a value of 2
-	 * requires that index0 and index1 are valid, and so forth
+	 * 64-bit Host Destination Address.
+	 * This is the host address where the directory will be written.
 	 */
-	uint16_t	dimensions;
-	/* index for the 1st dimensions */
-	uint16_t	index_0;
-	/* index for the 2nd dimensions */
-	uint16_t	index_1;
-	/* index for the 3rd dimensions */
-	uint16_t	index_2;
-	/* index for the 4th dimensions */
-	uint16_t	index_3;
-	uint8_t	unused_0[2];
+	uint64_t	host_dest_addr;
 } __rte_packed;
 
-/* hwrm_nvm_validate_option_output (size:128b/16B) */
-struct hwrm_nvm_validate_option_output {
+/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
+struct hwrm_nvm_get_dir_entries_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -42337,14 +44593,7 @@ struct hwrm_nvm_validate_option_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint8_t	result;
-	/* indicates that the value provided for the option is not matching with the saved data. */
-	#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
-	/* indicates that the value provided for the option is matching the saved data. */
-	#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH     UINT32_C(0x1)
-	#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
-		HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
-	uint8_t	unused_0[6];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -42355,27 +44604,13 @@ struct hwrm_nvm_validate_option_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
-struct hwrm_nvm_validate_option_cmd_err {
-	/*
-	 * command specific error codes that goes to
-	 * the cmd_err field in Common HWRM Error Response.
-	 */
-	uint8_t	code;
-	/* Unknown error */
-	#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
-	#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
-		HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
-	uint8_t	unused_0[7];
-} __rte_packed;
-
-/****************
- * hwrm_oem_cmd *
- ****************/
+/*************************
+ * hwrm_nvm_get_dir_info *
+ *************************/
 
 
-/* hwrm_oem_cmd_input (size:1024b/128B) */
-struct hwrm_oem_cmd_input {
+/* hwrm_nvm_get_dir_info_input (size:128b/16B) */
+struct hwrm_nvm_get_dir_info_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -42404,14 +44639,10 @@ struct hwrm_oem_cmd_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	IANA;
-	uint32_t	unused_0;
-	/* This field contains the vendor specific command data. */
-	uint32_t	oem_data[26];
 } __rte_packed;
 
-/* hwrm_oem_cmd_output (size:768b/96B) */
-struct hwrm_oem_cmd_output {
+/* hwrm_nvm_get_dir_info_output (size:192b/24B) */
+struct hwrm_nvm_get_dir_info_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -42420,11 +44651,11 @@ struct hwrm_oem_cmd_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint32_t	IANA;
-	uint32_t	unused_0;
-	/* This field contains the vendor specific response data. */
-	uint32_t	oem_data[18];
-	uint8_t	unused_1[7];
+	/* Number of directory entries in the directory. */
+	uint32_t	entries;
+	/* Size of each directory entry, in bytes. */
+	uint32_t	entry_length;
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -42435,150 +44666,13 @@ struct hwrm_oem_cmd_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/*****************
- * hwrm_fw_reset *
+/******************
+ * hwrm_nvm_write *
  ******************/
 
 
-/* hwrm_fw_reset_input (size:192b/24B) */
-struct hwrm_fw_reset_input {
-	/* The HWRM command request type. */
-	uint16_t        req_type;
-	/*
-	 * The completion ring to send the completion event on. This should
-	 * be the NQ ID returned from the `nq_alloc` HWRM command.
-	 */
-	uint16_t        cmpl_ring;
-	/*
-	 * The sequence ID is used by the driver for tracking multiple
-	 * commands. This ID is treated as opaque data by the firmware and
-	 * the value is returned in the `hwrm_resp_hdr` upon completion.
-	 */
-	uint16_t        seq_id;
-	/*
-	 * The target ID of the command:
-	 * * 0x0-0xFFF8 - The function ID
-	 * * 0xFFF8-0xFFFE - Reserved for internal processors
-	 * * 0xFFFF - HWRM
-	 */
-	uint16_t        target_id;
-	/*
-	 * A physical address pointer pointing to a host buffer that the
-	 * command's response data will be written. This can be either a host
-	 * physical address (HPA) or a guest physical address (GPA) and must
-	 * point to a physically contiguous block of memory.
-	 */
-	uint64_t        resp_addr;
-	/* Type of embedded processor. */
-	uint8_t embedded_proc_type;
-	/* Boot Processor */
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
-		UINT32_C(0x0)
-	/* Management Processor */
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
-		UINT32_C(0x1)
-	/* Network control processor */
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
-		UINT32_C(0x2)
-	/* RoCE control processor */
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
-		UINT32_C(0x3)
-	/*
-	 * Host (in multi-host environment): This is only valid if requester is IPC.
-	 * Reinit host hardware resources and PCIe.
-	 */
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
-		UINT32_C(0x4)
-	/* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
-		UINT32_C(0x5)
-	/* Reset all blocks of the chip (including all processors) */
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
-		UINT32_C(0x6)
-	/*
-	 * Host (in multi-host environment): This is only valid if requester is IPC.
-	 * Reinit host hardware resources.
-	 */
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
-		UINT32_C(0x7)
-	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
-		HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
-	/* Type of self reset. */
-	uint8_t selfrst_status;
-	/* No Self Reset */
-	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
-		UINT32_C(0x0)
-	/* Self Reset as soon as possible to do so safely */
-	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
-		UINT32_C(0x1)
-	/* Self Reset on PCIe Reset */
-	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
-		UINT32_C(0x2)
-	/* Self Reset immediately after notification to all clients. */
-	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
-		UINT32_C(0x3)
-	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
-		HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
-	/*
-	 * Indicate which host is being reset. 0 means first host.
-	 * Only valid when embedded_proc_type is host in multihost
-	 * environment
-	 */
-	uint8_t host_idx;
-	uint8_t flags;
-	/*
-	 * When this bit is '1', then the core firmware initiates
-	 * the reset only after graceful shut down of all registered instances.
-	 * If not, the device will continue with the existing firmware.
-	 */
-	#define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL     UINT32_C(0x1)
-	uint8_t unused_0[4];
-} __rte_packed;
-
-/* hwrm_fw_reset_output (size:128b/16B) */
-struct hwrm_fw_reset_output {
-	/* The specific error status for the command. */
-	uint16_t        error_code;
-	/* The HWRM command request type. */
-	uint16_t        req_type;
-	/* The sequence ID from the original command. */
-	uint16_t        seq_id;
-	/* The length of the response data in number of bytes. */
-	uint16_t        resp_len;
-	/* Type of self reset. */
-	uint8_t selfrst_status;
-	/* No Self Reset */
-	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
-		UINT32_C(0x0)
-	/* Self Reset as soon as possible to do so safely */
-	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
-		UINT32_C(0x1)
-	/* Self Reset on PCIe Reset */
-	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
-		UINT32_C(0x2)
-	/* Self Reset immediately after notification to all clients. */
-	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
-		UINT32_C(0x3)
-	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
-		HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
-	uint8_t unused_0[6];
-	/*
-	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM.  This field should be read as '1'
-	 * to indicate that the output has been completely written.
-	 * When writing a command completion or response to an internal processor,
-	 * the order of writes has to be such that this field is written last.
-	 */
-	uint8_t valid;
-} __rte_packed;
-
-/**********************
- * hwrm_port_ts_query *
- ***********************/
-
-
-/* hwrm_port_ts_query_input (size:192b/24B) */
-struct hwrm_port_ts_query_input {
+/* hwrm_nvm_write_input (size:384b/48B) */
+struct hwrm_nvm_write_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -42607,31 +44701,49 @@ struct hwrm_port_ts_query_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint32_t	flags;
 	/*
-	 * Enumeration denoting the RX, TX type of the resource.
-	 * This enumeration is used for resources that are similar for both
-	 * TX and RX paths of the chip.
+	 * 64-bit Host Source Address.
+	 * This is where the source data is.
 	 */
-	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH		0x1UL
-	/* tx path */
-	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX		0x0UL
-	/* rx path */
-	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX		0x1UL
-	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST	\
-		HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
+	uint64_t	host_src_addr;
+	/* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
+	uint16_t	dir_type;
 	/*
-	 * If set, the response includes the current value of the free
-	 * running timer.
+	 * Directory ordinal.
+	 * The 0-based instance of the combined Directory Entry Type and Extension.
 	 */
-	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME	0x2UL
-	/* Port ID of port that is being queried. */
-	uint16_t	port_id;
-	uint8_t		unused_0[2];
+	uint16_t	dir_ordinal;
+	/* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
+	uint16_t	dir_ext;
+	/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
+	uint16_t	dir_attr;
+	/*
+	 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
+	 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
+	 */
+	uint32_t	dir_data_length;
+	/* Option. */
+	uint16_t	option;
+	uint16_t	flags;
+	/*
+	 * When this bit is '1', the original active image
+	 * will not be removed. TBD: what purpose is this?
+	 */
+	#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
+		UINT32_C(0x1)
+	/*
+	 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
+	 * If this value is less than the specified data length, it will be ignored.
+	 * The response will contain the actual allocated item length, which may be greater than the requested item length.
+	 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
+	 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
+	 */
+	uint32_t	dir_item_length;
+	uint32_t	unused_0;
 } __rte_packed;
 
-/* hwrm_port_ts_query_output (size:192b/24B) */
-struct hwrm_port_ts_query_output {
+/* hwrm_nvm_write_output (size:128b/16B) */
+struct hwrm_nvm_write_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -42641,13 +44753,13 @@ struct hwrm_port_ts_query_output {
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
 	/*
-	 * Timestamp value of PTP message captured, or current value of
-	 * free running timer.
+	 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
+	 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
 	 */
-	uint32_t	ptp_msg_ts[2];
-	/* Sequence ID of the PTP message captured. */
-	uint16_t	ptp_msg_seqid;
-	uint8_t		unused_0[5];
+	uint32_t	dir_item_length;
+	/* The directory index of the created or modified item. */
+	uint16_t	dir_idx;
+	uint8_t	unused_0;
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -42655,65 +44767,34 @@ struct hwrm_port_ts_query_output {
 	 * When writing a command completion or response to an internal processor,
 	 * the order of writes has to be such that this field is written last.
 	 */
-	uint8_t		valid;
+	uint8_t	valid;
 } __rte_packed;
 
-/*
- * This structure is fixed at the beginning of the ChiMP SRAM (GRC
- * offset: 0x31001F0). Host software is expected to read from this
- * location for a defined signature. If it exists, the software can
- * assume the presence of this structure and the validity of the
- * FW_STATUS location in the next field.
- */
-/* hcomm_status (size:64b/8B) */
-struct hcomm_status {
-	uint32_t	sig_ver;
-	/*
-	 * This field defines the version of the structure. The latest
-	 * version value is 1.
-	 */
-	#define HCOMM_STATUS_VER_MASK		UINT32_C(0xff)
-	#define HCOMM_STATUS_VER_SFT		0
-	#define HCOMM_STATUS_VER_LATEST		UINT32_C(0x1)
-	#define HCOMM_STATUS_VER_LAST		HCOMM_STATUS_VER_LATEST
-	/*
-	 * This field is to store the signature value to indicate the
-	 * presence of the structure.
-	 */
-	#define HCOMM_STATUS_SIGNATURE_MASK	UINT32_C(0xffffff00)
-	#define HCOMM_STATUS_SIGNATURE_SFT	8
-	#define HCOMM_STATUS_SIGNATURE_VAL	(UINT32_C(0x484353) << 8)
-	#define HCOMM_STATUS_SIGNATURE_LAST	HCOMM_STATUS_SIGNATURE_VAL
-	uint32_t	fw_status_loc;
-	#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK	UINT32_C(0x3)
-	#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT	0
-	/* PCIE configuration space */
-	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG	UINT32_C(0x0)
-	/* GRC space */
-	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC	UINT32_C(0x1)
-	/* BAR0 space */
-	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0	UINT32_C(0x2)
-	/* BAR1 space */
-	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1	UINT32_C(0x3)
-	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST	\
-		HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
+/* hwrm_nvm_write_cmd_err (size:64b/8B) */
+struct hwrm_nvm_write_cmd_err {
 	/*
-	 * This offset where the fw_status register is located. The value
-	 * is generally 4-byte aligned.
+	 * command specific error codes that goes to
+	 * the cmd_err field in Common HWRM Error Response.
 	 */
-	#define HCOMM_STATUS_TRUE_OFFSET_MASK		UINT32_C(0xfffffffc)
-	#define HCOMM_STATUS_TRUE_OFFSET_SFT		2
+	uint8_t	code;
+	/* Unknown error */
+	#define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN  UINT32_C(0x0)
+	/* Unable to complete operation due to fragmentation */
+	#define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
+	/* nvm is completely full. */
+	#define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
+	#define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
+		HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
+	uint8_t	unused_0[7];
 } __rte_packed;
-/* This is the GRC offset where the hcomm_status struct resides. */
-#define HCOMM_STATUS_STRUCT_LOC		0x31001F0UL
 
-/**************************
- * hwrm_cfa_counter_qcaps *
- **************************/
+/*******************
+ * hwrm_nvm_modify *
+ *******************/
 
 
-/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
-struct hwrm_cfa_counter_qcaps_input {
+/* hwrm_nvm_modify_input (size:320b/40B) */
+struct hwrm_nvm_modify_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -42742,10 +44823,42 @@ struct hwrm_cfa_counter_qcaps_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
+	/*
+	 * 64-bit Host Source Address.
+	 * This is where the modified data is.
+	 */
+	uint64_t	host_src_addr;
+	/* 16-bit directory entry index. */
+	uint16_t	dir_idx;
+	uint16_t	flags;
+	/*
+	 * This flag indicates the sender wants to modify a continuous NVRAM
+	 * area using a batch of this HWRM requests. The offset of a request
+	 * must be continuous to the end of previous request's. Firmware does
+	 * not update the directory entry until receiving the last request,
+	 * which is indicated by the batch_last flag.
+	 * This flag is set usually when a sender does not have a block of
+	 * memory that is big enough to hold the entire NVRAM data for send
+	 * at one time.
+	 */
+	#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE     UINT32_C(0x1)
+	/*
+	 * This flag can be used only when the batch_mode flag is set.
+	 * It indicates this request is the last of batch requests.
+	 */
+	#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST     UINT32_C(0x2)
+	/* 32-bit NVRAM byte-offset to modify content from. */
+	uint32_t	offset;
+	/*
+	 * Length of data to be modified, in bytes. The length shall
+	 * be non-zero.
+	 */
+	uint32_t	len;
+	uint8_t	unused_1[4];
 } __rte_packed;
 
-/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
-struct hwrm_cfa_counter_qcaps_output {
+/* hwrm_nvm_modify_output (size:128b/16B) */
+struct hwrm_nvm_modify_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -42754,46 +44867,7 @@ struct hwrm_cfa_counter_qcaps_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	uint32_t	flags;
-	/* Enumeration denoting the supported CFA counter format. */
-	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
-		UINT32_C(0x1)
-	/* CFA counter types are not supported. */
-	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
-		UINT32_C(0x0)
-	/* 64-bit packet counters followed by 64-bit byte counters format. */
-	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
-		UINT32_C(0x1)
-	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
-		HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
-	uint32_t	unused_0;
-	/* Minimum guaranteed number of flow counters supported for this function, in RX direction. */
-	uint32_t	min_rx_fc;
-	/* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */
-	uint32_t	max_rx_fc;
-	/* Minimum guaranteed number of flow counters supported for this function, in TX direction. */
-	uint32_t	min_tx_fc;
-	/* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */
-	uint32_t	max_tx_fc;
-	/* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */
-	uint32_t	min_rx_efc;
-	/* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */
-	uint32_t	max_rx_efc;
-	/* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */
-	uint32_t	min_tx_efc;
-	/* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */
-	uint32_t	max_tx_efc;
-	/* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */
-	uint32_t	min_rx_mdc;
-	/* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */
-	uint32_t	max_rx_mdc;
-	/* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */
-	uint32_t	min_tx_mdc;
-	/* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */
-	uint32_t	max_tx_mdc;
-	/* Maximum guaranteed number of flow counters which can be used during flow alloc. */
-	uint32_t	max_flow_alloc_fc;
-	uint8_t	unused_1[3];
+	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM.  This field should be read as '1'
@@ -42804,13 +44878,13 @@ struct hwrm_cfa_counter_qcaps_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/************************
- * hwrm_cfa_counter_cfg *
- ************************/
+/***************************
+ * hwrm_nvm_find_dir_entry *
+ ***************************/
 
 
-/* hwrm_cfa_counter_cfg_input (size:256b/32B) */
-struct hwrm_cfa_counter_cfg_input {
+/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
+struct hwrm_nvm_find_dir_entry_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -42839,64 +44913,42 @@ struct hwrm_cfa_counter_cfg_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint16_t	flags;
-	/* Enumeration denoting the configuration mode. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
-		UINT32_C(0x1)
-	/* Disable the configuration mode. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
-		UINT32_C(0x0)
-	/* Enable the configuration mode. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
+	uint32_t	enables;
+	/*
+	 * This bit must be '1' for the dir_idx_valid field to be
+	 * configured.
+	 */
+	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
 		UINT32_C(0x1)
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
-		HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
-	/* Enumeration denoting the RX, TX type of the resource. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
-		UINT32_C(0x2)
-	/* Tx path. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
-		(UINT32_C(0x0) << 1)
-	/* Rx path. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
-		(UINT32_C(0x1) << 1)
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
-		HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
-	/* Enumeration denoting the data transfer mode. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
-		UINT32_C(0xc)
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT       2
-	/* Push mode. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
-		(UINT32_C(0x0) << 2)
-	/* Pull mode. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
-		(UINT32_C(0x1) << 2)
-	/* Pull on async update. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
-		(UINT32_C(0x2) << 2)
-	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
-		HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
-	uint16_t	counter_type;
-	/* Flow counters. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC  UINT32_C(0x0)
-	/* Extended flow counters. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
-	/* Meter drop counters. */
-	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
-	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
-		HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
-	/* Ctx memory handle to be used for the counter. */
-	uint16_t	ctx_id;
-	/* Counter update cadence hint (only in Push mode). */
-	uint16_t	update_tmr_ms;
-	/* Total number of entries. */
-	uint32_t	num_entries;
-	uint32_t	unused_0;
+	/* Directory Entry Index */
+	uint16_t	dir_idx;
+	/* Directory Entry (Image) Type */
+	uint16_t	dir_type;
+	/*
+	 * Directory ordinal.
+	 * The instance of this Directory Type
+	 */
+	uint16_t	dir_ordinal;
+	/* The Directory Entry Extension flags. */
+	uint16_t	dir_ext;
+	/* This value indicates the search option using dir_ordinal. */
+	uint8_t	opt_ordinal;
+	/* This value indicates the search option using dir_ordinal. */
+	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
+	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
+	/* Equal to specified ordinal value. */
+	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ    UINT32_C(0x0)
+	/* Greater than or equal to specified ordinal value */
+	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE    UINT32_C(0x1)
+	/* Greater than specified ordinal value */
+	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT    UINT32_C(0x2)
+	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
+		HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
+	uint8_t	unused_0[3];
 } __rte_packed;
 
-/* hwrm_cfa_counter_cfg_output (size:128b/16B) */
-struct hwrm_cfa_counter_cfg_output {
+/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
+struct hwrm_nvm_find_dir_entry_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -42905,6 +44957,19 @@ struct hwrm_cfa_counter_cfg_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
+	/* Allocated NVRAM for this directory entry, in bytes. */
+	uint32_t	dir_item_length;
+	/* Size of the stored data for this directory entry, in bytes. */
+	uint32_t	dir_data_length;
+	/*
+	 * Firmware version.
+	 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
+	 */
+	uint32_t	fw_ver;
+	/* Directory ordinal. */
+	uint16_t	dir_ordinal;
+	/* Directory Entry Index */
+	uint16_t	dir_idx;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
@@ -42916,13 +44981,13 @@ struct hwrm_cfa_counter_cfg_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/***************************
- * hwrm_cfa_counter_qstats *
- ***************************/
+/****************************
+ * hwrm_nvm_erase_dir_entry *
+ ****************************/
 
 
-/* hwrm_cfa_counter_qstats_input (size:320b/40B) */
-struct hwrm_cfa_counter_qstats_input {
+/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
+struct hwrm_nvm_erase_dir_entry_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -42951,27 +45016,13 @@ struct hwrm_cfa_counter_qstats_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	uint16_t	flags;
-	/* Enumeration denoting the RX, TX type of the resource. */
-	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH     UINT32_C(0x1)
-	/* Tx path. */
-	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)
-	/* Rx path. */
-	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)
-	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
-		HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
-	uint16_t	counter_type;
-	uint16_t	input_flow_ctx_id;
-	uint16_t	num_entries;
-	uint16_t	delta_time_ms;
-	uint16_t	meter_instance_id;
-	uint16_t	mdc_ctx_id;
-	uint8_t	unused_0[2];
-	uint64_t	expected_count;
+	/* Directory Entry Index */
+	uint16_t	dir_idx;
+	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_cfa_counter_qstats_output (size:128b/16B) */
-struct hwrm_cfa_counter_qstats_output {
+/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
+struct hwrm_nvm_erase_dir_entry_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -42991,13 +45042,13 @@ struct hwrm_cfa_counter_qstats_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/***********************
- * hwrm_cfa_pair_alloc *
- ***********************/
+/*************************
+ * hwrm_nvm_get_dev_info *
+ *************************/
 
 
-/* hwrm_cfa_pair_alloc_input (size:576b/72B) */
-struct hwrm_cfa_pair_alloc_input {
+/* hwrm_nvm_get_dev_info_input (size:128b/16B) */
+struct hwrm_nvm_get_dev_info_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -43026,104 +45077,256 @@ struct hwrm_cfa_pair_alloc_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/*
-	 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
-	 *            5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
+} __rte_packed;
+
+/* hwrm_nvm_get_dev_info_output (size:640b/80B) */
+struct hwrm_nvm_get_dev_info_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* Manufacturer ID. */
+	uint16_t	manufacturer_id;
+	/* Device ID. */
+	uint16_t	device_id;
+	/* Sector size of the NVRAM device. */
+	uint32_t	sector_size;
+	/* Total size, in bytes of the NVRAM device. */
+	uint32_t	nvram_size;
+	uint32_t	reserved_size;
+	/* Available size that can be used, in bytes.  Available size is the NVRAM size take away the used size and reserved size. */
+	uint32_t	available_size;
+	/* This field represents the major version of NVM cfg */
+	uint8_t	nvm_cfg_ver_maj;
+	/* This field represents the minor version of NVM cfg */
+	uint8_t	nvm_cfg_ver_min;
+	/* This field represents the update version of NVM cfg */
+	uint8_t	nvm_cfg_ver_upd;
+	uint8_t	flags;
+	/*
+	 * If set to 1, firmware will provide various firmware version
+	 * information stored in the flash.
 	 */
-	uint16_t	pair_mode;
-	/* Pair between VF on local host with PF or VF on specified host. */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
-		UINT32_C(0x0)
-	/* Pair between REP on local host with PF or VF on specified host. */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
+	#define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \
 		UINT32_C(0x1)
-	/* Pair between REP on local host with REP on specified host. */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
-		UINT32_C(0x2)
-	/* Pair for the proxy interface. */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
-		UINT32_C(0x3)
-	/* Pair for the PF interface. */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
-		UINT32_C(0x4)
-	/* Modify existing rep2fn pair and move pair to new PF. */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
-		UINT32_C(0x5)
-	/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
-		UINT32_C(0x6)
-	/* Truflow pair between REP on local host with PF or VF on specified host. */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
-		UINT32_C(0x7)
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
-		HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
-	/* Logical VF number (range: 0 -> MAX_VFS -1). */
-	uint16_t	vf_a_id;
-	/* Logical Host (0xff-local host). */
-	uint8_t	host_b_id;
-	/* Logical PF (0xff-PF for command channel). */
-	uint8_t	pf_b_id;
-	/* Logical VF number (range: 0 -> MAX_VFS -1). */
-	uint16_t	vf_b_id;
-	/* Loopback port (0xff-internal loopback), valid for mode-3. */
-	uint8_t	port_id;
-	/* Priority used for encap of loopback packets valid for mode-3. */
-	uint8_t	pri;
-	/* New PF for rep2fn modify, valid for mode 5. */
-	uint16_t	new_pf_fid;
+	/*
+	 * This field represents the board package name stored in the flash.
+	 * (ASCII chars with NULL at the end).
+	 */
+	char	pkg_name[16];
+	/*
+	 * This field represents the major version of HWRM firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	hwrm_fw_major;
+	/*
+	 * This field represents the minor version of HWRM firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	hwrm_fw_minor;
+	/*
+	 * This field represents the build version of HWRM firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	hwrm_fw_build;
+	/*
+	 * This field can be used to represent firmware branches or customer
+	 * specific releases tied to a specific (major, minor, build) version
+	 * of the HWRM firmware.
+	 */
+	uint16_t	hwrm_fw_patch;
+	/*
+	 * This field represents the major version of mgmt firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	mgmt_fw_major;
+	/*
+	 * This field represents the minor version of mgmt firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	mgmt_fw_minor;
+	/*
+	 * This field represents the build version of mgmt firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	mgmt_fw_build;
+	/*
+	 * This field can be used to represent firmware branches or customer
+	 * specific releases tied to a specific (major, minor, build) version
+	 * of the mgmt firmware.
+	 */
+	uint16_t	mgmt_fw_patch;
+	/*
+	 * This field represents the major version of roce firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	roce_fw_major;
+	/*
+	 * This field represents the minor version of roce firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	roce_fw_minor;
+	/*
+	 * This field represents the build version of roce firmware, stored in
+	 * the flash.
+	 */
+	uint16_t	roce_fw_build;
+	/*
+	 * This field can be used to represent firmware branches or customer
+	 * specific releases tied to a specific (major, minor, build) version
+	 * of the roce firmware.
+	 */
+	uint16_t	roce_fw_patch;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_nvm_mod_dir_entry *
+ **************************/
+
+
+/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
+struct hwrm_nvm_mod_dir_entry_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
 	uint32_t	enables;
 	/*
-	 * This bit must be '1' for the q_ab field to be
+	 * This bit must be '1' for the checksum field to be
 	 * configured.
 	 */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID      UINT32_C(0x1)
+	#define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM     UINT32_C(0x1)
+	/* Directory Entry Index */
+	uint16_t	dir_idx;
 	/*
-	 * This bit must be '1' for the q_ba field to be
-	 * configured.
+	 * Directory ordinal.
+	 * The (0-based) instance of this Directory Type.
 	 */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID      UINT32_C(0x2)
+	uint16_t	dir_ordinal;
+	/* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
+	uint16_t	dir_ext;
+	/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
+	uint16_t	dir_attr;
 	/*
-	 * This bit must be '1' for the fc_ab field to be
-	 * configured.
+	 * If valid, then this field updates the checksum
+	 * value of the content in the directory entry.
 	 */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID     UINT32_C(0x4)
+	uint32_t	checksum;
+} __rte_packed;
+
+/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
+struct hwrm_nvm_mod_dir_entry_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	unused_0[7];
 	/*
-	 * This bit must be '1' for the fc_ba field to be
-	 * configured.
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
 	 */
-	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID     UINT32_C(0x8)
-	/* VF Pair name (32 byte string). */
-	char	pair_name[32];
+	uint8_t	valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_nvm_verify_update *
+ **************************/
+
+
+/* hwrm_nvm_verify_update_input (size:192b/24B) */
+struct hwrm_nvm_verify_update_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
 	/*
-	 * The q_ab value specifies the logical index of the TX/RX CoS
-	 * queue to be assigned for traffic in the A to B direction of
-	 * the interface pair. The default value is 0.
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
 	 */
-	uint8_t	q_ab;
+	uint16_t	cmpl_ring;
 	/*
-	 * The q_ba value specifies the logical index of the TX/RX CoS
-	 * queue to be assigned for traffic in the B to A direction of
-	 * the interface pair. The default value is 1.
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
 	 */
-	uint8_t	q_ba;
+	uint16_t	seq_id;
 	/*
-	 * Specifies whether RX ring flow control is disabled (0) or enabled
-	 * (1) in the A to B direction. The default value is 0, meaning that
-	 * packets will be dropped when the B-side RX rings are full.
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
 	 */
-	uint8_t	fc_ab;
+	uint16_t	target_id;
 	/*
-	 * Specifies whether RX ring flow control is disabled (0) or enabled
-	 * (1) in the B to A direction. The default value is 1, meaning that
-	 * the RX CoS queue will be flow controlled when the A-side RX rings
-	 * are full.
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
 	 */
-	uint8_t	fc_ba;
-	uint8_t	unused_1[4];
+	uint64_t	resp_addr;
+	/* Directory Entry Type, to be verified. */
+	uint16_t	dir_type;
+	/*
+	 * Directory ordinal.
+	 * The instance of the Directory Type to be verified.
+	 */
+	uint16_t	dir_ordinal;
+	/*
+	 * The Directory Entry Extension flags.
+	 * The "UPDATE" extension flag must be set in this value.
+	 * A corresponding directory entry with the same type and ordinal values but *without*
+	 * the "UPDATE" extension flag must also exist. The other flags of the extension must
+	 * be identical between the active and update entries.
+	 */
+	uint16_t	dir_ext;
+	uint8_t	unused_0[2];
 } __rte_packed;
 
-/* hwrm_cfa_pair_alloc_output (size:192b/24B) */
-struct hwrm_cfa_pair_alloc_output {
+/* hwrm_nvm_verify_update_output (size:128b/16B) */
+struct hwrm_nvm_verify_update_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -43132,18 +45335,10 @@ struct hwrm_cfa_pair_alloc_output {
 	uint16_t	seq_id;
 	/* The length of the response data in number of bytes. */
 	uint16_t	resp_len;
-	/* Only valid for modes 1 and 2. */
-	uint16_t	rx_cfa_code_a;
-	/* Only valid for modes 1 and 2. */
-	uint16_t	tx_cfa_action_a;
-	/* Only valid for mode 2. */
-	uint16_t	rx_cfa_code_b;
-	/* Only valid for mode 2. */
-	uint16_t	tx_cfa_action_b;
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM. This field should be read as '1'
+	 * is completely written to RAM.  This field should be read as '1'
 	 * to indicate that the output has been completely written.
 	 * When writing a command completion or response to an internal processor,
 	 * the order of writes has to be such that this field is written last.
@@ -43151,13 +45346,13 @@ struct hwrm_cfa_pair_alloc_output {
 	uint8_t	valid;
 } __rte_packed;
 
-/**********************
- * hwrm_cfa_pair_free *
- **********************/
+/***************************
+ * hwrm_nvm_install_update *
+ ***************************/
 
 
-/* hwrm_cfa_pair_free_input (size:448b/56B) */
-struct hwrm_cfa_pair_free_input {
+/* hwrm_nvm_install_update_input (size:192b/24B) */
+struct hwrm_nvm_install_update_input {
 	/* The HWRM command request type. */
 	uint16_t	req_type;
 	/*
@@ -43186,40 +45381,181 @@ struct hwrm_cfa_pair_free_input {
 	 * point to a physically contiguous block of memory.
 	 */
 	uint64_t	resp_addr;
-	/* VF Pair name (32 byte string). */
-	char	pair_name[32];
-	/* Logical PF (0xff-PF for command channel). */
-	uint8_t	pf_b_id;
-	uint8_t	unused_0[3];
-	/* Logical VF number (range: 0 -> MAX_VFS -1). */
-	uint16_t	vf_id;
 	/*
-	 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
-	 *            5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
+	 * Installation type. If the value 3 through 0xffff is used,
+	 * only packaged items with that type value will be installed and
+	 * conditional installation directives for those packaged items
+	 * will be over-ridden (i.e. 'create' or 'replace' will be treated
+	 * as 'install').
 	 */
-	uint16_t	pair_mode;
-	/* Pair between VF on local host with PF or VF on specified host. */
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN          UINT32_C(0x0)
-	/* Pair between REP on local host with PF or VF on specified host. */
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN         UINT32_C(0x1)
-	/* Pair between REP on local host with REP on specified host. */
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP        UINT32_C(0x2)
-	/* Pair for the proxy interface. */
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY          UINT32_C(0x3)
-	/* Pair for the PF interface. */
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR         UINT32_C(0x4)
-	/* Modify existing rep2fn pair and move pair to new PF. */
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD     UINT32_C(0x5)
-	/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL  UINT32_C(0x6)
-	/* Truflow pair between REP on local host with PF or VF on specified host. */
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
-	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
-		HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
+	uint32_t	install_type;
+	/*
+	 * Perform a normal package installation. Conditional installation
+	 * directives (e.g. 'create' and 'replace') of packaged items
+	 * will be followed.
+	 */
+	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
+	/*
+	 * Install all packaged items regardless of installation directive
+	 * (i.e. treat all packaged items as though they have an installation
+	 * directive of 'install').
+	 */
+	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
+		UINT32_C(0xffffffff)
+	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
+		HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
+	uint16_t	flags;
+	/* If set to 1, then securely erase all unused locations in persistent storage. */
+	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
+		UINT32_C(0x1)
+	/*
+	 * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
+	 * When combined with erase_unused_space then unspecified images will be securely erased.
+	 */
+	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
+		UINT32_C(0x2)
+	/*
+	 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
+	 * Allow additional time for this command to complete if this bit is set to 1.
+	 */
+	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
+		UINT32_C(0x4)
+	/*
+	 * If set to 1, FW will verify the package in the "UPDATE" NVM item
+	 * without installing it. This flag is for FW internal use only.
+	 * Users should not set this flag. The request will otherwise fail.
+	 */
+	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
+		UINT32_C(0x8)
+	uint8_t	unused_0[2];
 } __rte_packed;
 
-/* hwrm_cfa_pair_free_output (size:128b/16B) */
-struct hwrm_cfa_pair_free_output {
+/* hwrm_nvm_install_update_output (size:192b/24B) */
+struct hwrm_nvm_install_update_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/*
+	 * Bit-mask of successfully installed items.
+	 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
+	 * A value of 0 indicates that no items were successfully installed.
+	 */
+	uint64_t	installed_items;
+	/* result is 8 b */
+	uint8_t	result;
+	/* There was no problem with the package installation. */
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
+		HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
+	/* problem_item is 8 b */
+	uint8_t	problem_item;
+	/* There was no problem with any packaged items. */
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
+		UINT32_C(0x0)
+	/* There was a problem with the NVM package itself. */
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
+		UINT32_C(0xff)
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
+		HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
+	/* reset_required is 8 b */
+	uint8_t	reset_required;
+	/*
+	 * No reset is required for installed/updated firmware or
+	 * microcode to take effect.
+	 */
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
+		UINT32_C(0x0)
+	/*
+	 * A PCIe reset (e.g. system reboot) is
+	 * required for newly installed/updated firmware or
+	 * microcode to take effect.
+	 */
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
+		UINT32_C(0x1)
+	/*
+	 * A controller power reset (e.g. system power-cycle) is
+	 * required for newly installed/updated firmware or
+	 * microcode to take effect. Some newly installed/updated
+	 * firmware or microcode may still take effect upon the
+	 * next PCIe reset.
+	 */
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
+		UINT32_C(0x2)
+	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
+		HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
+	uint8_t	unused_0[4];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
+struct hwrm_nvm_install_update_cmd_err {
+	/*
+	 * command specific error codes that goes to
+	 * the cmd_err field in Common HWRM Error Response.
+	 */
+	uint8_t	code;
+	/* Unknown error */
+	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN  UINT32_C(0x0)
+	/* Unable to complete operation due to fragmentation */
+	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
+	/* nvm is completely full. */
+	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
+	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
+		HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
+	uint8_t	unused_0[7];
+} __rte_packed;
+
+/******************
+ * hwrm_nvm_flush *
+ ******************/
+
+
+/* hwrm_nvm_flush_input (size:128b/16B) */
+struct hwrm_nvm_flush_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+} __rte_packed;
+
+/* hwrm_nvm_flush_output (size:128b/16B) */
+struct hwrm_nvm_flush_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
 	/* The HWRM command request type. */
@@ -43231,7 +45567,7 @@ struct hwrm_cfa_pair_free_output {
 	uint8_t	unused_0[7];
 	/*
 	 * This field is used in Output records to indicate that the output
-	 * is completely written to RAM. This field should be read as '1'
+	 * is completely written to RAM.  This field should be read as '1'
 	 * to indicate that the output has been completely written.
 	 * When writing a command completion or response to an internal processor,
 	 * the order of writes has to be such that this field is written last.
@@ -43239,4 +45575,743 @@ struct hwrm_cfa_pair_free_output {
 	uint8_t	valid;
 } __rte_packed;
 
+/* hwrm_nvm_flush_cmd_err (size:64b/8B) */
+struct hwrm_nvm_flush_cmd_err {
+	/*
+	 * command specific error codes that goes to
+	 * the cmd_err field in Common HWRM Error Response.
+	 */
+	uint8_t	code;
+	/* Unknown error */
+	#define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+	/* flush could not be performed */
+	#define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL    UINT32_C(0x1)
+	#define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
+		HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
+	uint8_t	unused_0[7];
+} __rte_packed;
+
+/*************************
+ * hwrm_nvm_get_variable *
+ *************************/
+
+
+/* hwrm_nvm_get_variable_input (size:320b/40B) */
+struct hwrm_nvm_get_variable_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/*
+	 * This is the host address where
+	 * nvm variable will be stored
+	 */
+	uint64_t	dest_data_addr;
+	/* size of data in bits */
+	uint16_t	data_len;
+	/* nvm cfg option number */
+	uint16_t	option_num;
+	/* reserved. */
+	#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0    UINT32_C(0x0)
+	/* reserved. */
+	#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
+		UINT32_C(0xffff)
+	#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
+		HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
+	/*
+	 * Number of dimensions for this nvm configuration variable.
+	 * This value indicates how many of the indexN values to use.
+	 * A value of 0 means that none of the indexN values are valid.
+	 * A value of 1 requires at index0 is valued, a value of 2
+	 * requires that index0 and index1 are valid, and so forth
+	 */
+	uint16_t	dimensions;
+	/* index for the 1st dimensions */
+	uint16_t	index_0;
+	/* index for the 2nd dimensions */
+	uint16_t	index_1;
+	/* index for the 3rd dimensions */
+	uint16_t	index_2;
+	/* index for the 4th dimensions */
+	uint16_t	index_3;
+	uint8_t	flags;
+	/*
+	 * When this bit is set to 1, the factory default value will be returned,
+	 * 0 returns the operational value.
+	 */
+	#define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
+		UINT32_C(0x1)
+	uint8_t	unused_0;
+} __rte_packed;
+
+/* hwrm_nvm_get_variable_output (size:128b/16B) */
+struct hwrm_nvm_get_variable_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* size of data of the actual variable retrieved in bits */
+	uint16_t	data_len;
+	/*
+	 * option_num is the option number for the data retrieved.  It is possible in the
+	 * future that the option number returned would be different than requested.  This
+	 * condition could occur if an option is deprecated and a new option id is defined
+	 * with similar characteristics, but has a slightly different definition.  This
+	 * also makes it convenient for the caller to identify the variable result with
+	 * the option id from the response.
+	 */
+	uint16_t	option_num;
+	/* reserved. */
+	#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0    UINT32_C(0x0)
+	/* reserved. */
+	#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
+		UINT32_C(0xffff)
+	#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
+		HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
+	uint8_t	unused_0[3];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
+struct hwrm_nvm_get_variable_cmd_err {
+	/*
+	 * command specific error codes that goes to
+	 * the cmd_err field in Common HWRM Error Response.
+	 */
+	uint8_t	code;
+	/* Unknown error */
+	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN       UINT32_C(0x0)
+	/* variable does not exist */
+	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
+	/* configuration is corrupted and the variable cannot be saved */
+	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   UINT32_C(0x2)
+	/* length specified is too small */
+	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
+	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
+		HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
+	uint8_t	unused_0[7];
+} __rte_packed;
+
+/*************************
+ * hwrm_nvm_set_variable *
+ *************************/
+
+
+/* hwrm_nvm_set_variable_input (size:320b/40B) */
+struct hwrm_nvm_set_variable_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/*
+	 * This is the host address where
+	 * nvm variable will be copied from
+	 */
+	uint64_t	src_data_addr;
+	/* size of data in bits */
+	uint16_t	data_len;
+	/* nvm cfg option number */
+	uint16_t	option_num;
+	/* reserved. */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0    UINT32_C(0x0)
+	/* reserved. */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
+		UINT32_C(0xffff)
+	#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
+		HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
+	/*
+	 * Number of dimensions for this nvm configuration variable.
+	 * This value indicates how many of the indexN values to use.
+	 * A value of 0 means that none of the indexN values are valid.
+	 * A value of 1 requires at index0 is valued, a value of 2
+	 * requires that index0 and index1 are valid, and so forth
+	 */
+	uint16_t	dimensions;
+	/* index for the 1st dimensions */
+	uint16_t	index_0;
+	/* index for the 2nd dimensions */
+	uint16_t	index_1;
+	/* index for the 3rd dimensions */
+	uint16_t	index_2;
+	/* index for the 4th dimensions */
+	uint16_t	index_3;
+	uint8_t	flags;
+	/* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
+		UINT32_C(0x1)
+	/* encryption method */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
+		UINT32_C(0xe)
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT           1
+	/* No encryption. */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
+		(UINT32_C(0x0) << 1)
+	/* one-way encryption. */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
+		(UINT32_C(0x1) << 1)
+	/* symmetric AES256 encryption. */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
+		(UINT32_C(0x2) << 1)
+	/* SHA1 digest appended to plaintext contents, for authentication */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
+		(UINT32_C(0x3) << 1)
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
+		HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
+		UINT32_C(0x70)
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT         4
+	/* When this bit is 1, update the factory default region */
+	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
+		UINT32_C(0x80)
+	uint8_t	unused_0;
+} __rte_packed;
+
+/* hwrm_nvm_set_variable_output (size:128b/16B) */
+struct hwrm_nvm_set_variable_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
+struct hwrm_nvm_set_variable_cmd_err {
+	/*
+	 * command specific error codes that goes to
+	 * the cmd_err field in Common HWRM Error Response.
+	 */
+	uint8_t	code;
+	/* Unknown error */
+	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN       UINT32_C(0x0)
+	/* variable does not exist */
+	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
+	/* configuration is corrupted and the variable cannot be saved */
+	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   UINT32_C(0x2)
+	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
+		HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
+	uint8_t	unused_0[7];
+} __rte_packed;
+
+/****************************
+ * hwrm_nvm_validate_option *
+ ****************************/
+
+
+/* hwrm_nvm_validate_option_input (size:320b/40B) */
+struct hwrm_nvm_validate_option_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/*
+	 * This is the host address where
+	 * nvm variable will be copied from
+	 */
+	uint64_t	src_data_addr;
+	/* size of data in bits */
+	uint16_t	data_len;
+	/* nvm cfg option number */
+	uint16_t	option_num;
+	/* reserved. */
+	#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
+		UINT32_C(0x0)
+	/* reserved. */
+	#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
+		UINT32_C(0xffff)
+	#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
+		HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
+	/*
+	 * Number of dimensions for this nvm configuration variable.
+	 * This value indicates how many of the indexN values to use.
+	 * A value of 0 means that none of the indexN values are valid.
+	 * A value of 1 requires at index0 is valued, a value of 2
+	 * requires that index0 and index1 are valid, and so forth
+	 */
+	uint16_t	dimensions;
+	/* index for the 1st dimensions */
+	uint16_t	index_0;
+	/* index for the 2nd dimensions */
+	uint16_t	index_1;
+	/* index for the 3rd dimensions */
+	uint16_t	index_2;
+	/* index for the 4th dimensions */
+	uint16_t	index_3;
+	uint8_t	unused_0[2];
+} __rte_packed;
+
+/* hwrm_nvm_validate_option_output (size:128b/16B) */
+struct hwrm_nvm_validate_option_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	result;
+	/* indicates that the value provided for the option is not matching with the saved data. */
+	#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
+	/* indicates that the value provided for the option is matching the saved data. */
+	#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH     UINT32_C(0x1)
+	#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
+		HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
+	uint8_t	unused_0[6];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
+struct hwrm_nvm_validate_option_cmd_err {
+	/*
+	 * command specific error codes that goes to
+	 * the cmd_err field in Common HWRM Error Response.
+	 */
+	uint8_t	code;
+	/* Unknown error */
+	#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+	#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
+		HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
+	uint8_t	unused_0[7];
+} __rte_packed;
+
+/****************
+ * hwrm_oem_cmd *
+ ****************/
+
+
+/* hwrm_oem_cmd_input (size:1024b/128B) */
+struct hwrm_oem_cmd_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	uint32_t	IANA;
+	uint32_t	unused_0;
+	/* This field contains the vendor specific command data. */
+	uint32_t	oem_data[26];
+} __rte_packed;
+
+/* hwrm_oem_cmd_output (size:768b/96B) */
+struct hwrm_oem_cmd_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint32_t	IANA;
+	uint32_t	unused_0;
+	/* This field contains the vendor specific response data. */
+	uint32_t	oem_data[18];
+	uint8_t	unused_1[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/*****************
+ * hwrm_fw_reset *
+ ******************/
+
+
+/* hwrm_fw_reset_input (size:192b/24B) */
+struct hwrm_fw_reset_input {
+	/* The HWRM command request type. */
+	uint16_t        req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t        cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t        seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFE - Reserved for internal processors
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t        target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t        resp_addr;
+	/* Type of embedded processor. */
+	uint8_t embedded_proc_type;
+	/* Boot Processor */
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
+		UINT32_C(0x0)
+	/* Management Processor */
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
+		UINT32_C(0x1)
+	/* Network control processor */
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
+		UINT32_C(0x2)
+	/* RoCE control processor */
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
+		UINT32_C(0x3)
+	/*
+	 * Host (in multi-host environment): This is only valid if requester is IPC.
+	 * Reinit host hardware resources and PCIe.
+	 */
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
+		UINT32_C(0x4)
+	/* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
+		UINT32_C(0x5)
+	/* Reset all blocks of the chip (including all processors) */
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
+		UINT32_C(0x6)
+	/*
+	 * Host (in multi-host environment): This is only valid if requester is IPC.
+	 * Reinit host hardware resources.
+	 */
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
+		UINT32_C(0x7)
+	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
+		HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
+	/* Type of self reset. */
+	uint8_t selfrst_status;
+	/* No Self Reset */
+	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
+		UINT32_C(0x0)
+	/* Self Reset as soon as possible to do so safely */
+	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
+		UINT32_C(0x1)
+	/* Self Reset on PCIe Reset */
+	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
+		UINT32_C(0x2)
+	/* Self Reset immediately after notification to all clients. */
+	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
+		UINT32_C(0x3)
+	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
+		HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
+	/*
+	 * Indicate which host is being reset. 0 means first host.
+	 * Only valid when embedded_proc_type is host in multihost
+	 * environment
+	 */
+	uint8_t host_idx;
+	uint8_t flags;
+	/*
+	 * When this bit is '1', then the core firmware initiates
+	 * the reset only after graceful shut down of all registered instances.
+	 * If not, the device will continue with the existing firmware.
+	 */
+	#define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL     UINT32_C(0x1)
+	uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_fw_reset_output (size:128b/16B) */
+struct hwrm_fw_reset_output {
+	/* The specific error status for the command. */
+	uint16_t        error_code;
+	/* The HWRM command request type. */
+	uint16_t        req_type;
+	/* The sequence ID from the original command. */
+	uint16_t        seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t        resp_len;
+	/* Type of self reset. */
+	uint8_t selfrst_status;
+	/* No Self Reset */
+	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
+		UINT32_C(0x0)
+	/* Self Reset as soon as possible to do so safely */
+	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
+		UINT32_C(0x1)
+	/* Self Reset on PCIe Reset */
+	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
+		UINT32_C(0x2)
+	/* Self Reset immediately after notification to all clients. */
+	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
+		UINT32_C(0x3)
+	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
+		HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
+	uint8_t unused_0[6];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_port_ts_query *
+ ***********************/
+
+
+/* hwrm_port_ts_query_input (size:192b/24B) */
+struct hwrm_port_ts_query_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	uint32_t	flags;
+	/*
+	 * Enumeration denoting the RX, TX type of the resource.
+	 * This enumeration is used for resources that are similar for both
+	 * TX and RX paths of the chip.
+	 */
+	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH		0x1UL
+	/* tx path */
+	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX		0x0UL
+	/* rx path */
+	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX		0x1UL
+	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST	\
+		HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
+	/*
+	 * If set, the response includes the current value of the free
+	 * running timer.
+	 */
+	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME	0x2UL
+	/* Port ID of port that is being queried. */
+	uint16_t	port_id;
+	uint8_t		unused_0[2];
+} __rte_packed;
+
+/* hwrm_port_ts_query_output (size:192b/24B) */
+struct hwrm_port_ts_query_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/*
+	 * Timestamp value of PTP message captured, or current value of
+	 * free running timer.
+	 */
+	uint32_t	ptp_msg_ts[2];
+	/* Sequence ID of the PTP message captured. */
+	uint16_t	ptp_msg_seqid;
+	uint8_t		unused_0[5];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM.  This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t		valid;
+} __rte_packed;
+
+/*
+ * This structure is fixed at the beginning of the ChiMP SRAM (GRC
+ * offset: 0x31001F0). Host software is expected to read from this
+ * location for a defined signature. If it exists, the software can
+ * assume the presence of this structure and the validity of the
+ * FW_STATUS location in the next field.
+ */
+/* hcomm_status (size:64b/8B) */
+struct hcomm_status {
+	uint32_t	sig_ver;
+	/*
+	 * This field defines the version of the structure. The latest
+	 * version value is 1.
+	 */
+	#define HCOMM_STATUS_VER_MASK		UINT32_C(0xff)
+	#define HCOMM_STATUS_VER_SFT		0
+	#define HCOMM_STATUS_VER_LATEST		UINT32_C(0x1)
+	#define HCOMM_STATUS_VER_LAST		HCOMM_STATUS_VER_LATEST
+	/*
+	 * This field is to store the signature value to indicate the
+	 * presence of the structure.
+	 */
+	#define HCOMM_STATUS_SIGNATURE_MASK	UINT32_C(0xffffff00)
+	#define HCOMM_STATUS_SIGNATURE_SFT	8
+	#define HCOMM_STATUS_SIGNATURE_VAL	(UINT32_C(0x484353) << 8)
+	#define HCOMM_STATUS_SIGNATURE_LAST	HCOMM_STATUS_SIGNATURE_VAL
+	uint32_t	fw_status_loc;
+	#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK	UINT32_C(0x3)
+	#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT	0
+	/* PCIE configuration space */
+	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG	UINT32_C(0x0)
+	/* GRC space */
+	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC	UINT32_C(0x1)
+	/* BAR0 space */
+	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0	UINT32_C(0x2)
+	/* BAR1 space */
+	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1	UINT32_C(0x3)
+	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST	\
+		HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
+	/*
+	 * This offset where the fw_status register is located. The value
+	 * is generally 4-byte aligned.
+	 */
+	#define HCOMM_STATUS_TRUE_OFFSET_MASK		UINT32_C(0xfffffffc)
+	#define HCOMM_STATUS_TRUE_OFFSET_SFT		2
+} __rte_packed;
+/* This is the GRC offset where the hcomm_status struct resides. */
+#define HCOMM_STATUS_STRUCT_LOC		0x31001F0UL
 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */
