From patchwork Tue Sep 29 12:01:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 79194 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E5BD1A04C0; Tue, 29 Sep 2020 14:04:12 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CC3E61DA93; Tue, 29 Sep 2020 14:01:42 +0200 (CEST) Received: from incedge.chinasoftinc.com (unknown [114.113.233.8]) by dpdk.org (Postfix) with ESMTP id BFAFB1DA21 for ; Tue, 29 Sep 2020 14:01:28 +0200 (CEST) X-ASG-Debug-ID: 1601380886-149d11049b2967d0001-TfluYd Received: from mail.chinasoftinc.com (inccas001.ito.icss [10.168.0.51]) by incedge.chinasoftinc.com with ESMTP id TXDSdeh8u4WRT6Lx (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 29 Sep 2020 20:01:26 +0800 (CST) X-Barracuda-Envelope-From: huwei013@chinasoftinc.com X-Barracuda-RBL-Trusted-Forwarder: 10.168.0.51 X-ASG-Whitelist: Client Received: from localhost.localdomain (120.133.139.157) by INCCAS001.ito.icss (10.168.0.60) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 20:01:26 +0800 From: "Wei Hu (Xavier)" X-Barracuda-RBL-Trusted-Forwarder: 10.168.0.60 To: CC: Date: Tue, 29 Sep 2020 20:01:16 +0800 X-ASG-Orig-Subj: [PATCH v2 8/9] net/hns3: check return value when reading PCI config space Message-ID: <20200929120117.50394-9-huwei013@chinasoftinc.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20200929120117.50394-1-huwei013@chinasoftinc.com> References: <20200929110945.70761-1-huwei013@chinasoftinc.com> <20200929120117.50394-1-huwei013@chinasoftinc.com> MIME-Version: 1.0 X-Originating-IP: [120.133.139.157] X-Barracuda-Connect: inccas001.ito.icss[10.168.0.51] X-Barracuda-Start-Time: 1601380886 X-Barracuda-Encrypted: ECDHE-RSA-AES256-SHA X-Barracuda-URL: https://incspam.chinasofti.com:443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at chinasoftinc.com X-Barracuda-Scan-Msg-Size: 4205 Subject: [dpdk-dev] [PATCH v2 8/9] net/hns3: check return value when reading PCI config space X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng This patch add return value check when calling rte_pci_read_config function. Fixes: cea37e513329 ("net/hns3: fix FLR reset") Cc: stable@dpdk.org Signed-off-by: Hongbo Zheng Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_ethdev_vf.c | 62 ++++++++++++++++++++++++++++++++------- 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 849f6cc..a6cc11d 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -64,12 +64,18 @@ static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr); /* set PCI bus mastering */ -static void +static int hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) { uint16_t reg; + int ret; - rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); + ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_COMMAND); + return ret; + } if (op) /* set the master bit */ @@ -77,7 +83,7 @@ hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) else reg &= ~(PCI_COMMAND_MASTER); - rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); + return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); } /** @@ -94,16 +100,34 @@ hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) uint8_t pos; uint8_t id; int ttl; + int ret; + + ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS); + return 0; + } - rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); if (!(status & PCI_STATUS_CAP_LIST)) return 0; ttl = MAX_PCIE_CAPABILITY; - rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST); + ret = rte_pci_read_config(device, &pos, sizeof(pos), + PCI_CAPABILITY_LIST); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_CAPABILITY_LIST); + return 0; + } + while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { - rte_pci_read_config(device, &id, sizeof(id), - (pos + PCI_CAP_LIST_ID)); + ret = rte_pci_read_config(device, &id, sizeof(id), + (pos + PCI_CAP_LIST_ID)); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + (pos + PCI_CAP_LIST_ID)); + break; + } if (id == 0xFF) break; @@ -111,8 +135,13 @@ hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) if (id == cap) return (int)pos; - rte_pci_read_config(device, &pos, sizeof(pos), - (pos + PCI_CAP_LIST_NEXT)); + ret = rte_pci_read_config(device, &pos, sizeof(pos), + (pos + PCI_CAP_LIST_NEXT)); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + (pos + PCI_CAP_LIST_NEXT)); + break; + } } return 0; } @@ -122,11 +151,18 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op) { uint16_t control; int pos; + int ret; pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); if (pos) { - rte_pci_read_config(device, &control, sizeof(control), + ret = rte_pci_read_config(device, &control, sizeof(control), (pos + PCI_MSIX_FLAGS)); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + (pos + PCI_MSIX_FLAGS)); + return -ENXIO; + } + if (op) control |= PCI_MSIX_FLAGS_ENABLE; else @@ -2574,7 +2610,11 @@ hns3vf_reinit_dev(struct hns3_adapter *hns) if (hw->reset.level == HNS3_VF_FULL_RESET) { rte_intr_disable(&pci_dev->intr_handle); - hns3vf_set_bus_master(pci_dev, true); + ret = hns3vf_set_bus_master(pci_dev, true); + if (ret) { + hns3_err(hw, "failed to set pci bus, ret = %d", ret); + return ret; + } } /* Firmware command initialize */