From patchwork Wed Sep 23 18:06:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Dumitrescu X-Patchwork-Id: 78622 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BFC82A04B1; Wed, 23 Sep 2020 20:13:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2678B1DD9B; Wed, 23 Sep 2020 20:08:37 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 33B951DA77 for ; Wed, 23 Sep 2020 20:07:38 +0200 (CEST) IronPort-SDR: g0NTl+LRZ0jm8HutnPImyd47/iYIIs6TFvGG8z6Xg6kTWyDHfcaRnxt/1GpOFoC8H6AZ2CaGj/ mMb29liVneuw== X-IronPort-AV: E=McAfee;i="6000,8403,9753"; a="245809614" X-IronPort-AV: E=Sophos;i="5.77,293,1596524400"; d="scan'208";a="245809614" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2020 11:07:37 -0700 IronPort-SDR: CAabT598Fut5RGau+nsWNHD2JbA+bW0lDdBo6TOOYqUO8lD2ytfJlh0cHfMu42cN19oQU5pxKh b/dSg9baZ5qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,293,1596524400"; d="scan'208";a="305478009" Received: from silpixa00400573.ir.intel.com (HELO silpixa00400573.ger.corp.intel.com) ([10.237.223.107]) by orsmga003.jf.intel.com with ESMTP; 23 Sep 2020 11:07:36 -0700 From: Cristian Dumitrescu To: dev@dpdk.org Cc: thomas@monjalon.net, david.marchand@redhat.com Date: Wed, 23 Sep 2020 19:06:44 +0100 Message-Id: <20200923180645.55852-41-cristian.dumitrescu@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200923180645.55852-1-cristian.dumitrescu@intel.com> References: <20200910152645.9342-2-cristian.dumitrescu@intel.com> <20200923180645.55852-1-cristian.dumitrescu@intel.com> Subject: [dpdk-dev] [PATCH v5 40/41] examples/pipeline: add l2fwd with MAC swap example X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add L2 Forwarding example with MAC destination and source address swap to the SWX pipeline application. Example command line: ./build/pipeline -l0-1 -- -s ./examples/l2fwd_macswp.cli Signed-off-by: Cristian Dumitrescu --- examples/pipeline/examples/l2fwd_macswp.cli | 25 ++++++++ examples/pipeline/examples/l2fwd_macswp.spec | 59 +++++++++++++++++++ .../pipeline/examples/l2fwd_macswp_pcap.cli | 20 +++++++ 3 files changed, 104 insertions(+) create mode 100644 examples/pipeline/examples/l2fwd_macswp.cli create mode 100644 examples/pipeline/examples/l2fwd_macswp.spec create mode 100644 examples/pipeline/examples/l2fwd_macswp_pcap.cli diff --git a/examples/pipeline/examples/l2fwd_macswp.cli b/examples/pipeline/examples/l2fwd_macswp.cli new file mode 100644 index 000000000..8031b2655 --- /dev/null +++ b/examples/pipeline/examples/l2fwd_macswp.cli @@ -0,0 +1,25 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2010-2020 Intel Corporation + +mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 + +link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK1 dev 0000:18:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK2 dev 0000:3b:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK3 dev 0000:3b:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on + +pipeline PIPELINE0 create 0 + +pipeline PIPELINE0 port in 0 link LINK0 rxq 0 bsz 32 +pipeline PIPELINE0 port in 1 link LINK1 rxq 0 bsz 32 +pipeline PIPELINE0 port in 2 link LINK2 rxq 0 bsz 32 +pipeline PIPELINE0 port in 3 link LINK3 rxq 0 bsz 32 + +pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32 +pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32 +pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32 +pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32 + +pipeline PIPELINE0 build ./examples/pipeline/examples/l2fwd_macswp.spec + +thread 1 pipeline PIPELINE0 enable diff --git a/examples/pipeline/examples/l2fwd_macswp.spec b/examples/pipeline/examples/l2fwd_macswp.spec new file mode 100644 index 000000000..e81f20622 --- /dev/null +++ b/examples/pipeline/examples/l2fwd_macswp.spec @@ -0,0 +1,59 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2020 Intel Corporation + +// +// Packet headers. +// +struct ethernet_h { + bit<48> dst_addr + bit<48> src_addr + bit<16> ether_type +} + +header ethernet instanceof ethernet_h + +// +// Packet meta-data. +// +struct metadata_t { + bit<32> port + bit<48> addr +} + +metadata instanceof metadata_t + +// +// Actions. +// +action macswp args none { + mov m.addr h.ethernet.dst_addr + mov h.ethernet.dst_addr h.ethernet.src_addr + mov h.ethernet.src_addr m.addr + return +} + +// +// Tables. +// +table stub { + key { + } + + actions { + macswp + } + + default_action macswp args none const +} + +// +// Pipeline. +// +apply { + rx m.port + extract h.ethernet + table stub + xor m.port 1 + emit h.ethernet + tx m.port +} diff --git a/examples/pipeline/examples/l2fwd_macswp_pcap.cli b/examples/pipeline/examples/l2fwd_macswp_pcap.cli new file mode 100644 index 000000000..9044d7d7f --- /dev/null +++ b/examples/pipeline/examples/l2fwd_macswp_pcap.cli @@ -0,0 +1,20 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2010-2020 Intel Corporation + +mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 + +pipeline PIPELINE0 create 0 + +pipeline PIPELINE0 port in 0 source MEMPOOL0 ./examples/packet.pcap +pipeline PIPELINE0 port in 1 source MEMPOOL0 ./examples/packet.pcap +pipeline PIPELINE0 port in 2 source MEMPOOL0 ./examples/packet.pcap +pipeline PIPELINE0 port in 3 source MEMPOOL0 ./examples/packet.pcap + +pipeline PIPELINE0 port out 0 sink none +pipeline PIPELINE0 port out 1 sink none +pipeline PIPELINE0 port out 2 sink none +pipeline PIPELINE0 port out 3 sink none + +pipeline PIPELINE0 build ./examples/l2fwd_macswp.spec + +thread 1 pipeline PIPELINE0 enable