From patchwork Tue Sep 1 11:50:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 76212 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 29968A04AC; Tue, 1 Sep 2020 13:52:57 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 230CD1C122; Tue, 1 Sep 2020 13:51:23 +0200 (CEST) Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by dpdk.org (Postfix) with ESMTP id CE67D1C0B7 for ; Tue, 1 Sep 2020 13:51:16 +0200 (CEST) X-QQ-mid: bizesmtp5t1598961072tiqcjjcx5 Received: from localhost.localdomain.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Tue, 01 Sep 2020 19:51:12 +0800 (CST) X-QQ-SSF: 01400000000000B0C000000A0000000 X-QQ-FEAT: HgcpZqDDs6Q5HwIo/sOmZCL2uG+ox1+zVowPkM5GpZpBxd6CwPGCK2BRNqMeC tg6Jm78CP1zRwkBtf8KYisiZiPZPch77Qms14USYtSBYvOQQIKL70GuJhMhuozIKtelk0nq 2B5NhXSNmJi7xcIECic4CJ4drdwhwzoFIc10Baa8diycGQUOWYSahXFiq2M4FeV0e67/6Wo A2+eB4SRpsTEhxnW8cRO0mMItbHRrPweYKUCLSPayx3ivvHqd1zU4gObefNLf4UGQtIn6SF UqnFPAMTXeTBUYtJjvlXMuPl4N/x480sQ6XWxrEgLEYKLcVMbwGbrgQQ1PzC0p9FGkvZ1L6 F7a00GUwC6QECed10PgAMPcvBpY7A== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Date: Tue, 1 Sep 2020 19:50:40 +0800 Message-Id: <20200901115113.1529675-9-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200901115113.1529675-1-jiawenwu@trustnetic.com> References: <20200901115113.1529675-1-jiawenwu@trustnetic.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign5 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH v1 09/42] net/txgbe: add PHY init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add phy init functions, get phy type and identify. Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/meson.build | 1 + drivers/net/txgbe/base/txgbe.h | 1 + drivers/net/txgbe/base/txgbe_hw.c | 57 +++++ drivers/net/txgbe/base/txgbe_hw.h | 2 + drivers/net/txgbe/base/txgbe_phy.c | 253 +++++++++++++++++++++ drivers/net/txgbe/base/txgbe_phy.h | 336 ++++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_type.h | 7 + 7 files changed, 657 insertions(+) create mode 100644 drivers/net/txgbe/base/txgbe_phy.c create mode 100644 drivers/net/txgbe/base/txgbe_phy.h diff --git a/drivers/net/txgbe/base/meson.build b/drivers/net/txgbe/base/meson.build index 94cdfcfc1..069879a7c 100644 --- a/drivers/net/txgbe/base/meson.build +++ b/drivers/net/txgbe/base/meson.build @@ -5,6 +5,7 @@ sources = [ 'txgbe_eeprom.c', 'txgbe_hw.c', 'txgbe_mng.c', + 'txgbe_phy.c', 'txgbe_vf.c', ] diff --git a/drivers/net/txgbe/base/txgbe.h b/drivers/net/txgbe/base/txgbe.h index 329764be0..764caa439 100644 --- a/drivers/net/txgbe/base/txgbe.h +++ b/drivers/net/txgbe/base/txgbe.h @@ -8,6 +8,7 @@ #include "txgbe_type.h" #include "txgbe_mng.h" #include "txgbe_eeprom.h" +#include "txgbe_phy.h" #include "txgbe_hw.h" #endif /* _TXGBE_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 9a77adc72..8090d68f9 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -3,6 +3,7 @@ */ #include "txgbe_type.h" +#include "txgbe_phy.h" #include "txgbe_vf.h" #include "txgbe_eeprom.h" #include "txgbe_mng.h" @@ -138,6 +139,8 @@ s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, wr32(hw, TXGBE_ETHADDRIDX, index); wr32(hw, TXGBE_ETHADDRL, rar_low); wr32(hw, TXGBE_ETHADDRH, rar_high); + + return 0; } /** @@ -273,6 +276,55 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw) return err; } +void txgbe_init_mac_link_ops(struct txgbe_hw *hw) +{ + struct txgbe_mac_info *mac = &hw->mac; + + DEBUGFUNC("txgbe_init_mac_link_ops"); + + /* + * enable the laser control functions for SFP+ fiber + * and MNG not enabled + */ + RTE_SET_USED(mac); +} + +/** + * txgbe_init_phy_raptor - PHY/SFP specific init + * @hw: pointer to hardware structure + * + * Initialize any function pointers that were not able to be + * set during init_shared_code because the PHY/SFP type was + * not known. Perform the SFP init if necessary. + * + **/ +s32 txgbe_init_phy_raptor(struct txgbe_hw *hw) +{ + struct txgbe_phy_info *phy = &hw->phy; + s32 err = 0; + + DEBUGFUNC("txgbe_init_phy_raptor"); + + if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) { + /* Store flag indicating I2C bus access control unit. */ + hw->phy.qsfp_shared_i2c_bus = TRUE; + + /* Initialize access to QSFP+ I2C bus */ + txgbe_flush(hw); + } + + /* Identify the PHY or SFP module */ + err = phy->identify(hw); + if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) + goto init_phy_ops_out; + + /* Setup function pointers based on detected SFP module and speeds */ + txgbe_init_mac_link_ops(hw); + +init_phy_ops_out: + return err; +} + /** * txgbe_init_ops_pf - Inits func ptrs and MAC type * @hw: pointer to hardware structure @@ -283,8 +335,13 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw) s32 txgbe_init_ops_pf(struct txgbe_hw *hw) { struct txgbe_mac_info *mac = &hw->mac; + struct txgbe_phy_info *phy = &hw->phy; struct txgbe_rom_info *rom = &hw->rom; + /* PHY */ + phy->identify = txgbe_identify_phy; + phy->init = txgbe_init_phy_raptor; + /* MAC */ mac->init_hw = txgbe_init_hw; mac->start_hw = txgbe_start_hw_raptor; diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index a2816c40a..a70b0340a 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -21,6 +21,8 @@ void txgbe_clear_tx_pending(struct txgbe_hw *hw); s32 txgbe_init_shared_code(struct txgbe_hw *hw); s32 txgbe_set_mac_type(struct txgbe_hw *hw); s32 txgbe_init_ops_pf(struct txgbe_hw *hw); +void txgbe_init_mac_link_ops(struct txgbe_hw *hw); s32 txgbe_reset_hw(struct txgbe_hw *hw); s32 txgbe_start_hw_raptor(struct txgbe_hw *hw); +s32 txgbe_init_phy_raptor(struct txgbe_hw *hw); #endif /* _TXGBE_HW_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c new file mode 100644 index 000000000..f2f79475c --- /dev/null +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015-2020 + */ + +#include "txgbe_hw.h" +#include "txgbe_eeprom.h" +#include "txgbe_mng.h" +#include "txgbe_phy.h" + +/** + * txgbe_identify_extphy - Identify a single address for a PHY + * @hw: pointer to hardware structure + * @phy_addr: PHY address to probe + * + * Returns true if PHY found + */ +static bool txgbe_identify_extphy(struct txgbe_hw *hw) +{ + u16 phy_addr = 0; + + if (!txgbe_validate_phy_addr(hw, phy_addr)) { + DEBUGOUT("Unable to validate PHY address 0x%04X\n", + phy_addr); + return false; + } + + if (txgbe_get_phy_id(hw)) + return false; + + hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id); + if (hw->phy.type == txgbe_phy_unknown) { + u16 ext_ability = 0; + hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY, + TXGBE_MD_DEV_PMA_PMD, + &ext_ability); + + if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY | + TXGBE_MD_PHY_1000BASET_ABILITY)) + hw->phy.type = txgbe_phy_cu_unknown; + else + hw->phy.type = txgbe_phy_generic; + } + + return true; +} + +/** + * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register + * @hw: pointer to hardware structure + * + * Read TXGBE_ETHPHYIF register and save field values, and check for valid field + * values. + **/ +static s32 txgbe_read_phy_if(struct txgbe_hw *hw) +{ + hw->phy.media_type = hw->phy.get_media_type(hw); + + /* Save NW management interface connected on board. This is used + * to determine internal PHY mode. + */ + hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF); + + /* If MDIO is connected to external PHY, then set PHY address. */ + if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT) { + hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel); + } + + if (!hw->phy.phy_semaphore_mask) { + if (hw->bus.lan_id) + hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY; + else + hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY; + } + + return 0; +} + +/** + * txgbe_identify_phy - Get physical layer module + * @hw: pointer to hardware structure + * + * Determines the physical layer module found on the current adapter. + **/ +s32 txgbe_identify_phy(struct txgbe_hw *hw) +{ + s32 err = TXGBE_ERR_PHY_ADDR_INVALID; + + DEBUGFUNC("txgbe_identify_phy"); + + txgbe_read_phy_if(hw); + + if (hw->phy.type != txgbe_phy_unknown) + return 0; + + /* Raptor 10GBASE-T requires an external PHY */ + if (hw->phy.media_type == txgbe_media_type_copper) { + err = txgbe_identify_extphy(hw); + } else if (hw->phy.media_type == txgbe_media_type_fiber) { + err = txgbe_identify_module(hw); + } else { + hw->phy.type = txgbe_phy_none; + return 0; + } + + /* Return error if SFP module has been detected but is not supported */ + if (hw->phy.type == txgbe_phy_sfp_unsupported) + return TXGBE_ERR_SFP_NOT_SUPPORTED; + + return err; +} + +/** + * txgbe_validate_phy_addr - Determines phy address is valid + * @hw: pointer to hardware structure + * @phy_addr: PHY address + * + **/ +bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr) +{ + u16 phy_id = 0; + bool valid = false; + + DEBUGFUNC("txgbe_validate_phy_addr"); + + hw->phy.addr = phy_addr; + hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH, + TXGBE_MD_DEV_PMA_PMD, &phy_id); + + if (phy_id != 0xFFFF && phy_id != 0x0) + valid = true; + + DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id); + + return valid; +} + +/** + * txgbe_get_phy_id - Get the phy type + * @hw: pointer to hardware structure + * + **/ +s32 txgbe_get_phy_id(struct txgbe_hw *hw) +{ + u32 err; + u16 phy_id_high = 0; + u16 phy_id_low = 0; + + DEBUGFUNC("txgbe_get_phy_id"); + + err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH, + TXGBE_MD_DEV_PMA_PMD, + &phy_id_high); + + if (err == 0) { + hw->phy.id = (u32)(phy_id_high << 16); + err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW, + TXGBE_MD_DEV_PMA_PMD, + &phy_id_low); + hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK); + hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK); + } + DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", + phy_id_high, phy_id_low); + + return err; +} + +/** + * txgbe_get_phy_type_from_id - Get the phy type + * @phy_id: PHY ID information + * + **/ +enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id) +{ + enum txgbe_phy_type phy_type; + + DEBUGFUNC("txgbe_get_phy_type_from_id"); + + switch (phy_id) { + case TXGBE_PHYID_TN1010: + phy_type = txgbe_phy_tn; + break; + case TXGBE_PHYID_QT2022: + phy_type = txgbe_phy_qt; + break; + case TXGBE_PHYID_ATH: + phy_type = txgbe_phy_nl; + break; + case TXGBE_PHYID_MTD3310: + phy_type = txgbe_phy_cu_mtd; + break; + default: + phy_type = txgbe_phy_unknown; + break; + } + + return phy_type; +} + +/** + * txgbe_identify_module - Identifies module type + * @hw: pointer to hardware structure + * + * Determines HW type and calls appropriate function. + **/ +s32 txgbe_identify_module(struct txgbe_hw *hw) +{ + s32 err = TXGBE_ERR_SFP_NOT_PRESENT; + + DEBUGFUNC("txgbe_identify_module"); + + switch (hw->phy.media_type) { + case txgbe_media_type_fiber: + err = txgbe_identify_sfp_module(hw); + break; + + case txgbe_media_type_fiber_qsfp: + err = txgbe_identify_qsfp_module(hw); + break; + + default: + hw->phy.sfp_type = txgbe_sfp_type_not_present; + err = TXGBE_ERR_SFP_NOT_PRESENT; + break; + } + + return err; +} + +/** + * txgbe_identify_sfp_module - Identifies SFP modules + * @hw: pointer to hardware structure + * + * Searches for and identifies the SFP module and assigns appropriate PHY type. + **/ +s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) +{ + RTE_SET_USED(hw); + return 0; +} + +/** + * txgbe_identify_qsfp_module - Identifies QSFP modules + * @hw: pointer to hardware structure + * + * Searches for and identifies the QSFP module and assigns appropriate PHY type + **/ +s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw) +{ + RTE_SET_USED(hw); + return 0; +} + diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h new file mode 100644 index 000000000..73ed734b2 --- /dev/null +++ b/drivers/net/txgbe/base/txgbe_phy.h @@ -0,0 +1,336 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015-2020 + */ + +#ifndef _TXGBE_PHY_H_ +#define _TXGBE_PHY_H_ + +#include "txgbe_type.h" + +#define TXGBE_SFP_DETECT_RETRIES 10 +#define TXGBE_MD_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ + + +/* ETH PHY Registers */ +#define SR_XS_PCS_MMD_STATUS1 0x030001 +#define SR_XS_PCS_CTRL2 0x030007 +#define SR_PCS_CTRL2_TYPE_SEL MS16(0, 0x3) +#define SR_PCS_CTRL2_TYPE_SEL_R LS16(0, 0, 0x3) +#define SR_PCS_CTRL2_TYPE_SEL_X LS16(1, 0, 0x3) +#define SR_PCS_CTRL2_TYPE_SEL_W LS16(2, 0, 0x3) +#define SR_PMA_CTRL1 0x010000 +#define SR_PMA_CTRL1_SS13 MS16(13, 0x1) +#define SR_PMA_CTRL1_SS13_KX LS16(0, 13, 0x1) +#define SR_PMA_CTRL1_SS13_KX4 LS16(1, 13, 0x1) +#define SR_PMA_CTRL1_LB MS16(0, 0x1) +#define SR_MII_MMD_CTL 0x1F0000 +#define SR_MII_MMD_CTL_AN_EN 0x1000 +#define SR_MII_MMD_CTL_RESTART_AN 0x0200 +#define SR_MII_MMD_DIGI_CTL 0x1F8000 +#define SR_MII_MMD_AN_CTL 0x1F8001 +#define SR_MII_MMD_AN_ADV 0x1F0004 +#define SR_MII_MMD_AN_ADV_PAUSE(v) ((0x3 & (v)) << 7) +#define SR_MII_MMD_AN_ADV_PAUSE_ASM 0x80 +#define SR_MII_MMD_AN_ADV_PAUSE_SYM 0x100 +#define SR_MII_MMD_LP_BABL 0x1F0005 +#define SR_AN_CTRL 0x070000 +#define SR_AN_CTRL_RSTRT_AN MS16(9, 0x1) +#define SR_AN_CTRL_AN_EN MS16(12, 0x1) +#define SR_AN_MMD_ADV_REG1 0x070010 +#define SR_AN_MMD_ADV_REG1_PAUSE(v) ((0x3 & (v)) << 10) +#define SR_AN_MMD_ADV_REG1_PAUSE_SYM 0x400 +#define SR_AN_MMD_ADV_REG1_PAUSE_ASM 0x800 +#define SR_AN_MMD_ADV_REG2 0x070011 +#define SR_AN_MMD_ADV_REG2_BP_TYPE_KX4 0x40 +#define SR_AN_MMD_ADV_REG2_BP_TYPE_KX 0x20 +#define SR_AN_MMD_ADV_REG2_BP_TYPE_KR 0x80 +#define SR_AN_MMD_ADV_REG2_BP_TYPE_MASK 0xFFFF +#define SR_AN_MMD_LP_ABL1 0x070013 +#define VR_AN_KR_MODE_CL 0x078003 +#define VR_XS_OR_PCS_MMD_DIGI_CTL1 0x038000 +#define VR_XS_OR_PCS_MMD_DIGI_CTL1_ENABLE 0x1000 +#define VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST 0x8000 +#define VR_XS_OR_PCS_MMD_DIGI_STATUS 0x038010 +#define VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK 0x1C +#define VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD 0x10 + +#define TXGBE_PHY_MPLLA_CTL0 0x018071 +#define TXGBE_PHY_MPLLA_CTL3 0x018077 +#define TXGBE_PHY_MISC_CTL0 0x018090 +#define TXGBE_PHY_VCO_CAL_LD0 0x018092 +#define TXGBE_PHY_VCO_CAL_LD1 0x018093 +#define TXGBE_PHY_VCO_CAL_LD2 0x018094 +#define TXGBE_PHY_VCO_CAL_LD3 0x018095 +#define TXGBE_PHY_VCO_CAL_REF0 0x018096 +#define TXGBE_PHY_VCO_CAL_REF1 0x018097 +#define TXGBE_PHY_RX_AD_ACK 0x018098 +#define TXGBE_PHY_AFE_DFE_ENABLE 0x01805D +#define TXGBE_PHY_DFE_TAP_CTL0 0x01805E +#define TXGBE_PHY_RX_EQ_ATT_LVL0 0x018057 +#define TXGBE_PHY_RX_EQ_CTL0 0x018058 +#define TXGBE_PHY_RX_EQ_CTL 0x01805C +#define TXGBE_PHY_TX_EQ_CTL0 0x018036 +#define TXGBE_PHY_TX_EQ_CTL1 0x018037 +#define TXGBE_PHY_TX_RATE_CTL 0x018034 +#define TXGBE_PHY_RX_RATE_CTL 0x018054 +#define TXGBE_PHY_TX_GEN_CTL2 0x018032 +#define TXGBE_PHY_RX_GEN_CTL2 0x018052 +#define TXGBE_PHY_RX_GEN_CTL3 0x018053 +#define TXGBE_PHY_MPLLA_CTL2 0x018073 +#define TXGBE_PHY_RX_POWER_ST_CTL 0x018055 +#define TXGBE_PHY_TX_POWER_ST_CTL 0x018035 +#define TXGBE_PHY_TX_GENCTRL1 0x018031 + +#define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX 32 +#define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_10GBASER_KR 33 +#define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER 40 +#define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_MASK 0xFF +#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX 0x46 +#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR 0x7B +#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER 0x56 +#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_MASK 0x7FF +#define TXGBE_PHY_MISC_CTL0_TX2RX_LB_EN_0 0x1 +#define TXGBE_PHY_MISC_CTL0_TX2RX_LB_EN_3_1 0xE +#define TXGBE_PHY_MISC_CTL0_RX_VREF_CTRL 0x1F00 +#define TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX 1344 +#define TXGBE_PHY_VCO_CAL_LD0_10GBASER_KR 1353 +#define TXGBE_PHY_VCO_CAL_LD0_OTHER 1360 +#define TXGBE_PHY_VCO_CAL_LD0_MASK 0x1000 +#define TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX 42 +#define TXGBE_PHY_VCO_CAL_REF0_LD0_10GBASER_KR 41 +#define TXGBE_PHY_VCO_CAL_REF0_LD0_OTHER 34 +#define TXGBE_PHY_VCO_CAL_REF0_LD0_MASK 0x3F +#define TXGBE_PHY_AFE_DFE_ENABLE_DFE_EN0 0x10 +#define TXGBE_PHY_AFE_DFE_ENABLE_AFE_EN0 0x1 +#define TXGBE_PHY_AFE_DFE_ENABLE_MASK 0xFF +#define TXGBE_PHY_RX_EQ_CTL_CONT_ADAPT0 0x1 +#define TXGBE_PHY_RX_EQ_CTL_CONT_ADAPT_MASK 0xF +#define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_10GBASER_KR 0x0 +#define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_RXAUI 0x1 +#define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX 0x3 +#define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_OTHER 0x2 +#define TXGBE_PHY_TX_RATE_CTL_TX1_RATE_OTHER 0x20 +#define TXGBE_PHY_TX_RATE_CTL_TX2_RATE_OTHER 0x200 +#define TXGBE_PHY_TX_RATE_CTL_TX3_RATE_OTHER 0x2000 +#define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_MASK 0x7 +#define TXGBE_PHY_TX_RATE_CTL_TX1_RATE_MASK 0x70 +#define TXGBE_PHY_TX_RATE_CTL_TX2_RATE_MASK 0x700 +#define TXGBE_PHY_TX_RATE_CTL_TX3_RATE_MASK 0x7000 +#define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_10GBASER_KR 0x0 +#define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_RXAUI 0x1 +#define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX 0x3 +#define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_OTHER 0x2 +#define TXGBE_PHY_RX_RATE_CTL_RX1_RATE_OTHER 0x20 +#define TXGBE_PHY_RX_RATE_CTL_RX2_RATE_OTHER 0x200 +#define TXGBE_PHY_RX_RATE_CTL_RX3_RATE_OTHER 0x2000 +#define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_MASK 0x7 +#define TXGBE_PHY_RX_RATE_CTL_RX1_RATE_MASK 0x70 +#define TXGBE_PHY_RX_RATE_CTL_RX2_RATE_MASK 0x700 +#define TXGBE_PHY_RX_RATE_CTL_RX3_RATE_MASK 0x7000 +#define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_10GBASER_KR 0x200 +#define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_10GBASER_KR_RXAUI 0x300 +#define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER 0x100 +#define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_MASK 0x300 +#define TXGBE_PHY_TX_GEN_CTL2_TX1_WIDTH_OTHER 0x400 +#define TXGBE_PHY_TX_GEN_CTL2_TX1_WIDTH_MASK 0xC00 +#define TXGBE_PHY_TX_GEN_CTL2_TX2_WIDTH_OTHER 0x1000 +#define TXGBE_PHY_TX_GEN_CTL2_TX2_WIDTH_MASK 0x3000 +#define TXGBE_PHY_TX_GEN_CTL2_TX3_WIDTH_OTHER 0x4000 +#define TXGBE_PHY_TX_GEN_CTL2_TX3_WIDTH_MASK 0xC000 +#define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_10GBASER_KR 0x200 +#define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_10GBASER_KR_RXAUI 0x300 +#define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER 0x100 +#define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_MASK 0x300 +#define TXGBE_PHY_RX_GEN_CTL2_RX1_WIDTH_OTHER 0x400 +#define TXGBE_PHY_RX_GEN_CTL2_RX1_WIDTH_MASK 0xC00 +#define TXGBE_PHY_RX_GEN_CTL2_RX2_WIDTH_OTHER 0x1000 +#define TXGBE_PHY_RX_GEN_CTL2_RX2_WIDTH_MASK 0x3000 +#define TXGBE_PHY_RX_GEN_CTL2_RX3_WIDTH_OTHER 0x4000 +#define TXGBE_PHY_RX_GEN_CTL2_RX3_WIDTH_MASK 0xC000 +#define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_8 0x100 +#define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10 0x200 +#define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_16P5 0x400 +#define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_MASK 0x700 + +/****************************************************************************** + * SFP I2C Registers: + ******************************************************************************/ +/* SFP IDs: format of OUI is 0x[byte0][byte1][byte2][00] */ +#define TXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 +#define TXGBE_SFF_VENDOR_OUI_FTL 0x00906500 +#define TXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 +#define TXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 + +/* EEPROM (dev_addr = 0xA0) */ +#define TXGBE_I2C_EEPROM_DEV_ADDR 0xA0 +#define TXGBE_SFF_IDENTIFIER 0x00 +#define TXGBE_SFF_IDENTIFIER_SFP 0x03 +#define TXGBE_SFF_VENDOR_OUI_BYTE0 0x25 +#define TXGBE_SFF_VENDOR_OUI_BYTE1 0x26 +#define TXGBE_SFF_VENDOR_OUI_BYTE2 0x27 +#define TXGBE_SFF_1GBE_COMP_CODES 0x06 +#define TXGBE_SFF_10GBE_COMP_CODES 0x03 +#define TXGBE_SFF_CABLE_TECHNOLOGY 0x08 +#define TXGBE_SFF_CABLE_DA_PASSIVE 0x4 +#define TXGBE_SFF_CABLE_DA_ACTIVE 0x8 +#define TXGBE_SFF_CABLE_SPEC_COMP 0x3C +#define TXGBE_SFF_SFF_8472_SWAP 0x5C +#define TXGBE_SFF_SFF_8472_COMP 0x5E +#define TXGBE_SFF_SFF_8472_OSCB 0x6E +#define TXGBE_SFF_SFF_8472_ESCB 0x76 + +#define TXGBE_SFF_IDENTIFIER_QSFP_PLUS 0x0D +#define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5 +#define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6 +#define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7 +#define TXGBE_SFF_QSFP_CONNECTOR 0x82 +#define TXGBE_SFF_QSFP_10GBE_COMP 0x83 +#define TXGBE_SFF_QSFP_1GBE_COMP 0x86 +#define TXGBE_SFF_QSFP_CABLE_LENGTH 0x92 +#define TXGBE_SFF_QSFP_DEVICE_TECH 0x93 + +/* Bitmasks */ +#define TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 +#define TXGBE_SFF_1GBASESX_CAPABLE 0x1 +#define TXGBE_SFF_1GBASELX_CAPABLE 0x2 +#define TXGBE_SFF_1GBASET_CAPABLE 0x8 +#define TXGBE_SFF_10GBASESR_CAPABLE 0x10 +#define TXGBE_SFF_10GBASELR_CAPABLE 0x20 +#define TXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 +#define TXGBE_SFF_SOFT_RS_SELECT_10G 0x8 +#define TXGBE_SFF_SOFT_RS_SELECT_1G 0x0 +#define TXGBE_SFF_ADDRESSING_MODE 0x4 +#define TXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 +#define TXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 +#define TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23 +#define TXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0 +#define TXGBE_I2C_EEPROM_READ_MASK 0x100 +#define TXGBE_I2C_EEPROM_STATUS_MASK 0x3 +#define TXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 +#define TXGBE_I2C_EEPROM_STATUS_PASS 0x1 +#define TXGBE_I2C_EEPROM_STATUS_FAIL 0x2 +#define TXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 + +/* EEPROM for SFF-8472 (dev_addr = 0xA2) */ +#define TXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 + +/* SFP+ SFF-8472 Compliance */ +#define TXGBE_SFF_SFF_8472_UNSUP 0x00 + +/****************************************************************************** + * PHY MDIO Registers: + ******************************************************************************/ +#define TXGBE_MAX_PHY_ADDR 32 +/* PHY IDs*/ +#define TXGBE_PHYID_MTD3310 0x00000000U +#define TXGBE_PHYID_TN1010 0x00A19410U +#define TXGBE_PHYID_QT2022 0x0043A400U +#define TXGBE_PHYID_ATH 0x03429050U + +/* (dev_type = 1) */ +#define TXGBE_MD_DEV_PMA_PMD 0x1 +#define TXGBE_MD_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ +#define TXGBE_MD_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ +#define TXGBE_PHY_REVISION_MASK 0xFFFFFFF0 +#define TXGBE_MD_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ +#define TXGBE_MD_PHY_SPEED_10G 0x0001 /* 10G capable */ +#define TXGBE_MD_PHY_SPEED_1G 0x0010 /* 1G capable */ +#define TXGBE_MD_PHY_SPEED_100M 0x0020 /* 100M capable */ +#define TXGBE_MD_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ +#define TXGBE_MD_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ +#define TXGBE_MD_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ +#define TXGBE_MD_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ +#define TXGBE_MD_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ + +#define TXGBE_MD_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */ +#define TXGBE_MD_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ +#define TXGBE_MD_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ +#define TXGBE_MD_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ + +#define TXGBE_MD_FW_REV_LO 0xC011 +#define TXGBE_MD_FW_REV_HI 0xC012 + +#define TXGBE_TN_LASI_STATUS_REG 0x9005 +#define TXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 + +/* (dev_type = 3) */ +#define TXGBE_MD_DEV_PCS 0x3 +#define TXGBE_PCRC8ECL 0x0E810 /* PCR CRC-8 Error Count Lo */ +#define TXGBE_PCRC8ECH 0x0E811 /* PCR CRC-8 Error Count Hi */ +#define TXGBE_PCRC8ECH_MASK 0x1F +#define TXGBE_LDPCECL 0x0E820 /* PCR Uncorrected Error Count Lo */ +#define TXGBE_LDPCECH 0x0E821 /* PCR Uncorrected Error Count Hi */ + +/* (dev_type = 4) */ +#define TXGBE_MD_DEV_PHY_XS 0x4 +#define TXGBE_MD_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ +#define TXGBE_MD_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ + +/* (dev_type = 7) */ +#define TXGBE_MD_DEV_AUTO_NEG 0x7 + +#define TXGBE_MD_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ +#define TXGBE_MD_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ +#define TXGBE_MD_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */ +#define TXGBE_MD_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */ +#define TXGBE_MD_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */ +#define TXGBE_MD_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */ +#define TXGBE_MD_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ +#define TXGBE_TAF_SYM_PAUSE MS16(10, 0x3) +#define TXGBE_TAF_ASM_PAUSE MS16(11, 0x3) + +#define TXGBE_MD_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ +#define TXGBE_MD_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */ +/* PHY address definitions for new protocol MDIO commands */ +#define TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ +#define TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ +#define TXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ +#define TXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ +#define TXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ +#define TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ +#define TXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ +#define TXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400 +#define TXGBE_MII_5GBASE_T_ADVERTISE 0x0800 +#define TXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ +#define TXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ +#define TXGBE_MII_RESTART 0x200 +#define TXGBE_MII_AUTONEG_COMPLETE 0x20 +#define TXGBE_MII_AUTONEG_LINK_UP 0x04 +#define TXGBE_MII_AUTONEG_REG 0x0 +#define TXGBE_MD_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */ +#define TXGBE_MD_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */ +#define TXGBE_MD_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */ +#define TXGBE_MD_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */ + +/* (dev_type = 30) */ +#define TXGBE_MD_DEV_VENDOR_1 30 +#define TXGBE_MD_DEV_XFI_DSP 30 +#define TNX_FW_REV 0xB +#define TXGBE_MD_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ +#define TXGBE_MD_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ +#define TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ +#define TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ +#define TXGBE_MD_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 +#define TXGBE_MD_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 + +/* (dev_type = 31) */ +#define TXGBE_MD_DEV_GENERAL 31 +#define TXGBE_MD_PORT_CTRL 0xF001 +#define TXGBE_MD_PORT_CTRL_RESET MS16(14, 0x1) + +/****************************************************************************** + * SFP I2C Registers: + ******************************************************************************/ +#define TXGBE_I2C_SLAVEADDR (0x50) + +bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr); +enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id); +s32 txgbe_get_phy_id(struct txgbe_hw *hw); +s32 txgbe_identify_phy(struct txgbe_hw *hw); + +/* PHY specific */ +s32 txgbe_identify_module(struct txgbe_hw *hw); +s32 txgbe_identify_sfp_module(struct txgbe_hw *hw); +s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw); + +#endif /* _TXGBE_PHY_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index f8ac41fe9..9bbb04d20 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -363,9 +363,16 @@ struct txgbe_phy_info { u8 value); enum txgbe_phy_type type; + u32 addr; + u32 id; enum txgbe_sfp_type sfp_type; bool sfp_setup_needed; + u32 revision; + u32 media_type; + u32 phy_semaphore_mask; bool reset_disable; + bool qsfp_shared_i2c_bus; + u32 nw_mng_if_sel; }; struct txgbe_mbx_info {