[v3,2/2] net/octeontx2: add rss hash level support
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Commit Message
From: Kiran Kumar K <kirankumark@marvell.com>
Add support to choose rss hash level from ethdev rss config.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
drivers/net/octeontx2/otx2_ethdev.h | 4 +++-
drivers/net/octeontx2/otx2_rss.c | 9 +++++++--
2 files changed, 10 insertions(+), 3 deletions(-)
Comments
On Tue, Aug 18, 2020 at 12:52 PM <kirankumark@marvell.com> wrote:
>
> From: Kiran Kumar K <kirankumark@marvell.com>
>
> Add support to choose rss hash level from ethdev rss config.
>
> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
> ---
> drivers/net/octeontx2/otx2_ethdev.h | 4 +++-
> drivers/net/octeontx2/otx2_rss.c | 9 +++++++--
> 2 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
> index e9efe52bb..953445ecb 100644
> --- a/drivers/net/octeontx2/otx2_ethdev.h
> +++ b/drivers/net/octeontx2/otx2_ethdev.h
> @@ -119,7 +119,9 @@
> #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
> ETH_RSS_TCP | ETH_RSS_SCTP | \
> ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
> - NIX_RSS_L3_L4_SRC_DST)
> + NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_INNER | \
> + ETH_RSS_LEVEL_OUTER | \
> + ETH_RSS_LEVEL_INNER_OUTER)
Since it is value 1 and 2, for bitmask purpose, shouldn't be
ETH_RSS_LEVEL_MASK instead of ETH_RSS_LEVEL_OUTER |
ETH_RSS_LEVEL_INNER_OUTER
> -----Original Message-----
> From: Jerin Jacob <jerinjacobk@gmail.com>
> Sent: Tuesday, August 18, 2020 3:34 PM
> To: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
> Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; Nithin Kumar Dabilpuram
> <ndabilpuram@marvell.com>; dpdk-dev <dev@dpdk.org>; Thomas Monjalon
> <thomas@monjalon.net>; Ferruh Yigit <ferruh.yigit@intel.com>; Andrew
> Rybchenko <arybchenko@solarflare.com>; Ori Kam <orika@mellanox.com>;
> Ziyang Xuan <xuanziyang2@huawei.com>; Xiaoyun Wang
> <cloud.wangxiaoyun@huawei.com>; Guoyang Zhou
> <zhouguoyang@huawei.com>; Rosen Xu <rosen.xu@intel.com>; Beilei Xing
> <beilei.xing@intel.com>; jia.guo@intel.com; Rasesh Mody
> <rmody@marvell.com>; Shahed Shaikh <shshaikh@marvell.com>; Qiming Yang
> <qiming.yang@intel.com>; Qi Zhang <qi.z.zhang@intel.com>; Wiles, Keith
> <keith.wiles@intel.com>; Hemant Agrawal <hemant.agrawal@nxp.com>;
> Sachin Saxena <sachin.saxena@nxp.com>; Zhao1, Wei <wei.zhao1@intel.com>;
> John Daley <johndale@cisco.com>; Hyong Youb Kim <hyonkim@cisco.com>;
> Chas Williams <chas3@att.com>; Matan Azrad <matan@mellanox.com>;
> Shahaf Shuler <shahafs@mellanox.com>; Slava Ovsiienko
> <viacheslavo@mellanox.com>; Rahul Lakkireddy
> <rahul.lakkireddy@chelsio.com>; Gaetan Rivet <grive@u256.net>; Liron Himi
> <lironh@marvell.com>; Jingjing Wu <jingjing.wu@intel.com>; Wei Hu (Xavier
> <xavier.huwei@huawei.com>; Min Hu (Connor <humin29@huawei.com>; Yisen
> Zhuang <yisen.zhuang@huawei.com>; Ajit Khaparde
> <ajit.khaparde@broadcom.com>; Somnath Kotur
> <somnath.kotur@broadcom.com>; Jasvinder Singh
> <jasvinder.singh@intel.com>; Cristian Dumitrescu
> <cristian.dumitrescu@intel.com>
> Subject: [EXT] Re: [dpdk-dev] [PATCH v3 2/2] net/octeontx2: add rss hash level
> support
>
> External Email
>
> ----------------------------------------------------------------------
> On Tue, Aug 18, 2020 at 12:52 PM <kirankumark@marvell.com> wrote:
> >
> > From: Kiran Kumar K <kirankumark@marvell.com>
> >
> > Add support to choose rss hash level from ethdev rss config.
> >
> > Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
> > ---
> > drivers/net/octeontx2/otx2_ethdev.h | 4 +++-
> > drivers/net/octeontx2/otx2_rss.c | 9 +++++++--
> > 2 files changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/net/octeontx2/otx2_ethdev.h
> > b/drivers/net/octeontx2/otx2_ethdev.h
> > index e9efe52bb..953445ecb 100644
> > --- a/drivers/net/octeontx2/otx2_ethdev.h
> > +++ b/drivers/net/octeontx2/otx2_ethdev.h
> > @@ -119,7 +119,9 @@
> > #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP |
> ETH_RSS_UDP |\
> > ETH_RSS_TCP | ETH_RSS_SCTP | \
> > ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
> > - NIX_RSS_L3_L4_SRC_DST)
> > + NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_INNER | \
> > + ETH_RSS_LEVEL_OUTER | \
> > + ETH_RSS_LEVEL_INNER_OUTER)
>
> Since it is value 1 and 2, for bitmask purpose, shouldn't be
> ETH_RSS_LEVEL_MASK instead of ETH_RSS_LEVEL_OUTER |
> ETH_RSS_LEVEL_INNER_OUTER
Will update in V4.
@@ -119,7 +119,9 @@
#define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
ETH_RSS_TCP | ETH_RSS_SCTP | \
ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
- NIX_RSS_L3_L4_SRC_DST)
+ NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_INNER | \
+ ETH_RSS_LEVEL_OUTER | \
+ ETH_RSS_LEVEL_INNER_OUTER)
#define NIX_TX_OFFLOAD_CAPA ( \
DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
@@ -323,6 +323,7 @@ otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_conf *rss_conf)
{
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+ uint8_t rss_hash_level;
uint32_t flowkey_cfg;
uint8_t alg_idx;
int rc;
@@ -339,7 +340,9 @@ otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
otx2_nix_rss_set_key(dev, rss_conf->rss_key,
(uint32_t)rss_conf->rss_key_len);
- flowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss_conf->rss_hf, 0);
+ rss_hash_level = ETH_RSS_LEVEL(rss_conf->rss_hf);
+ flowkey_cfg =
+ otx2_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level);
rc = otx2_rss_set_hf(dev, flowkey_cfg, &alg_idx,
NIX_DEFAULT_RSS_CTX_GROUP,
@@ -375,6 +378,7 @@ otx2_nix_rss_config(struct rte_eth_dev *eth_dev)
{
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
uint32_t idx, qcnt = eth_dev->data->nb_rx_queues;
+ uint8_t rss_hash_level;
uint32_t flowkey_cfg;
uint64_t rss_hf;
uint8_t alg_idx;
@@ -399,7 +403,8 @@ otx2_nix_rss_config(struct rte_eth_dev *eth_dev)
}
rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
- flowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss_hf, 0);
+ rss_hash_level = ETH_RSS_LEVEL(rss_hf);
+ flowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
rc = otx2_rss_set_hf(dev, flowkey_cfg, &alg_idx,
NIX_DEFAULT_RSS_CTX_GROUP,