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[v2,1/2] ethdev: add level support for RSS offload types

Message ID 20200808143631.1704756-1-kirankumark@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Ferruh Yigit
Headers show
Series [v2,1/2] ethdev: add level support for RSS offload types | expand

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Context Check Description
ci/iol-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/checkpatch success coding style OK

Commit Message

Kiran Kumar Kokkilagadda Aug. 8, 2020, 2:36 p.m. UTC
From: Kiran Kumar K <kirankumark@marvell.com>

This patch reserves 2 bits as input selection to select Inner and
outer layers for RSS computation. It is combined with existing
ETH_RSS_* to choose Inner or outer layers for L2, L3 and L4.
This functionality already exists in rte_flow through level parameter in
RSS action configuration rte_flow_action_rss.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
v2 changes:
* Reserved bit 50 & 51

 lib/librte_ethdev/rte_ethdev.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

--
2.25.1

Comments

Ajit Khaparde Aug. 8, 2020, 2:40 p.m. UTC | #1
On Sat, Aug 8, 2020 at 7:36 AM <kirankumark@marvell.com> wrote:

> From: Kiran Kumar K <kirankumark@marvell.com>
>
> This patch reserves 2 bits as input selection to select Inner and
> outer layers for RSS computation. It is combined with existing
> ETH_RSS_* to choose Inner or outer layers for L2, L3 and L4.

How do you plan to use this? Do you need to make any changes to testpmd?


> This functionality already exists in rte_flow through level parameter in
> RSS action configuration rte_flow_action_rss.
>
> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
> ---
> v2 changes:
> * Reserved bit 50 & 51
>
>  lib/librte_ethdev/rte_ethdev.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/lib/librte_ethdev/rte_ethdev.h
> b/lib/librte_ethdev/rte_ethdev.h
> index d29930fd8..28184cc85 100644
> --- a/lib/librte_ethdev/rte_ethdev.h
> +++ b/lib/librte_ethdev/rte_ethdev.h
> @@ -552,6 +552,33 @@ struct rte_eth_rss_conf {
>  #define RTE_ETH_RSS_L3_PRE64      (1ULL << 53)
>  #define RTE_ETH_RSS_L3_PRE96      (1ULL << 52)
>
> +/*
> + * We use the following macros to combine with the above layers to choose
> + * inner and outer layers or both for RSS computation.
> + * Note: Default is 0: inner layers, 1: outer layers, 2: both
> + * bit 50 and 51 are reserved for this.
> + */
> +
> +/**
> + * Level 0, It basically stands for the innermost encapsulation level RSS
> + * can be performed on according to PMD and device capabilities.
> + */
> +#define ETH_RSS_LEVEL_INNER        (0ULL << 50)
> +/**
> + * Level 1, It basically stands for the outermost encapsulation level RSS
> + * can be performed on according to PMD and device capabilities.
> + */
> +#define ETH_RSS_LEVEL_OUTER        (1ULL << 50)
> +/**
> + * Level 2, It basically stands for the both inner and outermost
> + * encapsulation level RSS can be performed on according to PMD and
> + * device capabilities.
> + */
> +#define ETH_RSS_LEVEL_INNER_OUTER  (2ULL << 50)
> +#define ETH_RSS_LEVEL_MASK        (3ULL << 50)
> +
> +#define ETH_RSS_LEVEL(rss_hf) ((rss_hf & ETH_RSS_LEVEL_MASK) >> 50)
> +
>  /**
>   * For input set change of hash filter, if SRC_ONLY and DST_ONLY of
>   * the same level are used simultaneously, it is the same case as
> --
> 2.25.1
>
>
Kiran Kumar Kokkilagadda Aug. 14, 2020, 3:55 a.m. UTC | #2
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Sent: Saturday, August 8, 2020 8:10 PM
To: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
Cc: Andrew Rybchenko <arybchenko@solarflare.com>; Ferruh Yigit <ferruh.yigit@intel.com>; Thomas Monjalon <thomas@monjalon.net>; beilei.xing@intel.com; chas3@att.com; cloud.wangxiaoyun@huawei.com; cristian.dumitrescu@intel.com; dev@dpdk.org; grive@u256.net; hemant.agrawal@nxp.com; humin29@huawei.com; hyonkim@cisco.com; jasvinder.singh@intel.com; Jerin Jacob Kollanukkaran <jerinj@marvell.com>; jia.guo@intel.com; jingjing.wu@intel.com; johndale@cisco.com; keith.wiles@intel.com; Liron Himi <lironh@marvell.com>; matan@mellanox.com; Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>; orika@mellanox.com; qi.z.zhang@intel.com; qiming.yang@intel.com; rahul.lakkireddy@chelsio.com; Rasesh Mody <rmody@marvell.com>; rosen.xu@intel.com; sachin.saxena@nxp.com; shahafs@mellanox.com; Shahed Shaikh <shshaikh@marvell.com>; somnath.kotur@broadcom.com; viacheslavo@mellanox.com; wei.zhao1@intel.com; xavier.huwei@huawei.com; xuanziyang2@huawei.com; yisen.zhuang@huawei.com; zhouguoyang@huawei.com
Subject: [EXT] Re: [dpdk-dev][PATCH v2 1/2] ethdev: add level support for RSS offload types

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Patch

diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h
index d29930fd8..28184cc85 100644
--- a/lib/librte_ethdev/rte_ethdev.h
+++ b/lib/librte_ethdev/rte_ethdev.h
@@ -552,6 +552,33 @@  struct rte_eth_rss_conf {
 #define RTE_ETH_RSS_L3_PRE64	   (1ULL << 53)
 #define RTE_ETH_RSS_L3_PRE96	   (1ULL << 52)

+/*
+ * We use the following macros to combine with the above layers to choose
+ * inner and outer layers or both for RSS computation.
+ * Note: Default is 0: inner layers, 1: outer layers, 2: both
+ * bit 50 and 51 are reserved for this.
+ */
+
+/**
+ * Level 0, It basically stands for the innermost encapsulation level RSS
+ * can be performed on according to PMD and device capabilities.
+ */
+#define ETH_RSS_LEVEL_INNER        (0ULL << 50)
+/**
+ * Level 1, It basically stands for the outermost encapsulation level RSS
+ * can be performed on according to PMD and device capabilities.
+ */
+#define ETH_RSS_LEVEL_OUTER        (1ULL << 50)
+/**
+ * Level 2, It basically stands for the both inner and outermost
+ * encapsulation level RSS can be performed on according to PMD and
+ * device capabilities.
+ */
+#define ETH_RSS_LEVEL_INNER_OUTER  (2ULL << 50)
+#define ETH_RSS_LEVEL_MASK	   (3ULL << 50)
+
+#define ETH_RSS_LEVEL(rss_hf) ((rss_hf & ETH_RSS_LEVEL_MASK) >> 50)
+
 /**
  * For input set change of hash filter, if SRC_ONLY and DST_ONLY of
  * the same level are used simultaneously, it is the same case as