Checks
| Context | Check | Description |
|---|---|---|
| ci/checkpatch | success | coding style OK |
| ci/Intel-compilation | success | Compilation OK |
Commit Message
Guinan Sun
June 22, 2020, 6:46 a.m. UTC
Defined DPGFR, Dynamic Power Gate Force Control Register. Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com> Signed-off-by: Guinan Sun <guinanx.sun@intel.com> --- drivers/net/e1000/base/e1000_regs.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h index 2a258543e..9262d7fac 100644 --- a/drivers/net/e1000/base/e1000_regs.h +++ b/drivers/net/e1000/base/e1000_regs.h @@ -47,6 +47,7 @@ #define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */ #define E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */ #define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */ +#define E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */ #define E1000_FCT 0x00030 /* Flow Control Type - RW */ #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ #define E1000_VET 0x00038 /* VLAN Ether Type - RW */