From patchwork Mon Jun 22 06:46:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guinan Sun X-Patchwork-Id: 71917 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A025EA0350; Mon, 22 Jun 2020 09:14:30 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DA40F1D55F; Mon, 22 Jun 2020 09:06:56 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 0565E1D5BE for ; Mon, 22 Jun 2020 09:06:53 +0200 (CEST) IronPort-SDR: g4HJagZ8uPZyh94a5/F9dL/MB+7CVwXrs3TtJ41YvyWPSSdurqnUWWUZQtTzYvIJC3DDKYLTad sJ1GDUjpgohQ== X-IronPort-AV: E=McAfee;i="6000,8403,9659"; a="131070821" X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="131070821" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2020 00:06:52 -0700 IronPort-SDR: KCl3ZjssQDr1rnCUH6MjoehU2M3o9zU27kY4dGzUu1pq1yWc7ntsXdxPpLupysY+qrm+Ow0JbK oZrP99EATWmw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="384409174" Received: from dpdk.sh.intel.com ([10.239.255.83]) by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2020 00:06:51 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Jeff Guo , Zhao1 Wei , Guinan Sun , Jeff Kirsher Date: Mon, 22 Jun 2020 06:46:14 +0000 Message-Id: <20200622064634.70941-51-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200622064634.70941-1-guinanx.sun@intel.com> References: <20200622064634.70941-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH 50/70] net/e1000/base: clean up dead code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For i225 devices, the tag NO_I225_SUPPORT will never be defined, so remove the tag and code that reside in the i225 family file. Signed-off-by: Jeff Kirsher Signed-off-by: Guinan Sun --- drivers/net/e1000/base/e1000_i225.c | 125 +--------------------------- 1 file changed, 1 insertion(+), 124 deletions(-) diff --git a/drivers/net/e1000/base/e1000_i225.c b/drivers/net/e1000/base/e1000_i225.c index 089bc7a2a..85f0a72b1 100644 --- a/drivers/net/e1000/base/e1000_i225.c +++ b/drivers/net/e1000/base/e1000_i225.c @@ -587,50 +587,6 @@ STATIC s32 __e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, return ret_val; } -/* e1000_read_invm_word_i225 - Reads OTP - * @hw: pointer to the HW structure - * @address: the word address (aka eeprom offset) to read - * @data: pointer to the data read - * - * Reads 16-bit words from the OTP. Return error when the word is not - * stored in OTP. - */ -STATIC s32 e1000_read_invm_word_i225(struct e1000_hw *hw, u8 address, u16 *data) -{ - s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND; - u32 invm_dword; - u16 i; - u8 record_type, word_address; - - DEBUGFUNC("e1000_read_invm_word_i225"); - - for (i = 0; i < E1000_INVM_SIZE; i++) { - invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i)); - /* Get record type */ - record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); - if (record_type == e1000_invm_unitialized_structure) - break; - if (record_type == e1000_invm_csr_autoload_structure) - i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; - if (record_type == e1000_invm_rsa_key_sha256_structure) - i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; - if (record_type == e1000_invm_word_autoload_structure) { - word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); - if (word_address == address) { - *data = INVM_DWORD_TO_WORD_DATA(invm_dword); - DEBUGOUT2("Read INVM Word 0x%02x = %x", - address, *data); - status = E1000_SUCCESS; - break; - } - } - } - if (status != E1000_SUCCESS) - DEBUGOUT1("Requested word 0x%02x not found in OTP\n", address); - return status; -} - -#if defined(NVM_VERSION_SUPPORT) || defined(QV_RELEASE) /* e1000_read_invm_version_i225 - Reads iNVM version and image type * @hw: pointer to the HW structure * @invm_ver: version structure for the version read @@ -727,7 +683,6 @@ s32 e1000_read_invm_version_i225(struct e1000_hw *hw, return status; } -#endif /* NVM_VERSION_SUPPORT or QV_RELEASE */ /* e1000_validate_nvm_checksum_i225 - Validate EEPROM checksum * @hw: pointer to the HW structure * @@ -1076,80 +1031,7 @@ STATIC s32 e1000_valid_led_default_i225(struct e1000_hw *hw, u16 *data) break; } } -#ifndef QV_RELEASE out: -#endif /* QV_RELEASE */ - return ret_val; -} - -/* e1000_pll_workaround_i225 - * @hw: pointer to the HW structure - * - * Works around an errata in the PLL circuit where it occasionally - * provides the wrong clock frequency after power up. - */ -STATIC s32 e1000_pll_workaround_i225(struct e1000_hw *hw) -{ - s32 ret_val; - u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; - u16 nvm_word, phy_word, pci_word, tmp_nvm; - int i; - - /* Get PHY semaphore */ - hw->phy.ops.acquire(hw); - /* Get and set needed register values */ - wuc = E1000_READ_REG(hw, E1000_WUC); - mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); - reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; - E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val); - - /* Get data from NVM, or set default */ - ret_val = e1000_read_invm_word_i225(hw, E1000_INVM_AUTOLOAD, - &nvm_word); - if (ret_val != E1000_SUCCESS) - nvm_word = E1000_INVM_DEFAULT_AL; - tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL; - for (i = 0; i < E1000_MAX_PLL_TRIES; i++) { - /* check current state directly from internal PHY */ - e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0xFC); - usec_delay(20); - e1000_read_phy_reg_mdic(hw, E1000_PHY_PLL_FREQ_REG, &phy_word); - usec_delay(20); - e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0); - if ((phy_word & E1000_PHY_PLL_UNCONF) - != E1000_PHY_PLL_UNCONF) { - ret_val = E1000_SUCCESS; - } else { - ret_val = -E1000_ERR_PHY; - } - /* directly reset the internal PHY */ - ctrl = E1000_READ_REG(hw, E1000_CTRL); - E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); - - ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); - ctrl_ext |= (E1000_CTRL_EXT_PHYPDEN | E1000_CTRL_EXT_SDLPE); - E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); - - E1000_WRITE_REG(hw, E1000_WUC, 0); - reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); - E1000_WRITE_REG(hw, E1000_EEARBC_I225, reg_val); - - e1000_read_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); - pci_word |= E1000_PCI_PMCSR_D3; - e1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); - msec_delay(1); - pci_word &= ~E1000_PCI_PMCSR_D3; - e1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); - reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); - E1000_WRITE_REG(hw, E1000_EEARBC_I225, reg_val); - - /* restore WUC register */ - E1000_WRITE_REG(hw, E1000_WUC, wuc); - } - /* restore MDICNFG setting */ - E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); - /* Release PHY semaphore */ - hw->phy.ops.release(hw); return ret_val; } @@ -1191,12 +1073,7 @@ s32 e1000_init_hw_i225(struct e1000_hw *hw) s32 ret_val; DEBUGFUNC("e1000_init_hw_i225"); - if ((hw->mac.type >= e1000_i225) && - !(e1000_get_flash_presence_i225(hw))) { - ret_val = e1000_pll_workaround_i225(hw); - if (ret_val != E1000_SUCCESS) - return ret_val; - } + hw->phy.ops.get_cfg_done = e1000_get_cfg_done_i225; ret_val = e1000_init_hw_base(hw); return ret_val;