Checks
| Context | Check | Description |
|---|---|---|
| ci/checkpatch | success | coding style OK |
| ci/Intel-compilation | success | Compilation OK |
Commit Message
Guinan Sun
June 22, 2020, 6:46 a.m. UTC
Added defines for the EEC, SHADOWINF and FLFWUPDATE registers needed for the nvmupd_validate_offset function to correctly validate the NVM update offset. Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Guinan Sun <guinanx.sun@intel.com> --- drivers/net/e1000/base/e1000_regs.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h index 2e14ce109..afd27ac2b 100644 --- a/drivers/net/e1000/base/e1000_regs.h +++ b/drivers/net/e1000/base/e1000_regs.h @@ -145,7 +145,10 @@ #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ #define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */ #define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */ -#define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */ +/* Shadow Ram Write Register - RW */ +#define E1000_SRWR 0x12018 +#define E1000_EEC_REG 0x12010 + #define E1000_I210_FLMNGCTL 0x12038 #define E1000_I210_FLMNGDATA 0x1203C #define E1000_I210_FLMNGCNT 0x12040 @@ -156,6 +159,9 @@ #define E1000_I210_FLA 0x1201C +#define E1000_SHADOWINF 0x12068 +#define E1000_FLFWUPDATE 0x12108 + #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n)) #define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */