diff --git a/drivers/net/qede/Makefile b/drivers/net/qede/Makefile
index 5810b4d49..6ed776c5a 100644
--- a/drivers/net/qede/Makefile
+++ b/drivers/net/qede/Makefile
@@ -104,5 +104,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_ethdev.c
 SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_main.c
 SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_rxtx.c
 SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_filter.c
+SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_sriov.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/qede/meson.build b/drivers/net/qede/meson.build
index 12388a680..7f62cb78d 100644
--- a/drivers/net/qede/meson.build
+++ b/drivers/net/qede/meson.build
@@ -9,4 +9,5 @@ sources = files(
 	'qede_filter.c',
 	'qede_main.c',
 	'qede_rxtx.c',
+	'qede_sriov.c',
 )
diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c
index c4f8f1258..250cd2d0e 100644
--- a/drivers/net/qede/qede_ethdev.c
+++ b/drivers/net/qede/qede_ethdev.c
@@ -2714,6 +2714,7 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
 		adapter->vxlan.enable = false;
 		adapter->geneve.enable = false;
 		adapter->ipgre.enable = false;
+		qed_ops->sriov_configure(edev, pci_dev->max_vfs);
 	}
 
 	DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h
index b988a73f2..fcc17e22e 100644
--- a/drivers/net/qede/qede_ethdev.h
+++ b/drivers/net/qede/qede_ethdev.h
@@ -34,6 +34,7 @@
 #include "base/ecore_l2.h"
 #include "base/ecore_vf.h"
 
+#include "qede_sriov.h"
 #include "qede_logs.h"
 #include "qede_if.h"
 #include "qede_rxtx.h"
diff --git a/drivers/net/qede/qede_if.h b/drivers/net/qede/qede_if.h
index 858cd51d5..e30161616 100644
--- a/drivers/net/qede/qede_if.h
+++ b/drivers/net/qede/qede_if.h
@@ -82,6 +82,7 @@ struct qed_eth_ops {
 	const struct qed_common_ops *common;
 	int (*fill_dev_info)(struct ecore_dev *edev,
 			     struct qed_dev_eth_info *info);
+	void (*sriov_configure)(struct ecore_dev *edev, int num_vfs);
 };
 
 struct qed_link_params {
diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c
index 62039af6f..a02ef5685 100644
--- a/drivers/net/qede/qede_main.c
+++ b/drivers/net/qede/qede_main.c
@@ -786,6 +786,7 @@ const struct qed_common_ops qed_common_ops_pass = {
 const struct qed_eth_ops qed_eth_ops_pass = {
 	INIT_STRUCT_FIELD(common, &qed_common_ops_pass),
 	INIT_STRUCT_FIELD(fill_dev_info, &qed_fill_eth_dev_info),
+	INIT_STRUCT_FIELD(sriov_configure, &qed_sriov_configure),
 };
 
 const struct qed_eth_ops *qed_get_eth_ops(void)
diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c
new file mode 100644
index 000000000..ba4384e90
--- /dev/null
+++ b/drivers/net/qede/qede_sriov.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2020 Marvell.
+ * All rights reserved.
+ * www.marvell.com
+ */
+
+#include "qede_sriov.h"
+
+static void qed_sriov_enable_qid_config(struct ecore_hwfn *hwfn,
+					u16 vfid,
+					struct ecore_iov_vf_init_params *params)
+{
+	u16 num_pf_l2_queues, base, i;
+
+	/* Since we have an equal resource distribution per-VF, and we assume
+	 * PF has acquired its first queues, we start setting sequentially from
+	 * there.
+	 */
+	num_pf_l2_queues = (u16)FEAT_NUM(hwfn, ECORE_PF_L2_QUE);
+
+	base = num_pf_l2_queues + vfid * params->num_queues;
+	params->rel_vf_id = vfid;
+
+	for (i = 0; i < params->num_queues; i++) {
+		params->req_rx_queue[i] = base + i;
+		params->req_tx_queue[i] = base + i;
+	}
+
+	/* PF uses indices 0 for itself; Set vport/RSS afterwards */
+	params->vport_id = vfid + 1;
+	params->rss_eng_id = vfid + 1;
+}
+
+static void qed_sriov_enable(struct ecore_dev *edev, int num)
+{
+	struct ecore_iov_vf_init_params params;
+	struct ecore_hwfn *p_hwfn;
+	struct ecore_ptt *p_ptt;
+	int i, j, rc;
+
+	if ((u32)num >= RESC_NUM(&edev->hwfns[0], ECORE_VPORT)) {
+		DP_NOTICE(edev, false, "Can start at most %d VFs\n",
+			  RESC_NUM(&edev->hwfns[0], ECORE_VPORT) - 1);
+		return;
+	}
+
+	OSAL_MEMSET(&params, 0, sizeof(struct ecore_iov_vf_init_params));
+
+	for_each_hwfn(edev, j) {
+		int feat_num;
+
+		p_hwfn = &edev->hwfns[j];
+		p_ptt = ecore_ptt_acquire(p_hwfn);
+		feat_num = FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE) / num;
+
+		params.num_queues = OSAL_MIN_T(int, feat_num, 16);
+
+		for (i = 0; i < num; i++) {
+			if (!ecore_iov_is_valid_vfid(p_hwfn, i, false, true))
+				continue;
+
+			qed_sriov_enable_qid_config(p_hwfn, i, &params);
+
+			rc = ecore_iov_init_hw_for_vf(p_hwfn, p_ptt, &params);
+			if (rc) {
+				DP_ERR(edev, "Failed to enable VF[%d]\n", i);
+				ecore_ptt_release(p_hwfn, p_ptt);
+				return;
+			}
+		}
+
+		ecore_ptt_release(p_hwfn, p_ptt);
+	}
+}
+
+void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param)
+{
+	if (!IS_ECORE_SRIOV(edev)) {
+		DP_VERBOSE(edev, ECORE_MSG_IOV, "SR-IOV is not supported\n");
+		return;
+	}
+
+	if (num_vfs_param)
+		qed_sriov_enable(edev, num_vfs_param);
+}
diff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h
new file mode 100644
index 000000000..6c85b1dd5
--- /dev/null
+++ b/drivers/net/qede/qede_sriov.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2020 Marvell.
+ * All rights reserved.
+ * www.marvell.com
+ */
+
+#include "qede_ethdev.h"
+
+void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param);
