From patchwork Wed Apr 1 14:21:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67608 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 09549A057B; Wed, 1 Apr 2020 16:25:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AD7351C12A; Wed, 1 Apr 2020 16:22:15 +0200 (CEST) Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by dpdk.org (Postfix) with ESMTP id 8DCAE1C113 for ; Wed, 1 Apr 2020 16:22:09 +0200 (CEST) Received: by mail-lf1-f65.google.com with SMTP id t11so8199845lfe.4 for ; Wed, 01 Apr 2020 07:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5A9hsbTp+jjQv9P8DNmXLX5GuSXGtPzKA9NbAJIoZv4=; b=k6chPiwiGvecUN6TrT2fsMF6eDIsfuwdCvcPDN4N6BPhiHmQUl8jGF8buXVn/crluD uEHxur/XYSja74xqMN+NeyeLDpH/49hJbtUIaCbzR92dUbPZxytuVsQNtnsy+E0tuHG8 rnkqISHsCf6BzxHejzJzbHTSGiBnx9gYIoxYCcOkuk1DH0cA1R9zgWyy6rMbFYcoegT4 0+I9u/gtMv23puI11uGvgtIQafZimy9F1sDOZPE/cr05VbEi7Ic89uaJocH1risp3j0n FP32My6jvoKcfpgCkaK5tVTOE3vMnkNxl3YX1N9wxfB8P+jfdTO6aHznMlRa6/49BmGf 0n0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5A9hsbTp+jjQv9P8DNmXLX5GuSXGtPzKA9NbAJIoZv4=; b=jkcAFxe7qPHx2JP2HsV30OBIU1P9+1zDKcqNNmeDda+fiSzokH5Btk6hNRAYrBVE8j rpyuNYf1rQV+2pQH5e5Vnw5WWbbNoOwWbrcIMTMzDFj96hyfEZxI6WRMb1TxZ/2htl8I QZnCpU+CduRqF1QdWgIsI48iArgqmVV0mcMvH1hYp4tAnyCscu/0GjICIouC3i2PKcmq uETNLAKr/Vk/16iOgOtrSW/xdsVgyIY4+Ac5/hR+9N7yJnnz9jjNdayZ1YT+ruMnf87Y vpUTtox8V8jgQzTRxJyiIn+9d2f2+Fox9mSNHN3GQrc2QSKQn1aD6filb0oyTrMLWr14 h45g== X-Gm-Message-State: AGi0PuZOLktBx8Rj42dheXRne1PrNJtjUfFU9tT6hPRc997pubDkowJl QwJK4J/Ph6cLiXbmZkkLx1aqzNJzvI0= X-Google-Smtp-Source: APiQypLdkO9FVHmO3wxi7IOMcWMBjemzLhgEnFJ3ITey29ElR+XE1iILoozh8nhnQx/Ush2a46BCZQ== X-Received: by 2002:ac2:5096:: with SMTP id f22mr15136656lfm.79.1585750928764; Wed, 01 Apr 2020 07:22:08 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:22:07 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:21 +0200 Message-Id: <20200401142127.13715-24-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 23/29] net/ena: limit refill threshold by fixed value X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Divider used for both Tx and Rx cleanup/refill threshold can cause too big delay in case of the really big rings - for example if the 8k Rx ring will be used, the refill won't trigger unless 1024 threshold will be reached. It will also cause driver to try to allocate that much descriptors. Limiting it by fixed value - 256 in that case, would limit maximum time spent in repopulate function. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/ena_ethdev.c | 27 ++++++++++++++------------- drivers/net/ena/ena_ethdev.h | 10 ++++++++++ 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index a6375e71c5..fc14f1cb32 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -35,14 +35,6 @@ /*reverse version of ENA_IO_RXQ_IDX*/ #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) -/* While processing submitted and completed descriptors (rx and tx path - * respectively) in a loop it is desired to: - * - perform batch submissions while populating sumbissmion queue - * - avoid blocking transmission of other packets during cleanup phase - * Hence the utilization ratio of 1/8 of a queue size. - */ -#define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) - #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) @@ -2146,7 +2138,8 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); unsigned int ring_size = rx_ring->ring_size; unsigned int ring_mask = ring_size - 1; - unsigned int refill_required; + unsigned int free_queue_entries; + unsigned int refill_threshold; uint16_t next_to_clean = rx_ring->next_to_clean; uint16_t descs_in_use; struct rte_mbuf *mbuf; @@ -2215,11 +2208,15 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_ring->rx_stats.cnt += completed; rx_ring->next_to_clean = next_to_clean; - refill_required = ena_com_free_q_entries(rx_ring->ena_com_io_sq); + free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); + refill_threshold = + RTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER, + (unsigned int)ENA_REFILL_THRESH_PACKET); + /* Burst refill to save doorbells, memory barriers, const interval */ - if (refill_required > ENA_RING_DESCS_RATIO(ring_size)) { + if (free_queue_entries > refill_threshold) { ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); - ena_populate_rx_queue(rx_ring, refill_required); + ena_populate_rx_queue(rx_ring, free_queue_entries); } return completed; @@ -2358,6 +2355,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t seg_len; unsigned int ring_size = tx_ring->ring_size; unsigned int ring_mask = ring_size - 1; + unsigned int cleanup_budget; struct ena_com_tx_ctx ena_tx_ctx; struct ena_tx_buffer *tx_info; struct ena_com_buf *ebuf; @@ -2515,9 +2513,12 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, /* Put back descriptor to the ring for reuse */ tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; next_to_clean++; + cleanup_budget = + RTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER, + (unsigned int)ENA_REFILL_THRESH_PACKET); /* If too many descs to clean, leave it for another run */ - if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) + if (unlikely(total_tx_descs > cleanup_budget)) break; } tx_ring->tx_stats.available_desc = diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 9df34136da..77c405fbdd 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -30,6 +30,16 @@ #define ENA_WD_TIMEOUT_SEC 3 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz()) +/* While processing submitted and completed descriptors (rx and tx path + * respectively) in a loop it is desired to: + * - perform batch submissions while populating sumbissmion queue + * - avoid blocking transmission of other packets during cleanup phase + * Hence the utilization ratio of 1/8 of a queue size or max value if the size + * of the ring is very big - like 8k Rx rings. + */ +#define ENA_REFILL_THRESH_DIVIDER 8 +#define ENA_REFILL_THRESH_PACKET 256 + struct ena_adapter; enum ena_ring_type {