From patchwork Fri Mar 27 13:42:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagadheeraj Rottela X-Patchwork-Id: 67304 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC50DA057C; Fri, 27 Mar 2020 14:42:49 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 031101C1CD; Fri, 27 Mar 2020 14:42:49 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 8FDE31C1BD for ; Fri, 27 Mar 2020 14:42:47 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 02RDgWuV016659; Fri, 27 Mar 2020 06:42:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=E6U/RlGYzv5I90UpHwvKG0jPZ7MhE9KInEERAPDC+7U=; b=VPJq8NX1hnSltzUEZi1Whkrmz3aXDiCssicXJPt2um7dYI3wgGMWS8Jvhmrf0AJniHJY WUU78U8VUqaP92D3k5qrRU0IlxyBud4jha9nkkO/8WyiCu0q8IR9yYFfR6IZhGRodOEK 2wmElEIG/LHnyjK2y5VarE+lBkbPN5F6BZBKECPubQDrgQs+ImXx6BoDda2mNcGynfm6 ntM0ljqI3CVD6BPjH8FiZEJHl8HWYJH4utHu1YnWghAtVtOKmoupTiXuJKFYHKBenW36 V8STuR7Xmj4+O4mKDjn3sSEuYjmv8Gp/1vkoNITkLrlUZ2OxyEf7TGTjSL2zL/Ak3Kmh Xg== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 300bpd19yb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 27 Mar 2020 06:42:46 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Mar 2020 06:42:44 -0700 Received: from hyd1399.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 27 Mar 2020 06:42:42 -0700 From: Nagadheeraj Rottela To: CC: , , , Nagadheeraj Rottela Date: Fri, 27 Mar 2020 19:12:38 +0530 Message-ID: <20200327134239.23358-1-rnagadheeraj@marvell.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.645 definitions=2020-03-27_04:2020-03-27, 2020-03-27 signatures=0 Subject: [dpdk-dev] [PATCH v3 1/2] crypto/nitrox: fix invalid CSR register address generation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If the NPS_PKT ring/port is greater than 8191 the NPS_PKT*() macros will evaluate to incorrect values due to unintended sign extension from int to unsigned long. To fix this, add UL suffix to the constants in these macros. The same problem is with AQMQ_QSZX() macro also. Coverity issue: 349899, 349905, 349911, 349921, 349923 Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management") Fixes: 0a8fc2423bff ("crypto/nitrox: introduce Nitrox driver") Signed-off-by: Nagadheeraj Rottela --- drivers/crypto/nitrox/nitrox_csr.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h index 8cd92e38b..de7a3c671 100644 --- a/drivers/crypto/nitrox/nitrox_csr.h +++ b/drivers/crypto/nitrox/nitrox_csr.h @@ -12,18 +12,18 @@ #define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset)) /* NPS packet registers */ -#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000)) -#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000)) -#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000)) -#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000)) -#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000)) -#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000)) -#define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000)) -#define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000)) -#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000)) +#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088UL + ((_i) * 0x40000UL)) +#define NPS_PKT_SLC_CTLX(_i) (0x10000UL + ((_i) * 0x40000UL)) +#define NPS_PKT_SLC_CNTSX(_i) (0x10008UL + ((_i) * 0x40000UL)) +#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010UL + ((_i) * 0x40000UL)) /* AQM Virtual Function Registers */ -#define AQMQ_QSZX(_i) (0x20008 + ((_i)*0x40000)) +#define AQMQ_QSZX(_i) (0x20008UL + ((_i) * 0x40000UL)) static inline uint64_t nitrox_read_csr(uint8_t *bar_addr, uint64_t offset)