From patchwork Mon Mar 16 12:24:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dybkowski, AdamX" X-Patchwork-Id: 66706 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 37461A0559; Mon, 16 Mar 2020 13:28:45 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3D71D1C02C; Mon, 16 Mar 2020 13:28:30 +0100 (CET) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id B37FA1BF30 for ; Mon, 16 Mar 2020 13:28:27 +0100 (CET) IronPort-SDR: YtfiAT38Xk9HSNS5bD+U+AbIv4bUFTOHIJQYjD4ycU7p5jIHzyNMgQnvfgKHWTeJZD6fkh0u3Y 3CeSNJ6DCLmA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2020 05:28:26 -0700 IronPort-SDR: 7cmMFE+u06G1149Ff+tWeKVHdX7/RTbgNh3kVI0kwrfQBw64A4IqGe0DKNfcksa2YrG+M+F1kQ GSM3/OQh6CVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,560,1574150400"; d="scan'208";a="355000137" Received: from adamdybx-mobl.ger.corp.intel.com (HELO addy-VirtualBox.ger.corp.intel.com) ([10.104.125.61]) by fmsmga001.fm.intel.com with ESMTP; 16 Mar 2020 05:28:25 -0700 From: Adam Dybkowski To: dev@dpdk.org, fiona.trahe@intel.com, akhil.goyal@nxp.com Cc: Adam Dybkowski Date: Mon, 16 Mar 2020 13:24:21 +0100 Message-Id: <20200316122421.21546-3-adamx.dybkowski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200316122421.21546-1-adamx.dybkowski@intel.com> References: <20200313152423.23498-1-adamx.dybkowski@intel.com> <20200316122421.21546-1-adamx.dybkowski@intel.com> Subject: [dpdk-dev] [PATCH v3 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds handling of mixed hash-cipher algorithms available on GEN2 QAT in particular firmware versions. Also the documentation is updated to show the mixed crypto algorithms are supported on QAT GEN2. Signed-off-by: Adam Dybkowski --- doc/guides/cryptodevs/qat.rst | 9 ++++----- doc/guides/rel_notes/release_20_05.rst | 7 +++++++ drivers/crypto/qat/qat_sym_pmd.c | 27 ++++++++++++++++++++++++++ drivers/crypto/qat/qat_sym_pmd.h | 5 +++++ drivers/crypto/qat/qat_sym_session.c | 17 ++++++++++------ 5 files changed, 54 insertions(+), 11 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 06985e319..2e0dc1b00 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -82,18 +82,17 @@ All the usual chains are supported and also some mixed chains: +------------------+-----------+-------------+----------+----------+ | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC | +==================+===========+=============+==========+==========+ - | NULL CIPHER | Y | 3 | 3 | Y | + | NULL CIPHER | Y | 2&3 | 2&3 | Y | +------------------+-----------+-------------+----------+----------+ - | SNOW3G UEA2 | 3 | Y | 3 | 3 | + | SNOW3G UEA2 | 2&3 | Y | 2&3 | 2&3 | +------------------+-----------+-------------+----------+----------+ - | ZUC EEA3 | 3 | 3 | 2&3 | 3 | + | ZUC EEA3 | 2&3 | 2&3 | 2&3 | 2&3 | +------------------+-----------+-------------+----------+----------+ - | AES CTR | Y | 3 | 3 | Y | + | AES CTR | Y | 2&3 | 2&3 | Y | +------------------+-----------+-------------+----------+----------+ * The combinations marked as "Y" are supported on all QAT hardware versions. * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only. -* The combinations marked as "3" are supported on GEN3 QAT hardware only. Limitations diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst index 2190eaf85..bdfa64973 100644 --- a/doc/guides/rel_notes/release_20_05.rst +++ b/doc/guides/rel_notes/release_20_05.rst @@ -56,6 +56,13 @@ New Features Also, make sure to start the actual text at the margin. ========================================================= +* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.** + + Enabled handling of mixed algorithms in encrypted digest hash-cipher + (generation) and cipher-hash (verification) requests in QAT PMD + when running on GEN2 QAT hardware with particular firmware versions + (GEN3 support was added in DPDK 20.02). + Removed Items ------------- diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c index 666ede726..41305ea56 100644 --- a/drivers/crypto/qat/qat_sym_pmd.c +++ b/drivers/crypto/qat/qat_sym_pmd.c @@ -14,6 +14,8 @@ #include "qat_sym_session.h" #include "qat_sym_pmd.h" +#define MIXED_CRYPTO_MIN_FW_VER 0x04090000 + uint8_t cryptodev_qat_driver_id; static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = { @@ -187,6 +189,31 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id, qat_sgl_dst); } + /* Get fw version from QAT (GEN2), skip if we've got it already */ + if (qp->qat_dev_gen == QAT_GEN2 && !(qat_private->internal_capabilities + & QAT_SYM_CAP_VALID)) { + ret = qat_cq_get_fw_version(qp); + + if (ret < 0) { + qat_sym_qp_release(dev, qp_id); + return ret; + } + + if (ret != 0) + QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d", + (ret >> 24) & 0xff, + (ret >> 16) & 0xff, + (ret >> 8) & 0xff); + else + QAT_LOG(DEBUG, "unknown QAT firmware version"); + + /* set capabilities based on the fw version */ + qat_private->internal_capabilities = QAT_SYM_CAP_VALID | + ((ret >= MIXED_CRYPTO_MIN_FW_VER) ? + QAT_SYM_CAP_MIXED_CRYPTO : 0); + ret = 0; + } + return ret; } diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h index a32c25abc..a5a31e512 100644 --- a/drivers/crypto/qat/qat_sym_pmd.h +++ b/drivers/crypto/qat/qat_sym_pmd.h @@ -15,6 +15,10 @@ /** Intel(R) QAT Symmetric Crypto PMD driver name */ #define CRYPTODEV_NAME_QAT_SYM_PMD crypto_qat +/* Internal capabilities */ +#define QAT_SYM_CAP_MIXED_CRYPTO (1 << 0) +#define QAT_SYM_CAP_VALID (1 << 31) + extern uint8_t cryptodev_qat_driver_id; /** private data structure for a QAT device. @@ -29,6 +33,7 @@ struct qat_sym_dev_private { const struct rte_cryptodev_capabilities *qat_dev_capabilities; /* QAT device symmetric crypto capabilities */ uint16_t min_enq_burst_threshold; + uint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */ }; int diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 4359f2f0b..bf6af60aa 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -459,18 +459,23 @@ qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session, } static void -qat_sym_session_handle_mixed(struct qat_sym_session *session) +qat_sym_session_handle_mixed(const struct rte_cryptodev *dev, + struct qat_sym_session *session) { + const struct qat_sym_dev_private *qat_private = dev->data->dev_private; + enum qat_device_gen min_dev_gen = (qat_private->internal_capabilities & + QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3; + if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 && session->qat_cipher_alg != ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) { - session->min_qat_dev_gen = QAT_GEN3; + session->min_qat_dev_gen = min_dev_gen; qat_sym_session_set_ext_hash_flags(session, 1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS); } else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 && session->qat_cipher_alg != ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) { - session->min_qat_dev_gen = QAT_GEN3; + session->min_qat_dev_gen = min_dev_gen; qat_sym_session_set_ext_hash_flags(session, 1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS); } else if ((session->aes_cmac || @@ -479,7 +484,7 @@ qat_sym_session_handle_mixed(struct qat_sym_session *session) ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 || session->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) { - session->min_qat_dev_gen = QAT_GEN3; + session->min_qat_dev_gen = min_dev_gen; qat_sym_session_set_ext_hash_flags(session, 0); } } @@ -532,7 +537,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev, if (ret < 0) return ret; /* Special handling of mixed hash+cipher algorithms */ - qat_sym_session_handle_mixed(session); + qat_sym_session_handle_mixed(dev, session); } break; case ICP_QAT_FW_LA_CMD_HASH_CIPHER: @@ -551,7 +556,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev, if (ret < 0) return ret; /* Special handling of mixed hash+cipher algorithms */ - qat_sym_session_handle_mixed(session); + qat_sym_session_handle_mixed(dev, session); } break; case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM: