diff mbox series

eal/arm64: remove internal macros

Message ID 20200309093844.30579-1-david.marchand@redhat.com (mailing list archive)
State Accepted, archived
Delegated to: David Marchand
Headers show
Series eal/arm64: remove internal macros | expand

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/iol-mellanox-Performance success Performance Testing PASS
ci/travis-robot success Travis build: passed
ci/iol-testing success Testing PASS
ci/iol-intel-Performance fail Performance Testing issues
ci/checkpatch warning coding style issues

Commit Message

David Marchand March 9, 2020, 9:38 a.m. UTC
No need to export dsb and dmb.
EAL memory barriers are the public API.

%s/\<\(d.b\)\>(\([^()]*\))$/asm volatile("\1 \2" : : : "memory")/

Signed-off-by: David Marchand <david.marchand@redhat.com>
---
 .../common/include/arch/arm/rte_atomic_64.h   | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

Comments

Gavin Hu March 9, 2020, 1:22 p.m. UTC | #1
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Jerin Jacob March 9, 2020, 4:17 p.m. UTC | #2
On Mon, Mar 9, 2020 at 3:09 PM David Marchand <david.marchand@redhat.com> wrote:
>
> No need to export dsb and dmb.
> EAL memory barriers are the public API.
>
> %s/\<\(d.b\)\>(\([^()]*\))$/asm volatile("\1 \2" : : : "memory")/
>
> Signed-off-by: David Marchand <david.marchand@redhat.com>

Acked-by: Jerin Jacob <jerinj@marvell.com>


> ---
>  .../common/include/arch/arm/rte_atomic_64.h   | 19 ++++++++-----------
>  1 file changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index 859ae129d8..7b7099cdc1 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -19,20 +19,17 @@ extern "C" {
>  #include <rte_compat.h>
>  #include <rte_debug.h>
>
> -#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
> -#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
> +#define rte_mb() asm volatile("dsb sy" : : : "memory")
>
> -#define rte_mb() dsb(sy)
> +#define rte_wmb() asm volatile("dsb st" : : : "memory")
>
> -#define rte_wmb() dsb(st)
> +#define rte_rmb() asm volatile("dsb ld" : : : "memory")
>
> -#define rte_rmb() dsb(ld)
> +#define rte_smp_mb() asm volatile("dmb ish" : : : "memory")
>
> -#define rte_smp_mb() dmb(ish)
> +#define rte_smp_wmb() asm volatile("dmb ishst" : : : "memory")
>
> -#define rte_smp_wmb() dmb(ishst)
> -
> -#define rte_smp_rmb() dmb(ishld)
> +#define rte_smp_rmb() asm volatile("dmb ishld" : : : "memory")
>
>  #define rte_io_mb() rte_mb()
>
> @@ -40,9 +37,9 @@ extern "C" {
>
>  #define rte_io_rmb() rte_rmb()
>
> -#define rte_cio_wmb() dmb(oshst)
> +#define rte_cio_wmb() asm volatile("dmb oshst" : : : "memory")
>
> -#define rte_cio_rmb() dmb(oshld)
> +#define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory")
>
>  /*------------------------ 128 bit atomic operations -------------------------*/
>
> --
> 2.23.0
>
David Marchand March 13, 2020, 9:47 a.m. UTC | #3
On Mon, Mar 9, 2020 at 10:39 AM David Marchand
<david.marchand@redhat.com> wrote:
>
> No need to export dsb and dmb.
> EAL memory barriers are the public API.
>
> %s/\<\(d.b\)\>(\([^()]*\))$/asm volatile("\1 \2" : : : "memory")/
>
> Signed-off-by: David Marchand <david.marchand@redhat.com>

Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>


Applied.
diff mbox series

Patch

diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 859ae129d8..7b7099cdc1 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -19,20 +19,17 @@  extern "C" {
 #include <rte_compat.h>
 #include <rte_debug.h>
 
-#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
-#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+#define rte_mb() asm volatile("dsb sy" : : : "memory")
 
-#define rte_mb() dsb(sy)
+#define rte_wmb() asm volatile("dsb st" : : : "memory")
 
-#define rte_wmb() dsb(st)
+#define rte_rmb() asm volatile("dsb ld" : : : "memory")
 
-#define rte_rmb() dsb(ld)
+#define rte_smp_mb() asm volatile("dmb ish" : : : "memory")
 
-#define rte_smp_mb() dmb(ish)
+#define rte_smp_wmb() asm volatile("dmb ishst" : : : "memory")
 
-#define rte_smp_wmb() dmb(ishst)
-
-#define rte_smp_rmb() dmb(ishld)
+#define rte_smp_rmb() asm volatile("dmb ishld" : : : "memory")
 
 #define rte_io_mb() rte_mb()
 
@@ -40,9 +37,9 @@  extern "C" {
 
 #define rte_io_rmb() rte_rmb()
 
-#define rte_cio_wmb() dmb(oshst)
+#define rte_cio_wmb() asm volatile("dmb oshst" : : : "memory")
 
-#define rte_cio_rmb() dmb(oshld)
+#define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory")
 
 /*------------------------ 128 bit atomic operations -------------------------*/