From patchwork Mon Jan 6 03:38:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 64216 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 87D60A04F1; Mon, 6 Jan 2020 04:35:57 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 54A6F1D51E; Mon, 6 Jan 2020 04:35:50 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id A96371D37E for ; Mon, 6 Jan 2020 04:35:47 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jan 2020 19:35:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,401,1571727600"; d="scan'208";a="216726328" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga007.fm.intel.com with ESMTP; 05 Jan 2020 19:35:45 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Jeb Cramer , Paul M Stillwell Jr Date: Mon, 6 Jan 2020 11:38:40 +0800 Message-Id: <20200106033851.43978-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200106033851.43978-1-qi.z.zhang@intel.com> References: <20191205123847.39579-1-qi.z.zhang@intel.com> <20200106033851.43978-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 01/12] net/ice/base: whitelist register for NVM access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Allow tools to access register offset 0xB8188 (GLGEN_RSTAT) for NVMUpdate operations. This is a read-only register, so risk of other issues stemming from this change is low. Even so, update the write command to prevent and reject any commands which attempt to write to this register, just like we do for GL_HICR_EN. Signed-off-by: Jeb Cramer Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_nvm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 1dbfc2dcc..2d92524f2 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -504,6 +504,7 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd) case GL_FWSTS: case GL_MNG_FWSM: case GLGEN_CSR_DEBUG_C: + case GLGEN_RSTAT: case GLPCI_LBARCTRL: case GLNVM_GENS: case GLNVM_FLA: @@ -579,9 +580,14 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd, if (status) return status; - /* The HICR_EN register is read-only */ - if (cmd->offset == GL_HICR_EN) + /* Reject requests to write to read-only registers */ + switch (cmd->offset) { + case GL_HICR_EN: + case GLGEN_RSTAT: return ICE_ERR_OUT_OF_RANGE; + default: + break; + } ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",