From patchwork Tue Oct 29 15:37:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 62168 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70439A00BE; Tue, 29 Oct 2019 16:37:56 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2CBA51BEE1; Tue, 29 Oct 2019 16:37:52 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 55D4C1BEC3 for ; Tue, 29 Oct 2019 16:37:38 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9TFTT6s003961; Tue, 29 Oct 2019 08:37:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=BJam82SYL7LDRzMh4mx8dahZvIU1YnpT9jylj/SRaP8=; b=eutIyNL8hmbyaoyfOPFyA/GqLuwZKMBTGpQ9t5pWFONVJraZoZ6YCZFnU673l/+4iG75 p8TnuTmCivnJFmvVv+Z5LdyaUbzlaGPBerPpWpwb9xWmmaGyzitSRBr+le4ToSdhT8CJ Brn2Nr9nqUIwLsK6Pr1s47e/h/On+AH3lCxF/lR6KWDHhm0isq4fzGy/+rqS0KlR7Yac wEzCkaR6HueppJcnsZkCCtgmX1RdEYaqFpBiYCQmSPx/oHEdirKWzTZXhdmJ7Bmbz90z xadzqxvkBcIKKjVCi84XuX70O06LsCq35I/fQ2S36hL2tV2baTr4BFM3GWQjd1s2fw+/ bg== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2vvnnp20sc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 29 Oct 2019 08:37:37 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 29 Oct 2019 08:37:35 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Tue, 29 Oct 2019 08:37:35 -0700 Received: from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.17.14]) by maili.marvell.com (Postfix) with ESMTP id D0DE33F703F; Tue, 29 Oct 2019 08:37:33 -0700 (PDT) From: To: , , , Thomas Monjalon CC: , Pavan Nikhilesh Date: Tue, 29 Oct 2019 21:07:18 +0530 Message-ID: <20191029153722.4547-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191029153722.4547-1-pbhagavatula@marvell.com> References: <20191029050312.2715-1-pbhagavatula@marvell.com> <20191029153722.4547-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-29_05:2019-10-28,2019-10-29 signatures=0 Subject: [dpdk-dev] [PATCH v15 3/7] ethdev: add validation to offloads set by PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Some PMDs cannot work when certain offloads are enable/disabled, as a workaround PMDs auto enable/disable offloads internally and expose it through dev->data->dev_conf.rxmode.offloads. After device specific dev_configure is called compare the requested offloads to the offloads exposed by the PMD and, if the PMD failed to enable a given offload then log it and return -EINVAL from rte_eth_dev_configure, else if the PMD failed to disable a given offload log and continue with rte_eth_dev_configure. Suggested-by: Andrew Rybchenko Signed-off-by: Pavan Nikhilesh Reviewed-by: Andrew Rybchenko --- lib/librte_ethdev/rte_ethdev.c | 59 ++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) -- 2.17.1 diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c index 3f45b9e9c..8c58da91c 100644 --- a/lib/librte_ethdev/rte_ethdev.c +++ b/lib/librte_ethdev/rte_ethdev.c @@ -1135,6 +1135,41 @@ rte_eth_dev_tx_offload_name(uint64_t offload) return name; } +static int +_rte_eth_dev_validate_offloads(uint16_t port_id, uint64_t req_offloads, + uint64_t set_offloads, + const char *(*f)(uint64_t)) +{ + uint64_t offloads_diff = req_offloads ^ set_offloads; + uint64_t offloads_req_diff, offloads_set_diff; + uint64_t offload; + uint8_t err = 0; + + /* Check if any offload is advertised but not enabled. */ + offloads_req_diff = offloads_diff & req_offloads; + while (offloads_req_diff) { + offload = 1ULL << __builtin_ctzll(offloads_req_diff); + offloads_req_diff &= ~offload; + RTE_ETHDEV_LOG(ERR, "Port %u failed to enable %s offload", + port_id, f(offload)); + err = 1; + } + + if (err) + return -EINVAL; + + /* Chech if any offload couldn't be disabled. */ + offloads_set_diff = offloads_diff & set_offloads; + while (offloads_set_diff) { + offload = 1ULL << __builtin_ctzll(offloads_set_diff); + offloads_set_diff &= ~offload; + RTE_ETHDEV_LOG(INFO, "Port %u failed to disable %s offload", + port_id, f(offload)); + } + + return 0; +} + int rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, const struct rte_eth_conf *dev_conf) @@ -1358,6 +1393,30 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, goto rollback; } + /* Validate Rx offloads. */ + diag = _rte_eth_dev_validate_offloads(port_id, + dev_conf->rxmode.offloads, + dev->data->dev_conf.rxmode.offloads, + rte_eth_dev_rx_offload_name); + if (diag != 0) { + rte_eth_dev_rx_queue_config(dev, 0); + rte_eth_dev_tx_queue_config(dev, 0); + ret = diag; + goto rollback; + } + + /* Validate Tx offloads. */ + diag = _rte_eth_dev_validate_offloads(port_id, + dev_conf->txmode.offloads, + dev->data->dev_conf.txmode.offloads, + rte_eth_dev_tx_offload_name); + if (diag != 0) { + rte_eth_dev_rx_queue_config(dev, 0); + rte_eth_dev_tx_queue_config(dev, 0); + ret = diag; + goto rollback; + } + return 0; rollback: