From patchwork Tue Oct 29 05:03:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 62133 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81AD7A00BE; Tue, 29 Oct 2019 06:03:54 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CA8091BEFA; Tue, 29 Oct 2019 06:03:42 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A83021BECE for ; Tue, 29 Oct 2019 06:03:27 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9T50OZv010940; Mon, 28 Oct 2019 22:03:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=bJgMbdbkHPMQjCbdnd+deAmJB0WrAUun4IXMDh4AVDo=; b=q6RB/O2l4T3aGKVyoajzpNZYiorjL3srrvAdK/UwSqW3bFp1VpGo6ze7juSDjmz+5ame nt/szF+lLTL6hkAWaUqR+TxGS9F7/AwFrzw51SfhG1nBSOzGslKlt4Pkb3L/MK0c7UBU nTB77sSqppL/mzhucglYudaMdc8xNswb9ZCgR9xm5xqEvsKfvfRIyvKMGjIMrUMu3vXL cuwOT972mkrNjXhkHY+TYd8hXFcr8yp0rdBwzu2FGv+GnTgeuKpC8XYejgIKnRg7owDK JguvqQEjUKWZzZ6z6a0uoICrwZxxe/Z9nicV2ieOFr8Mv05wN3h9pPtKwl6f4SiAyxtM CQ== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2vvkgq8qf3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 22:03:26 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Mon, 28 Oct 2019 22:03:25 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Mon, 28 Oct 2019 22:03:25 -0700 Received: from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255]) by maili.marvell.com (Postfix) with ESMTP id E23D13F7040; Mon, 28 Oct 2019 22:03:23 -0700 (PDT) From: To: , , , Thomas Monjalon CC: , Pavan Nikhilesh Date: Tue, 29 Oct 2019 10:33:07 +0530 Message-ID: <20191029050312.2715-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191029050312.2715-1-pbhagavatula@marvell.com> References: <20191025143314.11162-1-pbhagavatula@marvell.com> <20191029050312.2715-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-29_02:2019-10-28,2019-10-29 signatures=0 Subject: [dpdk-dev] [PATCH v14 3/7] ethdev: log offloads that can't be disabled by PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Some PMD can't work when certain offloads are disabled, to work around this the PMD auto enable the offloads internally and expose it through dev->data->dev_conf.rxmode.offloads. After dev_configure is called compare the requested offloads to the enabled offloads and log any offloads that have been enabled by the PMD. Suggested-by: Andrew Rybchenko Signed-off-by: Pavan Nikhilesh --- lib/librte_ethdev/rte_ethdev.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c index fef1dbb61..7dfc2f691 100644 --- a/lib/librte_ethdev/rte_ethdev.c +++ b/lib/librte_ethdev/rte_ethdev.c @@ -1142,6 +1142,8 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, struct rte_eth_dev *dev; struct rte_eth_dev_info dev_info; struct rte_eth_conf orig_conf; + uint64_t offloads_force_ena; + uint64_t offload; int diag; int ret; @@ -1357,6 +1359,26 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, goto rollback; } + /* Extract Rx offload bits that can't be disabled and log them */ + offloads_force_ena = dev_conf->rxmode.offloads ^ + dev->data->dev_conf.rxmode.offloads; + while (__builtin_popcount(offloads_force_ena)) { + offload = 1ULL << __builtin_ctzll(offloads_force_ena); + offloads_force_ena &= ~offload; + RTE_ETHDEV_LOG(INFO, "Port %u can't disable Rx offload %s\n", + port_id, rte_eth_dev_rx_offload_name(offload)); + } + + /* Extract Tx offload bits that can't be disabled and log them */ + offloads_force_ena = dev_conf->txmode.offloads ^ + dev->data->dev_conf.txmode.offloads; + while (__builtin_popcount(offloads_force_ena)) { + offload = 1ULL << __builtin_ctzll(offloads_force_ena); + offloads_force_ena &= ~offload; + RTE_ETHDEV_LOG(INFO, "Port %u can't disable Tx offload %s\n", + port_id, rte_eth_dev_tx_offload_name(offload)); + } + return 0; rollback: