From patchwork Wed Oct 23 15:20:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Kumar Kokkilagadda X-Patchwork-Id: 61773 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 08ADD271; Wed, 23 Oct 2019 17:21:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id B10801C436 for ; Wed, 23 Oct 2019 17:21:25 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9NFBSRH024657; Wed, 23 Oct 2019 08:21:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=2WPS9K+OK9Flolf1vrzwjPWRjvGKH/vQCjBamRwHiQs=; b=K/nVXoc5HPqnUqWM7TnmX96UQwn4zWKlzRIYlk9XYV4Z8wxKdqezVQMm9+pKMJyIHNaP /gE5unwSBvYs4H9WaSUbP6RxTHy+DdQLATl5iNPoqxUrgAtZtlnC0g0iR9rVURzrOsCA oPRcxGRC6KlTsTvHSFSuuYl06GNQFnM7eldzb+mRrnr8Q4F29okLiFy2NZbs2E83pwBp 38c6t9ZSfNcK8LTZpNncY+W7VRzqXLiWmuk5ivBrvlgQEGuZ1KPUARqfzoPrYitCoLju 81Bu+zZMjVzkQE7O4Pz+sVx05jxE+ddniW0oq6qHZtRO6j6Zwysm1mIuNgC+jO3+eOR3 og== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 2vt9u5kccx-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 23 Oct 2019 08:21:24 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Wed, 23 Oct 2019 08:21:23 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Wed, 23 Oct 2019 08:21:23 -0700 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id C9F823F703F; Wed, 23 Oct 2019 08:21:21 -0700 (PDT) From: To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K , "John McNamara" , Marko Kovacevic , Vamsi Attunuru CC: Date: Wed, 23 Oct 2019 20:50:41 +0530 Message-ID: <20191023152043.17887-1-kirankumark@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-23_04:2019-10-23,2019-10-23 signatures=0 Subject: [dpdk-dev] [PATCH 1/2] net/octeontx2: add support to enable switch type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar K Adding support to configure specific switch types like high2 and dsa on a port. When this switch type is configured, it is expected that all the traffic on that port should be of specific type only. Change-Id: I41c47c4f8d844666cd6afe20a60397b83908e2f4 Signed-off-by: Kiran Kumar K --- doc/guides/nics/octeontx2.rst | 12 +++++++++ drivers/common/octeontx2/otx2_mbox.h | 19 ++++++++++++- drivers/net/octeontx2/otx2_ethdev.c | 30 +++++++++++++++++++++ drivers/net/octeontx2/otx2_ethdev_devargs.c | 22 ++++++++++++++- drivers/net/octeontx2/otx2_flow.h | 1 + 5 files changed, 82 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst index fc8a130fb..adf7c7131 100644 --- a/doc/guides/nics/octeontx2.rst +++ b/doc/guides/nics/octeontx2.rst @@ -170,6 +170,18 @@ Runtime Config Options With the above configuration, each send queue's decscriptor buffer count is limited to a maximum of 64 buffers. +- ``switch header enable`` (default ``none``) + + A port can be configured to a specific switch header type by using + ``switch_header`` ``devargs`` parameter. + + For example:: + + -w 0002:02:00.0,switch_header="higig2" + + With the above configuration, higig2 will be enabled on that port and the + traffic on this port should be higig2 traffic only. Supported switch header + types are "higig2" and "dsa". .. note:: diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h index 445b03e26..c2a9e9fe6 100644 --- a/drivers/common/octeontx2/otx2_mbox.h +++ b/drivers/common/octeontx2/otx2_mbox.h @@ -89,7 +89,7 @@ struct mbox_msghdr { #define OTX2_MBOX_RSP_SIG (0xbeef) /* Signature, for validating corrupted msgs */ uint16_t __otx2_io sig; -#define OTX2_MBOX_VERSION (0x0002) +#define OTX2_MBOX_VERSION (0x0003) /* Version of msg's structure for this ID */ uint16_t __otx2_io ver; /* Offset of next msg within mailbox region */ @@ -236,6 +236,9 @@ M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ npc_mcam_read_entry_req, \ npc_mcam_read_entry_rsp) \ +M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ + npc_set_pkind, \ + msg_rsp) \ /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \ nix_lf_alloc_rsp) \ @@ -329,6 +332,20 @@ struct ready_msg_rsp { uint16_t __otx2_io rclk_freq; /* RCLK frequency */ }; +/* Struct to set pkind */ +struct npc_set_pkind { + struct mbox_msghdr hdr; +#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) +#define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1) +#define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2) +#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) + uint64_t __otx2_io mode; +#define PKIND_TX BIT_ULL(0) +#define PKIND_RX BIT_ULL(1) + uint8_t __otx2_io dir; + uint8_t __otx2_io pkind; /* valid only in case custom flag */ +}; + /* Structure for requesting resource provisioning. * 'modify' flag to be used when either requesting more * or detach partial of a certain resource type. diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index 62291c698..dfa8cd205 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -90,6 +90,30 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq) return 0; } +static int +nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev) +{ + struct otx2_mbox *mbox = dev->mbox; + struct npc_set_pkind *req; + struct msg_resp *rsp; + int rc; + + if (dev->npc_flow.switch_header_type == 0) + return 0; + + /* Notify AF about higig2 config */ + req = otx2_mbox_alloc_msg_npc_set_pkind(mbox); + req->mode = dev->npc_flow.switch_header_type; + req->dir = PKIND_RX; + rc = otx2_mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return rc; + req = otx2_mbox_alloc_msg_npc_set_pkind(mbox); + req->mode = dev->npc_flow.switch_header_type; + req->dir = PKIND_TX; + return otx2_mbox_process_msg(mbox, (void *)&rsp); +} + static int nix_lf_free(struct otx2_eth_dev *dev) { @@ -1612,6 +1636,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev) goto fail_offloads; } + rc = nix_lf_switch_header_type_enable(dev); + if (rc) { + otx2_err("Failed to enable switch type nix_lf rc=%d", rc); + goto free_nix_lf; + } + rc = nix_setup_lso_formats(dev); if (rc) { otx2_err("failed to setup nix lso format fields, rc=%d", rc); diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c index 7dc6e92be..ca9a5ffb8 100644 --- a/drivers/net/octeontx2/otx2_ethdev_devargs.c +++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c @@ -104,12 +104,27 @@ parse_sqb_count(const char *key, const char *value, void *extra_args) return 0; } +static int +parse_switch_header_type(const char *key, const char *value, void *extra_args) +{ + RTE_SET_USED(key); + + if (strcmp(value, "higig2") == 0) + *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG; + + if (strcmp(value, "dsa") == 0) + *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA; + + return 0; +} + #define OTX2_RSS_RETA_SIZE "reta_size" #define OTX2_PTYPE_DISABLE "ptype_disable" #define OTX2_SCL_ENABLE "scalar_enable" #define OTX2_MAX_SQB_COUNT "max_sqb_count" #define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size" #define OTX2_FLOW_MAX_PRIORITY "flow_max_priority" +#define OTX2_SWITCH_HEADER_TYPE "switch_header" int otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) @@ -118,6 +133,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) uint16_t rss_size = NIX_RSS_RETA_SIZE; uint16_t sqb_count = NIX_MAX_SQB; uint16_t flow_prealloc_size = 8; + uint16_t switch_header_type = 0; uint16_t flow_max_priority = 3; uint16_t scalar_enable = 0; struct rte_kvargs *kvlist; @@ -141,6 +157,8 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) &parse_flow_prealloc_size, &flow_prealloc_size); rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY, &parse_flow_max_priority, &flow_max_priority); + rte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE, + &parse_switch_header_type, &switch_header_type); rte_kvargs_free(kvlist); null_devargs: @@ -150,6 +168,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) dev->rss_info.rss_size = rss_size; dev->npc_flow.flow_prealloc_size = flow_prealloc_size; dev->npc_flow.flow_max_priority = flow_max_priority; + dev->npc_flow.switch_header_type = switch_header_type; return 0; exit: @@ -162,4 +181,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2, OTX2_SCL_ENABLE "=1" OTX2_MAX_SQB_COUNT "=<8-512>" OTX2_FLOW_PREALLOC_SIZE "=<1-32>" - OTX2_FLOW_MAX_PRIORITY "=<1-32>"); + OTX2_FLOW_MAX_PRIORITY "=<1-32>" + OTX2_SWITCH_HEADER_TYPE "="); diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h index ab068b088..6bfd5afde 100644 --- a/drivers/net/octeontx2/otx2_flow.h +++ b/drivers/net/octeontx2/otx2_flow.h @@ -190,6 +190,7 @@ struct otx2_npc_flow_info { uint16_t channel; /*rx channel */ uint16_t flow_prealloc_size; uint16_t flow_max_priority; + uint16_t switch_header_type; }; struct otx2_parse_state {