From patchwork Fri Sep 27 06:26:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagadheeraj Rottela X-Patchwork-Id: 59956 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C20BA2C37; Fri, 27 Sep 2019 08:26:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id CAB611E34 for ; Fri, 27 Sep 2019 08:26:29 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8R5nZuG002309; Thu, 26 Sep 2019 23:26:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=gmoJND0c0j3ShNiWvxYSRQ+WHQKtBF9lZ2hux8cfJYk=; b=XZItLDgpSdIUvBxTxl4Rem/6n0F7lUd3tf4kDPatDNc3onEGnSAxKkFNCaYgDAlUXX1H ZxO4IQgMIEjUgqk12Eogz96OXMoUwDQv6Qo5bOyD0kiAGe9qmK0Vb8wpPVhRbesRS7EL iBd6gSfF7qAJuZ0qhGFEYwjUzCAytF1SKJ+/F/FH8dbCRUdjixZSJxTAUvqyLyopkn6F qPnXmQlcwJk68CrJhBjc9urhGdV4Zf+Uf5b1SSgxrgnizDLXjXipmB7a1eW3S91fno8Z G2UJ6jJcd0XR23pbfinVeH1sF+KCSdENxFnaUdNdIQDJXfKowHcCbEXPooy+UXPtPwXX 6Q== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2v8vf2468a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2019 23:26:28 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 26 Sep 2019 23:26:27 -0700 Received: from NAM05-DM3-obe.outbound.protection.outlook.com (104.47.49.58) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Thu, 26 Sep 2019 23:26:26 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cPFm1DsfaLDW0sI/QwELiPbn1Ow3GipbMVcAgM3yKZ8ybK+m9rpDziqcX4CvLoX8XLFuy59RY/+pHRqX/4H+fo+PwmDubkA585RyiHaYlaAc6pm5RPWeji20MJHYgS6n9IdRKA7m21bN30YhN6Xb/sdnrm9zcv1Er+yY8CQaAcU0xMZAMyFI+7O+QrHbA3aRxkKlX01r4dMXljUyvaJ9LOOQDAdyys5e+VWbPw3nCMhGcBEouuqI9YE61YZRrFMhXFr0s4xHkqfb4qgBDbgSIGT8hB1x9VNDn0CuXnlqbesdY+3ba/Z8/VEfijmb6OBm5Mlm6Mz5MqVrDH4rKGFaRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gmoJND0c0j3ShNiWvxYSRQ+WHQKtBF9lZ2hux8cfJYk=; b=GJJy7zJvWimMxiwVJc4HqrxYlGtMOoi54YrKYRaUaygKlpNf5rMisi08NoQ+rgzzuaHuCbRbCLSpm3nmwREOR1O5z9HuJ0ClhpbUIGRtgg36I/BxP2nkoZlpWcXHGRHWLaj3rEs22bGk1hDZUs9ofkz92sFnG/lDeWr+JkR4S32oW0uoOGJpqfGvm5BT6+LZ5V0vllLwZYlyn7ZpCb1NSrBOuv8nqKzD33R04grvjvwbXhIPpGb/g7+KJ6EPp9YsRTCRUNOk3z5QZoO1R1Zn8vbAFROVeNlhqQwobVLLJwPl4ImRX16HgoSJiFeVPKUwf9Jm+xmxXsj+7qIoWhnkdw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com; dkim=pass header.d=marvell.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector2-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gmoJND0c0j3ShNiWvxYSRQ+WHQKtBF9lZ2hux8cfJYk=; b=Is7ZxuPXQzoF+CFHffG3HhZREHiDWlgf7Gnji8D7ZI1y7NO3ju5Z5nbr9YFiXzt1HWFk3h1KK5Q991UPgsEn04RygA9pHDyhZZAaI0kRNYcoZ8cB1fv2nu906CNdqSeMSAEtOqQ4rl5qXHQmXTopuFkS3hE7Oq7t07Lw8Z/0tTo= Received: from BYAPR18MB2792.namprd18.prod.outlook.com (20.179.56.216) by BYAPR18MB2984.namprd18.prod.outlook.com (20.179.59.97) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2284.19; Fri, 27 Sep 2019 06:26:25 +0000 Received: from BYAPR18MB2792.namprd18.prod.outlook.com ([fe80::7112:68c6:eb44:e9aa]) by BYAPR18MB2792.namprd18.prod.outlook.com ([fe80::7112:68c6:eb44:e9aa%3]) with mapi id 15.20.2284.028; Fri, 27 Sep 2019 06:26:25 +0000 From: Nagadheeraj Rottela To: "akhil.goyal@nxp.com" , "pablo.de.lara.guarch@intel.com" CC: Srikanth Jampala , "dev@dpdk.org" , Nagadheeraj Rottela Thread-Topic: [PATCH v6 1/8] crypto/nitrox: add Nitrox PMD library Thread-Index: AQHVdPx91b4XK9MXGUmk2oy8+ZyGDQ== Date: Fri, 27 Sep 2019 06:26:25 +0000 Message-ID: <20190927062533.19005-2-rnagadheeraj@marvell.com> References: <20190716091016.4788-1-rnagadheeraj@marvell.com> <20190927062533.19005-1-rnagadheeraj@marvell.com> In-Reply-To: <20190927062533.19005-1-rnagadheeraj@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR0101CA0025.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:c::11) To BYAPR18MB2792.namprd18.prod.outlook.com (2603:10b6:a03:105::24) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.13.6 x-originating-ip: [115.113.156.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 21f0c945-f84b-48f9-a058-08d743139f69 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:BYAPR18MB2984; x-ms-traffictypediagnostic: BYAPR18MB2984: x-ms-exchange-purlcount: 2 x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2733; x-forefront-prvs: 0173C6D4D5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(376002)(136003)(366004)(39860400002)(346002)(189003)(199004)(6436002)(26005)(30864003)(2906002)(107886003)(14444005)(102836004)(3846002)(1076003)(66066001)(14454004)(6486002)(55236004)(36756003)(305945005)(256004)(478600001)(186003)(6506007)(66946007)(110136005)(76176011)(8936002)(8676002)(54906003)(6116002)(71190400001)(5660300002)(71200400001)(52116002)(386003)(66556008)(66446008)(446003)(11346002)(2501003)(86362001)(81166006)(64756008)(966005)(316002)(4326008)(66476007)(25786009)(6306002)(50226002)(99286004)(2616005)(476003)(7736002)(486006)(81156014)(6512007); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2984; H:BYAPR18MB2792.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: QXbSj2UR3eZrPsd9/orle4PJu/TxcQWcjU2CrRG1i2ifOmu3ysxYrkK7hf6CX98ezg3yPbuLDnLq0FPKJEH3X/bpii29yIxiDhq5ltC9fcpXx6o7flumA8sXtYxbxWcnpa/YBqOVWdrfNR6gz/zae1cDIpz0kKcn7es0oNW5yOuKpUWYxu9YHkZMMuqKxMANBG3luTbHwGD/KUj++4L1uvRRYAb2VDNxAGWCRMg1s4lMXWiycjGFCwllGyWHB+5crP06jLnwXuDyWkkdzaDIOgZRmxaJ/QPhij6n3rBoRKMBwrEoJLpxqqqIy8Ko11WC9a3CXCA2Mr8ryOOQcV7GAiHai9me7maNHfyXF7XBB1+EuyW3A9H5pdVZWBRlfK0x5yM9xJpR+sHsXvAjGFWXKVeUMeAdkTLFqc15Tklmw1NKZK/orN2tK7Bxgr3NmsdCCqm4SniFt8+plgANNa3T6w== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 21f0c945-f84b-48f9-a058-08d743139f69 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Sep 2019 06:26:25.6102 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jDtCCeheRA0ex4EkbWfzzD8UOmu2TQwuoF1iiPwu+vY917nXWA6BwDxC7ceXQlewldDwBE7QT8/C8VslL5Ev9pTy7+UKFrvsXnm5doApaUs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2984 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-09-27_04:2019-09-25,2019-09-27 signatures=0 Subject: [dpdk-dev] [PATCH v6 1/8] crypto/nitrox: add Nitrox PMD library X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add bare minimum Nitrox PMD library which handles pci probe, remove and hardware initialization. Add logs, documentation and update maintainers file. Signed-off-by: Nagadheeraj Rottela --- MAINTAINERS | 7 ++ config/common_base | 5 + doc/guides/cryptodevs/index.rst | 1 + doc/guides/cryptodevs/nitrox.rst | 30 ++++++ drivers/crypto/Makefile | 1 + drivers/crypto/meson.build | 4 +- drivers/crypto/nitrox/Makefile | 30 ++++++ drivers/crypto/nitrox/meson.build | 15 +++ drivers/crypto/nitrox/nitrox_csr.h | 28 ++++++ drivers/crypto/nitrox/nitrox_device.c | 111 +++++++++++++++++++++++ drivers/crypto/nitrox/nitrox_device.h | 18 ++++ drivers/crypto/nitrox/nitrox_hal.c | 85 +++++++++++++++++ drivers/crypto/nitrox/nitrox_hal.h | 37 ++++++++ drivers/crypto/nitrox/nitrox_logs.c | 14 +++ drivers/crypto/nitrox/nitrox_logs.h | 15 +++ drivers/crypto/nitrox/rte_pmd_nitrox_version.map | 3 + mk/rte.app.mk | 1 + 17 files changed, 403 insertions(+), 2 deletions(-) create mode 100644 doc/guides/cryptodevs/nitrox.rst create mode 100644 drivers/crypto/nitrox/Makefile create mode 100644 drivers/crypto/nitrox/meson.build create mode 100644 drivers/crypto/nitrox/nitrox_csr.h create mode 100644 drivers/crypto/nitrox/nitrox_device.c create mode 100644 drivers/crypto/nitrox/nitrox_device.h create mode 100644 drivers/crypto/nitrox/nitrox_hal.c create mode 100644 drivers/crypto/nitrox/nitrox_hal.h create mode 100644 drivers/crypto/nitrox/nitrox_logs.c create mode 100644 drivers/crypto/nitrox/nitrox_logs.h create mode 100644 drivers/crypto/nitrox/rte_pmd_nitrox_version.map diff --git a/MAINTAINERS b/MAINTAINERS index b3d9aaddd..c881fd023 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -963,6 +963,13 @@ F: drivers/crypto/mvsam/ F: doc/guides/cryptodevs/mvsam.rst F: doc/guides/cryptodevs/features/mvsam.ini +Nitrox +M: Nagadheeraj Rottela +M: Srikanth Jampala +F: drivers/crypto/nitrox/ +F: doc/guides/cryptodevs/nitrox.rst +F: doc/guides/cryptodevs/features/nitrox.ini + Null Crypto M: Declan Doherty F: drivers/crypto/null/ diff --git a/config/common_base b/config/common_base index 8ef75c203..92ecb4a68 100644 --- a/config/common_base +++ b/config/common_base @@ -664,6 +664,11 @@ CONFIG_RTE_LIBRTE_PMD_CCP=n CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=n # +# Compile PMD for NITROX crypto device +# +CONFIG_RTE_LIBRTE_PMD_NITROX=y + +# # Compile generic security library # CONFIG_RTE_LIBRTE_SECURITY=y diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst index 83610e64f..d1e0d3203 100644 --- a/doc/guides/cryptodevs/index.rst +++ b/doc/guides/cryptodevs/index.rst @@ -21,6 +21,7 @@ Crypto Device Drivers octeontx openssl mvsam + nitrox null scheduler snow3g diff --git a/doc/guides/cryptodevs/nitrox.rst b/doc/guides/cryptodevs/nitrox.rst new file mode 100644 index 000000000..cb7f92755 --- /dev/null +++ b/doc/guides/cryptodevs/nitrox.rst @@ -0,0 +1,30 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(C) 2019 Marvell International Ltd. + +Marvell NITROX Crypto Poll Mode Driver +====================================== + +The Nitrox crypto poll mode driver provides support for offloading +cryptographic operations to the NITROX V security processor. Detailed +information about the NITROX V security processor can be obtained here: + +* https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/ + +Installation +------------ + +For compiling the Nitrox crypto PMD, please check if the +CONFIG_RTE_LIBRTE_PMD_NITROX setting is set to `y` in config/common_base file. + +* ``CONFIG_RTE_LIBRTE_PMD_NITROX=y`` + +Initialization +-------------- + +Nitrox crypto PMD depend on Nitrox kernel PF driver being installed on the +platform. Nitrox PF driver is required to create VF devices which will +be used by the PMD. Each VF device can enable one cryptodev PMD. + +Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SDK +and it's installation instructions can be obtained from: +`Marvell Technical Documentation Portal `_. diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 009f8443d..7129bcfc9 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -25,5 +25,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += caam_jr endif # CONFIG_RTE_LIBRTE_PMD_DPAA_SEC endif # CONFIG_RTE_LIBRTE_SECURITY DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += virtio +DIRS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox include $(RTE_SDK)/mk/rte.subdir.mk diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index 83e78860e..1a358ff8b 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -2,8 +2,8 @@ # Copyright(c) 2017 Intel Corporation drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec', - 'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler', - 'snow3g', 'virtio', 'zuc'] + 'kasumi', 'mvsam', 'nitrox', 'null', 'octeontx', 'openssl', 'qat', + 'scheduler', 'snow3g', 'virtio', 'zuc'] std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps config_flag_fmt = 'RTE_LIBRTE_@0@_PMD' diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile new file mode 100644 index 000000000..7681a6603 --- /dev/null +++ b/drivers/crypto/nitrox/Makefile @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2019 Marvell International Ltd. + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB = librte_pmd_nitrox.a + +# build flags +CFLAGS += -O3 +CFLAGS += $(WERROR_FLAGS) +CFLAGS += -DALLOW_EXPERIMENTAL_API + +# library version +LIBABIVER := 1 + +# versioning export map +EXPORT_MAP := rte_pmd_nitrox_version.map + +# external library dependencies +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool +LDLIBS += -lrte_pci -lrte_bus_pci +LDLIBS += -lrte_cryptodev + +# library source files +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build new file mode 100644 index 000000000..ad81f8cd8 --- /dev/null +++ b/drivers/crypto/nitrox/meson.build @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2019 Marvell International Ltd. + +if not is_linux + build = false + reason = 'only supported on Linux' +endif + +deps += ['bus_pci'] +allow_experimental_apis = true +sources = files( + 'nitrox_device.c', + 'nitrox_hal.c', + 'nitrox_logs.c', + ) diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h new file mode 100644 index 000000000..879104515 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_csr.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_CSR_H_ +#define _NITROX_CSR_H_ + +#include +#include + +#define CSR_DELAY 30 + +/* AQM Virtual Function Registers */ +#define AQMQ_QSZX(_i) (0x20008 + ((_i)*0x40000)) + +static inline uint64_t +nitrox_read_csr(uint8_t *bar_addr, uint64_t offset) +{ + return rte_read64(bar_addr + offset); +} + +static inline void +nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value) +{ + rte_write64(value, (bar_addr + offset)); +} + +#endif /* _NITROX_CSR_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_device.c b/drivers/crypto/nitrox/nitrox_device.c new file mode 100644 index 000000000..a73528211 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_device.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include + +#include "nitrox_device.h" +#include "nitrox_hal.h" + +#define PCI_VENDOR_ID_CAVIUM 0x177d +#define NITROX_V_PCI_VF_DEV_ID 0x13 + +TAILQ_HEAD(ndev_list, nitrox_device); +static struct ndev_list ndev_list = TAILQ_HEAD_INITIALIZER(ndev_list); + +static struct nitrox_device * +ndev_allocate(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + ndev = rte_zmalloc_socket("nitrox device", sizeof(*ndev), + RTE_CACHE_LINE_SIZE, + pdev->device.numa_node); + if (!ndev) + return NULL; + + TAILQ_INSERT_TAIL(&ndev_list, ndev, next); + return ndev; +} + +static void +ndev_init(struct nitrox_device *ndev, struct rte_pci_device *pdev) +{ + enum nitrox_vf_mode vf_mode; + + ndev->pdev = pdev; + ndev->bar_addr = pdev->mem_resource[0].addr; + vf_mode = vf_get_vf_config_mode(ndev->bar_addr); + ndev->nr_queues = vf_config_mode_to_nr_queues(vf_mode); +} + +static struct nitrox_device * +find_ndev(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + TAILQ_FOREACH(ndev, &ndev_list, next) + if (ndev->pdev == pdev) + return ndev; + + return NULL; +} + +static void +ndev_release(struct nitrox_device *ndev) +{ + if (!ndev) + return; + + TAILQ_REMOVE(&ndev_list, ndev, next); + rte_free(ndev); +} + +static int +nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + /* Nitrox CSR space */ + if (!pdev->mem_resource[0].addr) + return -EINVAL; + + ndev = ndev_allocate(pdev); + if (!ndev) + return -ENOMEM; + + ndev_init(ndev, pdev); + return 0; +} + +static int +nitrox_pci_remove(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + ndev = find_ndev(pdev); + if (!ndev) + return -ENODEV; + + ndev_release(ndev); + return 0; +} + +static struct rte_pci_id pci_id_nitrox_map[] = { + { + /* Nitrox 5 VF */ + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, NITROX_V_PCI_VF_DEV_ID) + }, + {.device_id = 0}, +}; + +static struct rte_pci_driver nitrox_pmd = { + .id_table = pci_id_nitrox_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = nitrox_pci_probe, + .remove = nitrox_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(nitrox, nitrox_pmd); +RTE_PMD_REGISTER_PCI_TABLE(nitrox, pci_id_nitrox_map); diff --git a/drivers/crypto/nitrox/nitrox_device.h b/drivers/crypto/nitrox/nitrox_device.h new file mode 100644 index 000000000..0d0167de2 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_device.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_DEVICE_H_ +#define _NITROX_DEVICE_H_ + +#include +#include + +struct nitrox_device { + TAILQ_ENTRY(nitrox_device) next; + struct rte_pci_device *pdev; + uint8_t *bar_addr; + uint16_t nr_queues; +}; + +#endif /* _NITROX_DEVICE_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_hal.c b/drivers/crypto/nitrox/nitrox_hal.c new file mode 100644 index 000000000..ed1882016 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_hal.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include +#include +#include +#include + +#include "nitrox_hal.h" +#include "nitrox_csr.h" + +#define MAX_VF_QUEUES 8 +#define MAX_PF_QUEUES 64 + +int +vf_get_vf_config_mode(uint8_t *bar_addr) +{ + union aqmq_qsz aqmq_qsz; + uint64_t reg_addr; + int q, vf_mode; + + aqmq_qsz.u64 = 0; + aqmq_qsz.s.host_queue_size = 0xDEADBEEF; + reg_addr = AQMQ_QSZX(0); + nitrox_write_csr(bar_addr, reg_addr, aqmq_qsz.u64); + rte_delay_us_block(CSR_DELAY); + + aqmq_qsz.u64 = 0; + for (q = 1; q < MAX_VF_QUEUES; q++) { + reg_addr = AQMQ_QSZX(q); + aqmq_qsz.u64 = nitrox_read_csr(bar_addr, reg_addr); + if (aqmq_qsz.s.host_queue_size == 0xDEADBEEF) + break; + } + + switch (q) { + case 1: + vf_mode = NITROX_MODE_VF128; + break; + case 2: + vf_mode = NITROX_MODE_VF64; + break; + case 4: + vf_mode = NITROX_MODE_VF32; + break; + case 8: + vf_mode = NITROX_MODE_VF16; + break; + default: + vf_mode = 0; + break; + } + + return vf_mode; +} + +int +vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode) +{ + int nr_queues; + + switch (vf_mode) { + case NITROX_MODE_PF: + nr_queues = MAX_PF_QUEUES; + break; + case NITROX_MODE_VF16: + nr_queues = 8; + break; + case NITROX_MODE_VF32: + nr_queues = 4; + break; + case NITROX_MODE_VF64: + nr_queues = 2; + break; + case NITROX_MODE_VF128: + nr_queues = 1; + break; + default: + nr_queues = 0; + break; + } + + return nr_queues; +} diff --git a/drivers/crypto/nitrox/nitrox_hal.h b/drivers/crypto/nitrox/nitrox_hal.h new file mode 100644 index 000000000..6184211a5 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_hal.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_HAL_H_ +#define _NITROX_HAL_H_ + +#include +#include + +#include "nitrox_csr.h" + +union aqmq_qsz { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t raz : 32; + uint64_t host_queue_size : 32; +#else + uint64_t host_queue_size : 32; + uint64_t raz : 32; +#endif + } s; +}; + +enum nitrox_vf_mode { + NITROX_MODE_PF = 0x0, + NITROX_MODE_VF16 = 0x1, + NITROX_MODE_VF32 = 0x2, + NITROX_MODE_VF64 = 0x3, + NITROX_MODE_VF128 = 0x4, +}; + +int vf_get_vf_config_mode(uint8_t *bar_addr); +int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode); + +#endif /* _NITROX_HAL_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_logs.c b/drivers/crypto/nitrox/nitrox_logs.c new file mode 100644 index 000000000..007056cb4 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_logs.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include + +int nitrox_logtype; + +RTE_INIT(nitrox_init_log) +{ + nitrox_logtype = rte_log_register("pmd.crypto.nitrox"); + if (nitrox_logtype >= 0) + rte_log_set_level(nitrox_logtype, RTE_LOG_NOTICE); +} diff --git a/drivers/crypto/nitrox/nitrox_logs.h b/drivers/crypto/nitrox/nitrox_logs.h new file mode 100644 index 000000000..50e52f396 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_logs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_LOGS_H_ +#define _NITROX_LOGS_H_ + +#define LOG_PREFIX "NITROX: " +#define NITROX_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, nitrox_logtype, \ + LOG_PREFIX "%s:%d " fmt, __func__, __LINE__, ## args) + +extern int nitrox_logtype; + +#endif /* _NITROX_LOGS_H_ */ diff --git a/drivers/crypto/nitrox/rte_pmd_nitrox_version.map b/drivers/crypto/nitrox/rte_pmd_nitrox_version.map new file mode 100644 index 000000000..0a539ae48 --- /dev/null +++ b/drivers/crypto/nitrox/rte_pmd_nitrox_version.map @@ -0,0 +1,3 @@ +DPDK_19.08 { + local: *; +}; diff --git a/mk/rte.app.mk b/mk/rte.app.mk index ba5c39e01..fb496692b 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -279,6 +279,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += -lrte_pmd_caam_jr endif # CONFIG_RTE_LIBRTE_DPAA_BUS endif # CONFIG_RTE_LIBRTE_SECURITY _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += -lrte_pmd_virtio_crypto +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += -lrte_pmd_nitrox endif # CONFIG_RTE_LIBRTE_CRYPTODEV ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)