From patchwork Fri Sep 20 12:44:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dybkowski, AdamX" X-Patchwork-Id: 59503 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1E94E1F3E1; Fri, 20 Sep 2019 14:46:17 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 886AC1F3C5 for ; Fri, 20 Sep 2019 14:46:13 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Sep 2019 05:46:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,528,1559545200"; d="scan'208";a="202497038" Received: from adamdybx-mobl.ger.corp.intel.com (HELO localhost.localdomain) ([10.104.12.169]) by fmsmga001.fm.intel.com with ESMTP; 20 Sep 2019 05:46:11 -0700 From: Adam Dybkowski To: dev@dpdk.org, fiona.trahe@intel.com, arturx.trybula@intel.com, akhil.goyal@nxp.com Cc: Adam Dybkowski Date: Fri, 20 Sep 2019 14:44:50 +0200 Message-Id: <20190920124452.29449-2-adamx.dybkowski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190920124452.29449-1-adamx.dybkowski@intel.com> References: <20190826074501.10653-1-adamx.dybkowski@intel.com> <20190920124452.29449-1-adamx.dybkowski@intel.com> Subject: [dpdk-dev] [PATCH v2 1/3] common/qat: add QAT RAM bank definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds QAT RAM bank definitions and related macros. Signed-off-by: Adam Dybkowski --- drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 73 ++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h index 813817720..c89a2c2fd 100644 --- a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h +++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h @@ -479,4 +479,77 @@ struct icp_qat_fw_comp_resp { /**< Common response params (checksums and byte counts) */ }; +/* RAM Bank definitions */ +#define QAT_FW_COMP_BANK_FLAG_MASK 0x1 + +#define QAT_FW_COMP_BANK_I_BITPOS 8 +#define QAT_FW_COMP_BANK_H_BITPOS 7 +#define QAT_FW_COMP_BANK_G_BITPOS 6 +#define QAT_FW_COMP_BANK_F_BITPOS 5 +#define QAT_FW_COMP_BANK_E_BITPOS 4 +#define QAT_FW_COMP_BANK_D_BITPOS 3 +#define QAT_FW_COMP_BANK_C_BITPOS 2 +#define QAT_FW_COMP_BANK_B_BITPOS 1 +#define QAT_FW_COMP_BANK_A_BITPOS 0 + +/** + ***************************************************************************** + * @ingroup icp_qat_fw_comp + * Definition of the ram bank enabled values + * @description + * Enumeration used to define whether a ram bank is enabled or not + * + *****************************************************************************/ +enum icp_qat_fw_comp_bank_enabled { + ICP_QAT_FW_COMP_BANK_DISABLED = 0, /*!< BANK DISABLED */ + ICP_QAT_FW_COMP_BANK_ENABLED = 1, /*!< BANK ENABLED */ + ICP_QAT_FW_COMP_BANK_DELIMITER = 2 /**< Delimiter type */ +}; + +/** + ****************************************************************************** + * @ingroup icp_qat_fw_comp + * + * @description + * Build the ram bank flags in the compression content descriptor + * which specify which banks are used to save history + * + * @param bank_i_enable + * @param bank_h_enable + * @param bank_g_enable + * @param bank_f_enable + * @param bank_e_enable + * @param bank_d_enable + * @param bank_c_enable + * @param bank_b_enable + * @param bank_a_enable + *****************************************************************************/ +#define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, \ + bank_h_enable, \ + bank_g_enable, \ + bank_f_enable, \ + bank_e_enable, \ + bank_d_enable, \ + bank_c_enable, \ + bank_b_enable, \ + bank_a_enable) \ + ((((bank_i_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_I_BITPOS) | \ + (((bank_h_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_H_BITPOS) | \ + (((bank_g_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_G_BITPOS) | \ + (((bank_f_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_F_BITPOS) | \ + (((bank_e_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_E_BITPOS) | \ + (((bank_d_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_D_BITPOS) | \ + (((bank_c_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_C_BITPOS) | \ + (((bank_b_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_B_BITPOS) | \ + (((bank_a_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ + << QAT_FW_COMP_BANK_A_BITPOS)) + #endif