From patchwork Fri Sep 6 12:43:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Kumar Kokkilagadda X-Patchwork-Id: 58860 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 21CA61F329; Fri, 6 Sep 2019 14:43:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 800401F327 for ; Fri, 6 Sep 2019 14:43:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x86CdviV015926; Fri, 6 Sep 2019 05:43:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=jT7S1bAHr0LlK/PzTg9tZhttLNVtJpG+EcolR2mA1xE=; b=M1OV3AiR5N+4otTjOqiwsvYGDBw/BxyGzTd6Zphc+SOlowY1Y6gHwnL+/nH9tk53MyFu +XvLIZGfTHTBI/PcN2THS3LShXpPqsU3SnMdjtdqbIvFnohbhwrZkrYhpRSYgIwzzhON HSkC6SWEBqMkFhX9l86hmU85DzK4d5J0dOlj09oILowpurc/ZtPOrkhra5IorpP7cXH1 WSbjuSpaL2leGw7ScCEdwZFbhuYnYeNZUCxtTorpKv2Db10NjbktDKdTssaoRF/VYsNY kBl/ce49s7lVbw+YSlncP5YYXL+Yh8isxLM+65xzGSvH1yLkswuxQeilMmkpx2KYm204 Bg== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2uqp8prcf8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2019 05:43:11 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 6 Sep 2019 05:43:09 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 6 Sep 2019 05:43:09 -0700 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 6A2A23F703F; Fri, 6 Sep 2019 05:43:07 -0700 (PDT) From: To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K , "John McNamara" , Marko Kovacevic CC: Date: Fri, 6 Sep 2019 18:13:02 +0530 Message-ID: <20190906124302.14534-1-kirankumark@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190906054050.13214-1-kirankumark@marvell.com> References: <20190906054050.13214-1-kirankumark@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-09-06_06:2019-09-04,2019-09-06 signatures=0 Subject: [dpdk-dev] [PATCH v3] net/octeontx2: add tx desc status dev ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar K Adding support for tx descriptor status dev ops for octeontx2. Signed-off-by: Kiran Kumar K Acked-by: Jerin Jacob --- V3 Changes: * Added version info in subject V2 Changes: * Fixed check for num of tx desc doc/guides/nics/features/octeontx2.ini | 1 + drivers/net/octeontx2/otx2_ethdev.c | 1 + drivers/net/octeontx2/otx2_ethdev.h | 1 + drivers/net/octeontx2/otx2_ethdev_ops.c | 38 ++++++++++++++++++++++++- 4 files changed, 40 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini index 66952328b..b89959994 100644 --- a/doc/guides/nics/features/octeontx2.ini +++ b/doc/guides/nics/features/octeontx2.ini @@ -39,6 +39,7 @@ Packet type parsing = Y Timesync = Y Timestamp offload = Y Rx descriptor status = Y +Tx descriptor status = Y Basic stats = Y Stats per queue = Y Extended stats = Y diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index b84128fef..696c85cb8 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -1646,6 +1646,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = { .rx_queue_count = otx2_nix_rx_queue_count, .rx_descriptor_done = otx2_nix_rx_descriptor_done, .rx_descriptor_status = otx2_nix_rx_descriptor_status, + .tx_descriptor_status = otx2_nix_tx_descriptor_status, .tx_done_cleanup = otx2_nix_tx_done_cleanup, .pool_ops_supported = otx2_nix_pool_ops_supported, .filter_ctrl = otx2_nix_dev_filter_ctrl, diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index 7b15d6bc8..1c660cb1e 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -377,6 +377,7 @@ uint32_t otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t qidx); int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt); int otx2_nix_rx_descriptor_done(void *rxq, uint16_t offset); int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset); +int otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset); void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en); void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev); diff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c index 7c6532b6f..ab07e4bc0 100644 --- a/drivers/net/octeontx2/otx2_ethdev_ops.c +++ b/drivers/net/octeontx2/otx2_ethdev_ops.c @@ -274,7 +274,7 @@ otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset) struct otx2_eth_rxq *rxq = rx_queue; uint32_t head, tail; - if (rxq->qlen >= offset) + if (rxq->qlen <= offset) return -EINVAL; nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev), @@ -286,6 +286,42 @@ otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset) return RTE_ETH_RX_DESC_AVAIL; } +static void +nix_tx_head_tail_get(struct otx2_eth_dev *dev, + uint32_t *head, uint32_t *tail, uint16_t queue_idx) +{ + uint64_t reg, val; + + if (head == NULL || tail == NULL) + return; + + reg = (((uint64_t)queue_idx) << 32); + val = otx2_atomic64_add_nosync(reg, (int64_t *) + (dev->base + NIX_LF_SQ_OP_STATUS)); + if (val & OP_ERR) + val = 0; + + *tail = (uint32_t)((val >> 28) & 0x3F); + *head = (uint32_t)((val >> 20) & 0x3F); +} + +int +otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + struct otx2_eth_txq *txq = tx_queue; + uint32_t head, tail; + + if (txq->qconf.nb_desc <= offset) + return -EINVAL; + + nix_tx_head_tail_get(txq->dev, &head, &tail, txq->sq); + + if (nix_offset_has_packet(head, tail, offset)) + return RTE_ETH_TX_DESC_DONE; + else + return RTE_ETH_TX_DESC_FULL; +} + /* It is a NOP for octeontx2 as HW frees the buffer on xmit */ int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)