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Mon, 26 Aug 2019 12:49:24 +0000 From: Nagadheeraj Rottela To: "akhil.goyal@nxp.com" , "pablo.de.lara.guarch@intel.com" , "mattias.ronnblom@ericsson.com" CC: "dev@dpdk.org" , Srikanth Jampala , Nagadheeraj Rottela Thread-Topic: [PATCH v4 02/11] crypto/nitrox: add PCI probe and remove routines Thread-Index: AQHVXAywz4Bivx8Ck0Cl4Gz9JvWaBA== Date: Mon, 26 Aug 2019 12:49:24 +0000 Message-ID: <20190826124836.21187-3-rnagadheeraj@marvell.com> References: <4b0fc70c-768a-a474-ace4-b69513412cae@ericsson.com> <20190826124836.21187-1-rnagadheeraj@marvell.com> In-Reply-To: <20190826124836.21187-1-rnagadheeraj@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::28) To MN2PR18MB2797.namprd18.prod.outlook.com (2603:10b6:208:a0::16) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.13.6 x-originating-ip: [115.113.156.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d40b1c84-5da2-4014-1437-08d72a23d2ba x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB3230; H:MN2PR18MB2797.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: sa0m5LehGu6ywO4n2KBnAM1/cMfQSlv++vPODzdoIQRVGyU6t2N+DEAmp3TN1BzsQMm2K0n5SRtguvc1mK/BUDWYO+qxBVt2jEAuIF9uWGOvk4kWQ1N5S8lyqHXXCWJV4w3AoqsQ8OTdxwL7lIYltnjTLGfyhuM5xirKHxeo2QlkL0p5+0xRx58FBhBi7Hc6IbVsMNk0dCOkbg8FcVJ1lIWXtKe4xX8gdDhHY8l4mRpPrfpLDJ2hp/ba4StQDuBtxGwmx/qFzznqhKXrvZElmiXrmxYchA3cUGQr9fU6oZ+E4aqE0fUH8PmoRRZDr5GOGhoxW9fs0F85Pf/FWRcKZVV5OAoBU9RDieCFXE/TKl3EvVasPkClNY58VjxnGX4P30ZbpedC4YK/k6+NV/vkWpNZ9CWGkz1av45QCmG8TiU= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: d40b1c84-5da2-4014-1437-08d72a23d2ba X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2019 12:49:24.7984 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: h5zEQWsGiWAS0hor55JNjx+WvBDtNH2FgtqagQaCHW60nSFa7PoBWzdUfmc5Yd5jR5QTW4PdB4hfWfab3n2kXh+qqmoXPsb63XhV6rV2Yvk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3230 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-26_07:2019-08-26,2019-08-26 signatures=0 Subject: [dpdk-dev] [PATCH v4 02/11] crypto/nitrox: add PCI probe and remove routines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add pci probe, remove and hardware init routines. Signed-off-by: Nagadheeraj Rottela --- drivers/crypto/nitrox/Makefile | 1 + drivers/crypto/nitrox/meson.build | 1 + drivers/crypto/nitrox/nitrox_csr.h | 28 +++++++++ drivers/crypto/nitrox/nitrox_device.c | 105 ++++++++++++++++++++++++++++++++++ drivers/crypto/nitrox/nitrox_device.h | 18 ++++++ drivers/crypto/nitrox/nitrox_hal.c | 86 ++++++++++++++++++++++++++++ drivers/crypto/nitrox/nitrox_hal.h | 37 ++++++++++++ 7 files changed, 276 insertions(+) create mode 100644 drivers/crypto/nitrox/nitrox_csr.h create mode 100644 drivers/crypto/nitrox/nitrox_device.h create mode 100644 drivers/crypto/nitrox/nitrox_hal.c create mode 100644 drivers/crypto/nitrox/nitrox_hal.h diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile index da33a1d2a..bc0220964 100644 --- a/drivers/crypto/nitrox/Makefile +++ b/drivers/crypto/nitrox/Makefile @@ -24,5 +24,6 @@ LDLIBS += -lrte_cryptodev # library source files SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build index 0afb14b00..f1c96b84d 100644 --- a/drivers/crypto/nitrox/meson.build +++ b/drivers/crypto/nitrox/meson.build @@ -10,4 +10,5 @@ deps += ['bus_pci'] allow_experimental_apis = true sources = files( 'nitrox_device.c', + 'nitrox_hal.c', ) diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h new file mode 100644 index 000000000..879104515 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_csr.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_CSR_H_ +#define _NITROX_CSR_H_ + +#include +#include + +#define CSR_DELAY 30 + +/* AQM Virtual Function Registers */ +#define AQMQ_QSZX(_i) (0x20008 + ((_i)*0x40000)) + +static inline uint64_t +nitrox_read_csr(uint8_t *bar_addr, uint64_t offset) +{ + return rte_read64(bar_addr + offset); +} + +static inline void +nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value) +{ + rte_write64(value, (bar_addr + offset)); +} + +#endif /* _NITROX_CSR_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_device.c b/drivers/crypto/nitrox/nitrox_device.c index d26535dee..5628c6d8b 100644 --- a/drivers/crypto/nitrox/nitrox_device.c +++ b/drivers/crypto/nitrox/nitrox_device.c @@ -1,3 +1,108 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(C) 2019 Marvell International Ltd. */ + +#include + +#include "nitrox_device.h" +#include "nitrox_hal.h" + +TAILQ_HEAD(ndev_list, nitrox_device); +static struct ndev_list ndev_list = TAILQ_HEAD_INITIALIZER(ndev_list); + +static struct nitrox_device * +ndev_allocate(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + ndev = rte_zmalloc_socket("nitrox device", sizeof(*ndev), + RTE_CACHE_LINE_SIZE, + pdev->device.numa_node); + if (!ndev) + return NULL; + + TAILQ_INSERT_TAIL(&ndev_list, ndev, next); + return ndev; +} + +static void +ndev_init(struct nitrox_device *ndev, struct rte_pci_device *pdev) +{ + enum nitrox_vf_mode vf_mode; + + ndev->pdev = pdev; + ndev->bar_addr = pdev->mem_resource[0].addr; + vf_mode = vf_get_vf_config_mode(ndev->bar_addr); + ndev->nr_queues = vf_config_mode_to_nr_queues(vf_mode); +} + +static struct nitrox_device * +find_ndev(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + TAILQ_FOREACH(ndev, &ndev_list, next) + if (ndev->pdev == pdev) + return ndev; + + return NULL; +} + +static void +ndev_release(struct nitrox_device *ndev) +{ + if (!ndev) + return; + + TAILQ_REMOVE(&ndev_list, ndev, next); + rte_free(ndev); +} + +static int +nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + /* Nitrox CSR space */ + if (!pdev->mem_resource[0].addr) + return -EINVAL; + + ndev = ndev_allocate(pdev); + if (!ndev) + return -ENOMEM; + + ndev_init(ndev, pdev); + return 0; +} + +static int +nitrox_pci_remove(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + ndev = find_ndev(pdev); + if (!ndev) + return -ENODEV; + + ndev_release(ndev); + return 0; +} + +static struct rte_pci_id pci_id_nitrox_map[] = { + { + /* Nitrox 5 VF */ + RTE_PCI_DEVICE(0x177d, 0x13) + }, + {.device_id = 0}, +}; + +static struct rte_pci_driver nitrox_pmd = { + .id_table = pci_id_nitrox_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = nitrox_pci_probe, + .remove = nitrox_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(nitrox, nitrox_pmd); +RTE_PMD_REGISTER_PCI_TABLE(nitrox, pci_id_nitrox_map); diff --git a/drivers/crypto/nitrox/nitrox_device.h b/drivers/crypto/nitrox/nitrox_device.h new file mode 100644 index 000000000..0d0167de2 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_device.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_DEVICE_H_ +#define _NITROX_DEVICE_H_ + +#include +#include + +struct nitrox_device { + TAILQ_ENTRY(nitrox_device) next; + struct rte_pci_device *pdev; + uint8_t *bar_addr; + uint16_t nr_queues; +}; + +#endif /* _NITROX_DEVICE_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_hal.c b/drivers/crypto/nitrox/nitrox_hal.c new file mode 100644 index 000000000..3dee59215 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_hal.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include +#include +#include +#include + +#include "nitrox_hal.h" +#include "nitrox_csr.h" + +#define MAX_VF_QUEUES 8 +#define MAX_PF_QUEUES 64 + +int +vf_get_vf_config_mode(uint8_t *bar_addr) +{ + union aqmq_qsz aqmq_qsz; + uint64_t reg_addr; + int q, vf_mode; + + aqmq_qsz.u64 = 0; + aqmq_qsz.s.host_queue_size = 0xDEADBEEF; + + reg_addr = AQMQ_QSZX(0); + nitrox_write_csr(bar_addr, reg_addr, aqmq_qsz.u64); + rte_delay_us_block(CSR_DELAY); + + aqmq_qsz.u64 = 0; + for (q = 1; q < MAX_VF_QUEUES; q++) { + reg_addr = AQMQ_QSZX(q); + aqmq_qsz.u64 = nitrox_read_csr(bar_addr, reg_addr); + if (aqmq_qsz.s.host_queue_size == 0xDEADBEEF) + break; + } + + switch (q) { + case 1: + vf_mode = NITROX_MODE_VF128; + break; + case 2: + vf_mode = NITROX_MODE_VF64; + break; + case 4: + vf_mode = NITROX_MODE_VF32; + break; + case 8: + vf_mode = NITROX_MODE_VF16; + break; + default: + vf_mode = 0; + break; + } + + return vf_mode; +} + +int +vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode) +{ + int nr_queues; + + switch (vf_mode) { + case NITROX_MODE_PF: + nr_queues = MAX_PF_QUEUES; + break; + case NITROX_MODE_VF16: + nr_queues = 8; + break; + case NITROX_MODE_VF32: + nr_queues = 4; + break; + case NITROX_MODE_VF64: + nr_queues = 2; + break; + case NITROX_MODE_VF128: + nr_queues = 1; + break; + default: + nr_queues = 0; + break; + } + + return nr_queues; +} diff --git a/drivers/crypto/nitrox/nitrox_hal.h b/drivers/crypto/nitrox/nitrox_hal.h new file mode 100644 index 000000000..6184211a5 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_hal.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_HAL_H_ +#define _NITROX_HAL_H_ + +#include +#include + +#include "nitrox_csr.h" + +union aqmq_qsz { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t raz : 32; + uint64_t host_queue_size : 32; +#else + uint64_t host_queue_size : 32; + uint64_t raz : 32; +#endif + } s; +}; + +enum nitrox_vf_mode { + NITROX_MODE_PF = 0x0, + NITROX_MODE_VF16 = 0x1, + NITROX_MODE_VF32 = 0x2, + NITROX_MODE_VF64 = 0x3, + NITROX_MODE_VF128 = 0x4, +}; + +int vf_get_vf_config_mode(uint8_t *bar_addr); +int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode); + +#endif /* _NITROX_HAL_H_ */