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Fri, 23 Aug 2019 10:42:15 +0000 From: Nagadheeraj Rottela To: "akhil.goyal@nxp.com" , "pablo.de.lara.guarch@intel.com" CC: "dev@dpdk.org" , Srikanth Jampala , Nagadheeraj Rottela Thread-Topic: [PATCH v3 05/11] crypto/nitrox: add software queue management functionality Thread-Index: AQHVWZ9tRbuSCd+GIE2zh3OU5tfXtA== Date: Fri, 23 Aug 2019 10:42:15 +0000 Message-ID: <20190823104144.19300-6-rnagadheeraj@marvell.com> References: <20190717052837.647-1-rnagadheeraj@marvell.com> <20190823104144.19300-1-rnagadheeraj@marvell.com> In-Reply-To: <20190823104144.19300-1-rnagadheeraj@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR01CA0110.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::26) To MN2PR18MB2797.namprd18.prod.outlook.com (2603:10b6:208:a0::16) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.13.6 x-originating-ip: [115.113.156.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0300c292-7322-46ea-b6ad-08d727b69037 x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB2830; H:MN2PR18MB2797.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kprVm0NPa6lBwg1NSwYOp+2vc8XssPblUySPOwNtvWHX+karurHAeFxoHeDcSHiKF6+NP7IrB4X8aBcy9JucuJ7vnXNsWorqfGxPgOH8jIsd3H0v1fsJztS0YxkEKzvP++4KJ8GozGvyHJtk7DGpT0cz7oAnudzxSE89TMoGb0x86nbIlx58nMGqsEpWWkZosGqPZcuCXL4sWaWcqmKL1iU154MU7hAVk8YPoSuRToVvXBUSOFPlC75ghu1Hl4Ori8PgX1zJxti1CgcbxaaKxd76UErQWejJndpw1KrJ8QGU/SVBK2BPdD9ylkOlFHUfS87oDFzFLuu4lRQr9jNyKRAf/uV+JFbJeKxfspy6CVqB5x4EFpVGQHsiApuulCfUm0UcbXPnSvr4Mp4lPhvqdY/w9eBkkh0AMtaf1l09S/k= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 0300c292-7322-46ea-b6ad-08d727b69037 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Aug 2019 10:42:15.4965 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2T97/ki+4/n3ETaEN1ktn/B+hqiEL2xSdfp1BWV+Pftcnt99TyVol5cZMEGG46C6Gw+8tfrLznP2P7JWY2VTAnBHvb0lUaD4V5MXt8iW6jY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2830 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-23_04:2019-08-21,2019-08-23 signatures=0 Subject: [dpdk-dev] [PATCH v3 05/11] crypto/nitrox: add software queue management functionality X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add software queue management code corresponding to queue pair setup and release functions. Signed-off-by: Nagadheeraj Rottela --- drivers/crypto/nitrox/Makefile | 2 + drivers/crypto/nitrox/meson.build | 2 + drivers/crypto/nitrox/nitrox_qp.c | 74 +++++++++++++++++ drivers/crypto/nitrox/nitrox_qp.h | 40 +++++++++ drivers/crypto/nitrox/nitrox_sym.c | 132 ++++++++++++++++++++++++++++-- drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 56 +++++++++++++ drivers/crypto/nitrox/nitrox_sym_reqmgr.h | 13 +++ 7 files changed, 312 insertions(+), 7 deletions(-) create mode 100644 drivers/crypto/nitrox/nitrox_qp.c create mode 100644 drivers/crypto/nitrox/nitrox_qp.h create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.c create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.h diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile index dedb74a34..f56992770 100644 --- a/drivers/crypto/nitrox/Makefile +++ b/drivers/crypto/nitrox/Makefile @@ -28,5 +28,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_capabilities.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_reqmgr.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_qp.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build index 7c565c5a4..03788366b 100644 --- a/drivers/crypto/nitrox/meson.build +++ b/drivers/crypto/nitrox/meson.build @@ -14,4 +14,6 @@ sources = files( 'nitrox_logs.c', 'nitrox_sym.c', 'nitrox_sym_capabilities.c', + 'nitrox_sym_reqmgr.c', + 'nitrox_qp.c' ) diff --git a/drivers/crypto/nitrox/nitrox_qp.c b/drivers/crypto/nitrox/nitrox_qp.c new file mode 100644 index 000000000..9673bb4f3 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_qp.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include +#include + +#include "nitrox_qp.h" +#include "nitrox_hal.h" +#include "nitrox_logs.h" + +#define MAX_CMD_QLEN 16384 + +static int +nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id) +{ + size_t ridq_size = qp->count * sizeof(*qp->ridq); + + qp->ridq = rte_zmalloc_socket("nitrox ridq", ridq_size, + RTE_CACHE_LINE_SIZE, + socket_id); + if (!qp->ridq) { + NITROX_LOG(ERR, "Failed to create rid queue\n"); + return -ENOMEM; + } + + return 0; +} + +int +nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name, + uint32_t nb_descriptors, uint8_t instr_size, int socket_id) +{ + int err; + uint32_t count; + + RTE_SET_USED(bar_addr); + RTE_SET_USED(instr_size); + count = rte_align32pow2(nb_descriptors); + if (count > MAX_CMD_QLEN) { + NITROX_LOG(ERR, "%s: Number of descriptors too big %d," + " greater than max queue length %d\n", + dev_name, count, + MAX_CMD_QLEN); + return -EINVAL; + } + + qp->count = count; + qp->head = qp->tail = 0; + rte_atomic16_init(&qp->pending_count); + err = nitrox_setup_ridq(qp, socket_id); + if (err) + goto ridq_err; + + return 0; + +ridq_err: + return err; + +} + +static void +nitrox_release_ridq(struct nitrox_qp *qp) +{ + rte_free(qp->ridq); +} + +int +nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr) +{ + RTE_SET_USED(bar_addr); + nitrox_release_ridq(qp); + return 0; +} diff --git a/drivers/crypto/nitrox/nitrox_qp.h b/drivers/crypto/nitrox/nitrox_qp.h new file mode 100644 index 000000000..cf0102ff9 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_qp.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_QP_H_ +#define _NITROX_QP_H_ + +#include + +#include + +struct nitrox_softreq; + +struct rid { + struct nitrox_softreq *sr; +}; + +struct nitrox_qp { + struct rid *ridq; + uint32_t count; + uint32_t head; + uint32_t tail; + struct rte_mempool *sr_mp; + struct rte_cryptodev_stats stats; + uint16_t qno; + rte_atomic16_t pending_count; +}; + +static inline bool +nitrox_qp_is_empty(struct nitrox_qp *qp) +{ + return (rte_atomic16_read(&qp->pending_count) == 0); +} + +int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, + const char *dev_name, uint32_t nb_descriptors, + uint8_t inst_size, int socket_id); +int nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr); + +#endif /* _NITROX_QP_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/nitrox_sym.c index c05042e54..05f089cae 100644 --- a/drivers/crypto/nitrox/nitrox_sym.c +++ b/drivers/crypto/nitrox/nitrox_sym.c @@ -10,9 +10,12 @@ #include "nitrox_sym.h" #include "nitrox_device.h" #include "nitrox_sym_capabilities.h" +#include "nitrox_qp.h" +#include "nitrox_sym_reqmgr.h" #include "nitrox_logs.h" #define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox +#define NPS_PKT_IN_INSTR_SIZE 64 struct nitrox_sym_device { struct rte_cryptodev *cdev; @@ -78,12 +81,127 @@ nitrox_sym_dev_info_get(struct rte_cryptodev *cdev, info->sym.max_nb_sessions = 0; } +static void +nitrox_sym_dev_stats_get(struct rte_cryptodev *cdev, + struct rte_cryptodev_stats *stats) +{ + int qp_id; + + for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) { + struct nitrox_qp *qp = cdev->data->queue_pairs[qp_id]; + + if (!qp) + continue; + + stats->enqueued_count += qp->stats.enqueued_count; + stats->dequeued_count += qp->stats.dequeued_count; + stats->enqueue_err_count += qp->stats.enqueue_err_count; + stats->dequeue_err_count += qp->stats.dequeue_err_count; + } +} + +static void +nitrox_sym_dev_stats_reset(struct rte_cryptodev *cdev) +{ + int qp_id; + + for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) { + struct nitrox_qp *qp = cdev->data->queue_pairs[qp_id]; + + if (!qp) + continue; + + memset(&qp->stats, 0, sizeof(qp->stats)); + } +} + static int -nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id) +nitrox_sym_dev_qp_setup(struct rte_cryptodev *cdev, uint16_t qp_id, + const struct rte_cryptodev_qp_conf *qp_conf, + int socket_id) { - RTE_SET_USED(cdev); - RTE_SET_USED(qp_id); + struct nitrox_sym_device *sym_dev = cdev->data->dev_private; + struct nitrox_device *ndev = sym_dev->ndev; + struct nitrox_qp *qp = NULL; + int err; + + NITROX_LOG(DEBUG, "queue %d\n", qp_id); + if (qp_id >= ndev->nr_queues) { + NITROX_LOG(ERR, "queue %u invalid, max queues supported %d\n", + qp_id, ndev->nr_queues); + return -EINVAL; + } + + if (cdev->data->queue_pairs[qp_id]) { + err = nitrox_sym_dev_qp_release(cdev, qp_id); + if (err) + return err; + } + + qp = rte_zmalloc_socket("nitrox PMD qp", sizeof(*qp), + RTE_CACHE_LINE_SIZE, + socket_id); + if (!qp) { + NITROX_LOG(ERR, "Failed to allocate nitrox qp\n"); + return -ENOMEM; + } + + qp->qno = qp_id; + err = nitrox_qp_setup(qp, ndev->bar_addr, cdev->data->name, + qp_conf->nb_descriptors, NPS_PKT_IN_INSTR_SIZE, + socket_id); + if (unlikely(err)) + goto qp_setup_err; + + qp->sr_mp = nitrox_sym_req_pool_create(cdev, qp->count, qp_id, + socket_id); + if (unlikely(!qp->sr_mp)) + goto req_pool_err; + + cdev->data->queue_pairs[qp_id] = qp; + NITROX_LOG(DEBUG, "queue %d setup done\n", qp_id); return 0; + +req_pool_err: + nitrox_qp_release(qp, ndev->bar_addr); +qp_setup_err: + rte_free(qp); + return err; +} + +static int +nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id) +{ + struct nitrox_sym_device *sym_dev = cdev->data->dev_private; + struct nitrox_device *ndev = sym_dev->ndev; + struct nitrox_qp *qp; + int err; + + NITROX_LOG(DEBUG, "queue %d\n", qp_id); + if (qp_id >= ndev->nr_queues) { + NITROX_LOG(ERR, "queue %u invalid, max queues supported %d\n", + qp_id, ndev->nr_queues); + return -EINVAL; + } + + qp = cdev->data->queue_pairs[qp_id]; + if (!qp) { + NITROX_LOG(DEBUG, "queue %u already freed\n", qp_id); + return 0; + } + + if (!nitrox_qp_is_empty(qp)) { + NITROX_LOG(ERR, "queue %d not empty\n", qp_id); + return -EAGAIN; + } + + cdev->data->queue_pairs[qp_id] = NULL; + err = nitrox_qp_release(qp, ndev->bar_addr); + nitrox_sym_req_pool_free(qp->sr_mp); + rte_free(qp); + NITROX_LOG(DEBUG, "queue %d release done\n", qp_id); + + return err; } static struct rte_cryptodev_ops nitrox_cryptodev_ops = { @@ -93,11 +211,11 @@ static struct rte_cryptodev_ops nitrox_cryptodev_ops = { .dev_close = nitrox_sym_dev_close, .dev_infos_get = nitrox_sym_dev_info_get, - .stats_get = NULL, - .stats_reset = NULL, + .stats_get = nitrox_sym_dev_stats_get, + .stats_reset = nitrox_sym_dev_stats_reset, - .queue_pair_setup = NULL, - .queue_pair_release = NULL, + .queue_pair_setup = nitrox_sym_dev_qp_setup, + .queue_pair_release = nitrox_sym_dev_qp_release, .sym_session_get_size = NULL, .sym_session_configure = NULL, diff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c new file mode 100644 index 000000000..42d67317c --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include +#include +#include + +#include "nitrox_sym_reqmgr.h" +#include "nitrox_logs.h" + +struct nitrox_softreq { + rte_iova_t iova; +}; + +static void +softreq_init(struct nitrox_softreq *sr, rte_iova_t iova) +{ + memset(sr, 0, sizeof(*sr)); + sr->iova = iova; +} + +static void +req_pool_obj_init(__rte_unused struct rte_mempool *mp, + __rte_unused void *opaque, void *obj, + __rte_unused unsigned int obj_idx) +{ + softreq_init(obj, rte_mempool_virt2iova(obj)); +} + +struct rte_mempool * +nitrox_sym_req_pool_create(struct rte_cryptodev *cdev, uint32_t nobjs, + uint16_t qp_id, int socket_id) +{ + char softreq_pool_name[RTE_RING_NAMESIZE]; + struct rte_mempool *mp; + + snprintf(softreq_pool_name, RTE_RING_NAMESIZE, "%s_sr_%d", + cdev->data->name, qp_id); + mp = rte_mempool_create(softreq_pool_name, + RTE_ALIGN_MUL_CEIL(nobjs, 64), + sizeof(struct nitrox_softreq), + 64, 0, NULL, NULL, req_pool_obj_init, NULL, + socket_id, 0); + if (unlikely(!mp)) + NITROX_LOG(ERR, "Failed to create req pool, qid %d, err %d\n", + qp_id, rte_errno); + + return mp; +} + +void +nitrox_sym_req_pool_free(struct rte_mempool *mp) +{ + rte_mempool_free(mp); +} diff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h new file mode 100644 index 000000000..5953c958c --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_SYM_REQMGR_H_ +#define _NITROX_SYM_REQMGR_H_ + +struct rte_mempool *nitrox_sym_req_pool_create(struct rte_cryptodev *cdev, + uint32_t nobjs, uint16_t qp_id, + int socket_id); +void nitrox_sym_req_pool_free(struct rte_mempool *mp); + +#endif /* _NITROX_SYM_REQMGR_H_ */