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Fri, 23 Aug 2019 10:42:13 +0000 From: Nagadheeraj Rottela To: "akhil.goyal@nxp.com" , "pablo.de.lara.guarch@intel.com" CC: "dev@dpdk.org" , Srikanth Jampala , Nagadheeraj Rottela Thread-Topic: [PATCH v3 04/11] crypto/nitrox: add basic symmetric cryptodev operations Thread-Index: AQHVWZ9srxmZVywFXECb3NIyM1zjuQ== Date: Fri, 23 Aug 2019 10:42:13 +0000 Message-ID: <20190823104144.19300-5-rnagadheeraj@marvell.com> References: <20190717052837.647-1-rnagadheeraj@marvell.com> <20190823104144.19300-1-rnagadheeraj@marvell.com> In-Reply-To: <20190823104144.19300-1-rnagadheeraj@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR01CA0110.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::26) To MN2PR18MB2797.namprd18.prod.outlook.com (2603:10b6:208:a0::16) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.13.6 x-originating-ip: [115.113.156.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 405ce330-4222-43ca-520f-08d727b68f10 x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB2830; H:MN2PR18MB2797.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Z7l+n9a3w/pJQVxVqSu0xGmFXhGvo3nPa8V5rs37hh/XA5MQcJUKhllUdlBH1B7vpu/WA2J3Q0EUYggoEvv/xbijkqxSmaDmx/BD0tyv1Ej9zpNZ1T9dIHU5vGoBN++OCoAThoqkyNT+07OcbQu3t4F+l2YG6bir8HJVYBujimKkOirpV5oKf1IxrFU6oaHHm29SfS6mxQ2L7a82hewfdeSbgesm5x6ypRgSdhPiS+Di7btNuiL2IT6Mfy2BBCLOYJN7Qkdzm7ik2M+G5adlT/jVWrtpZAQqQrGfiRy6PlVwzAVXSqOmsTU1AQETt81bFnPGsKETGuvzWqK4kguu+hUe0AuP+i0Y87wFhz8sU6no+kJsYRxtMwVGsw09wXJwRZL8TVeYGDVpHoJZLKgseoe1k8R1qe74G0Wr7AuYciU= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 405ce330-4222-43ca-520f-08d727b68f10 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Aug 2019 10:42:13.5506 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hS6xRISMXCanOqlltFwGYP6531KnlGGGsTZBPzL2UcprndXrZAKBvogx8szMrQsjijx6QMbiobVR3R0Br+6XgY/TjS8O+PNJBaGSD0i/gPU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2830 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-23_04:2019-08-21,2019-08-23 signatures=0 Subject: [dpdk-dev] [PATCH v3 04/11] crypto/nitrox: add basic symmetric cryptodev operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add the following cryptodev operations, - dev_configure - dev_start - dev_stop - dev_close - dev_infos_get Signed-off-by: Nagadheeraj Rottela --- doc/guides/cryptodevs/features/nitrox.ini | 38 ++++++++++++ doc/guides/cryptodevs/nitrox.rst | 37 +++++++++++ drivers/crypto/nitrox/Makefile | 1 + drivers/crypto/nitrox/meson.build | 1 + drivers/crypto/nitrox/nitrox_sym.c | 81 ++++++++++++++++++++++++- drivers/crypto/nitrox/nitrox_sym_capabilities.c | 57 +++++++++++++++++ drivers/crypto/nitrox/nitrox_sym_capabilities.h | 12 ++++ 7 files changed, 226 insertions(+), 1 deletion(-) create mode 100644 doc/guides/cryptodevs/features/nitrox.ini create mode 100644 drivers/crypto/nitrox/nitrox_sym_capabilities.c create mode 100644 drivers/crypto/nitrox/nitrox_sym_capabilities.h diff --git a/doc/guides/cryptodevs/features/nitrox.ini b/doc/guides/cryptodevs/features/nitrox.ini new file mode 100644 index 000000000..9f9e2619c --- /dev/null +++ b/doc/guides/cryptodevs/features/nitrox.ini @@ -0,0 +1,38 @@ +; +; Supported features of the 'nitrox' crypto driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Symmetric crypto = Y +Sym operation chaining = Y +HW Accelerated = Y +In Place SGL = Y +OOP SGL In SGL Out = Y +OOP SGL In LB Out = Y +OOP LB In SGL Out = Y +OOP LB In LB Out = Y + +; +; Supported crypto algorithms of the 'nitrox' crypto driver. +; +[Cipher] +AES CBC (128) = Y +AES CBC (192) = Y +AES CBC (256) = Y + +; +; Supported authentication algorithms of the 'nitrox' crypto driver. +; +[Auth] +SHA1 HMAC = Y + +; +; Supported AEAD algorithms of the 'nitrox' crypto driver. +; +[AEAD] + +; +; Supported Asymmetric algorithms of the 'nitrox' crypto driver. +; +[Asymmetric] diff --git a/doc/guides/cryptodevs/nitrox.rst b/doc/guides/cryptodevs/nitrox.rst index b6b86dda5..c16a5e393 100644 --- a/doc/guides/cryptodevs/nitrox.rst +++ b/doc/guides/cryptodevs/nitrox.rst @@ -9,3 +9,40 @@ cryptographic operations to the NITROX V security processor. Detailed information about the NITROX V security processor can be obtained here: * https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/ + +Features +-------- + +Nitrox crypto PMD has support for: + +Cipher algorithms: + +* ``RTE_CRYPTO_CIPHER_AES_CBC`` + +Hash algorithms: + +* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` + +Limitations +----------- + +* AES_CBC Cipher Only combination is not supported. + +Installation +------------ + +For compiling the Nitrox crypto PMD, please check if the +CONFIG_RTE_LIBRTE_PMD_NITROX setting is set to `y` in config/common_base file. + +* ``CONFIG_RTE_LIBRTE_PMD_NITROX=y`` + +Initialization +-------------- + +Nitrox crypto PMD depend on Nitrox kernel PF driver being installed on the +platform. Nitrox PF driver is required to create VF devices which will +be used by the PMD. Each VF device can enable one cryptodev PMD. + +Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SDK +and it's installation instructions can be obtained from: +`Marvell Technical Documentation Portal `_. diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile index 06c96ccd7..dedb74a34 100644 --- a/drivers/crypto/nitrox/Makefile +++ b/drivers/crypto/nitrox/Makefile @@ -27,5 +27,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_capabilities.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build index 1277cf58e..7c565c5a4 100644 --- a/drivers/crypto/nitrox/meson.build +++ b/drivers/crypto/nitrox/meson.build @@ -13,4 +13,5 @@ sources = files( 'nitrox_hal.c', 'nitrox_logs.c', 'nitrox_sym.c', + 'nitrox_sym_capabilities.c', ) diff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/nitrox_sym.c index c72016dd0..c05042e54 100644 --- a/drivers/crypto/nitrox/nitrox_sym.c +++ b/drivers/crypto/nitrox/nitrox_sym.c @@ -9,6 +9,7 @@ #include "nitrox_sym.h" #include "nitrox_device.h" +#include "nitrox_sym_capabilities.h" #include "nitrox_logs.h" #define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox @@ -25,6 +26,84 @@ static const struct rte_driver nitrox_rte_sym_drv = { .alias = nitrox_sym_drv_name }; +static int nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, + uint16_t qp_id); + +static int +nitrox_sym_dev_config(__rte_unused struct rte_cryptodev *cdev, + __rte_unused struct rte_cryptodev_config *config) +{ + return 0; +} + +static int +nitrox_sym_dev_start(__rte_unused struct rte_cryptodev *cdev) +{ + return 0; +} + +static void +nitrox_sym_dev_stop(__rte_unused struct rte_cryptodev *cdev) +{ +} + +static int +nitrox_sym_dev_close(struct rte_cryptodev *cdev) +{ + int i, ret; + + for (i = 0; i < cdev->data->nb_queue_pairs; i++) { + ret = nitrox_sym_dev_qp_release(cdev, i); + if (ret) + return ret; + } + + return 0; +} + +static void +nitrox_sym_dev_info_get(struct rte_cryptodev *cdev, + struct rte_cryptodev_info *info) +{ + struct nitrox_sym_device *sym_dev = cdev->data->dev_private; + struct nitrox_device *ndev = sym_dev->ndev; + + if (!info) + return; + + info->max_nb_queue_pairs = ndev->nr_queues; + info->feature_flags = cdev->feature_flags; + info->capabilities = nitrox_get_sym_capabilities(); + info->driver_id = nitrox_sym_drv_id; + info->sym.max_nb_sessions = 0; +} + +static int +nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id) +{ + RTE_SET_USED(cdev); + RTE_SET_USED(qp_id); + return 0; +} + +static struct rte_cryptodev_ops nitrox_cryptodev_ops = { + .dev_configure = nitrox_sym_dev_config, + .dev_start = nitrox_sym_dev_start, + .dev_stop = nitrox_sym_dev_stop, + .dev_close = nitrox_sym_dev_close, + .dev_infos_get = nitrox_sym_dev_info_get, + + .stats_get = NULL, + .stats_reset = NULL, + + .queue_pair_setup = NULL, + .queue_pair_release = NULL, + + .sym_session_get_size = NULL, + .sym_session_configure = NULL, + .sym_session_clear = NULL +}; + int nitrox_sym_pmd_create(struct nitrox_device *ndev) { @@ -50,7 +129,7 @@ nitrox_sym_pmd_create(struct nitrox_device *ndev) ndev->rte_sym_dev.name = cdev->data->name; cdev->driver_id = nitrox_sym_drv_id; - cdev->dev_ops = NULL; + cdev->dev_ops = &nitrox_cryptodev_ops; cdev->enqueue_burst = NULL; cdev->dequeue_burst = NULL; cdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | diff --git a/drivers/crypto/nitrox/nitrox_sym_capabilities.c b/drivers/crypto/nitrox/nitrox_sym_capabilities.c new file mode 100644 index 000000000..aa1ff2638 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_sym_capabilities.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include "nitrox_sym_capabilities.h" + +static const struct rte_cryptodev_capabilities nitrox_capabilities[] = { + { /* SHA1 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA1_HMAC, + .block_size = 64, + .key_size = { + .min = 1, + .max = 64, + .increment = 1 + }, + .digest_size = { + .min = 1, + .max = 20, + .increment = 1 + }, + .iv_size = { 0 } + }, } + }, } + }, + { /* AES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_CBC, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + + RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() +}; + +const struct rte_cryptodev_capabilities * +nitrox_get_sym_capabilities(void) +{ + return nitrox_capabilities; +} diff --git a/drivers/crypto/nitrox/nitrox_sym_capabilities.h b/drivers/crypto/nitrox/nitrox_sym_capabilities.h new file mode 100644 index 000000000..cb2d97572 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_sym_capabilities.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_SYM_CAPABILITIES_H_ +#define _NITROX_SYM_CAPABILITIES_H_ + +#include + +const struct rte_cryptodev_capabilities *nitrox_get_sym_capabilities(void); + +#endif /* _NITROX_SYM_CAPABILITIES_H_ */