diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index df66ba826..52fd8c897 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1019,9 +1019,6 @@ enum ice_status ice_check_reset(struct ice_hw *hw)
 	 * or EMPR has occurred. The grst delay value is in 100ms units.
 	 * Add 1sec for outstanding AQ commands that can take a long time.
 	 */
-#define GLGEN_RSTCTL		0x000B8180 /* Reset Source: POR */
-#define GLGEN_RSTCTL_GRSTDEL_S	0
-#define GLGEN_RSTCTL_GRSTDEL_M	MAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
 	grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
 		      GLGEN_RSTCTL_GRSTDEL_S) + 10;
 
diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h
index e63e41133..2b423baf8 100644
--- a/drivers/net/ice/base/ice_hw_autogen.h
+++ b/drivers/net/ice/base/ice_hw_autogen.h
@@ -154,7 +154,7 @@
 #define PF0_MBX_CPM_ARQH_PAGE			0x02D80390 /* Reset Source: CORER */
 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_S		0
 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_MBX_CPM_ARQLEN_PAGE			0x02D80290 /* Reset Source: CORER */
+#define PF0_MBX_CPM_ARQLEN_PAGE			0x02D80290 /* Reset Source: PFR */
 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_S	0
 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_M	MAKEMASK(0x3FF, 0)
 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_S	28
@@ -177,7 +177,7 @@
 #define PF0_MBX_CPM_ATQH_PAGE			0x02D80310 /* Reset Source: CORER */
 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_S		0
 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_MBX_CPM_ATQLEN_PAGE			0x02D80210 /* Reset Source: CORER */
+#define PF0_MBX_CPM_ATQLEN_PAGE			0x02D80210 /* Reset Source: PFR */
 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_S	0
 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_M	MAKEMASK(0x3FF, 0)
 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_S	28
@@ -202,7 +202,7 @@
 #define PF0_MBX_HLP_ARQH_PAGE			0x02D00390 /* Reset Source: CORER */
 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_S		0
 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_MBX_HLP_ARQLEN_PAGE			0x02D00290 /* Reset Source: CORER */
+#define PF0_MBX_HLP_ARQLEN_PAGE			0x02D00290 /* Reset Source: PFR */
 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_S	0
 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_M	MAKEMASK(0x3FF, 0)
 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_S	28
@@ -225,7 +225,7 @@
 #define PF0_MBX_HLP_ATQH_PAGE			0x02D00310 /* Reset Source: CORER */
 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_S		0
 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_MBX_HLP_ATQLEN_PAGE			0x02D00210 /* Reset Source: CORER */
+#define PF0_MBX_HLP_ATQLEN_PAGE			0x02D00210 /* Reset Source: PFR */
 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_S	0
 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_M	MAKEMASK(0x3FF, 0)
 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_S	28
@@ -250,7 +250,7 @@
 #define PF0_MBX_PSM_ARQH_PAGE			0x02D40390 /* Reset Source: CORER */
 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_S		0
 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_MBX_PSM_ARQLEN_PAGE			0x02D40290 /* Reset Source: CORER */
+#define PF0_MBX_PSM_ARQLEN_PAGE			0x02D40290 /* Reset Source: PFR */
 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_S	0
 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_M	MAKEMASK(0x3FF, 0)
 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_S	28
@@ -273,7 +273,7 @@
 #define PF0_MBX_PSM_ATQH_PAGE			0x02D40310 /* Reset Source: CORER */
 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_S		0
 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_MBX_PSM_ATQLEN_PAGE			0x02D40210 /* Reset Source: CORER */
+#define PF0_MBX_PSM_ATQLEN_PAGE			0x02D40210 /* Reset Source: PFR */
 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_S	0
 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_M	MAKEMASK(0x3FF, 0)
 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_S	28
@@ -298,7 +298,7 @@
 #define PF0_SB_CPM_ARQH_PAGE			0x02D803A0 /* Reset Source: CORER */
 #define PF0_SB_CPM_ARQH_PAGE_ARQH_S		0
 #define PF0_SB_CPM_ARQH_PAGE_ARQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_SB_CPM_ARQLEN_PAGE			0x02D802A0 /* Reset Source: CORER */
+#define PF0_SB_CPM_ARQLEN_PAGE			0x02D802A0 /* Reset Source: PFR */
 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_S		0
 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_S		28
@@ -321,7 +321,7 @@
 #define PF0_SB_CPM_ATQH_PAGE			0x02D80320 /* Reset Source: CORER */
 #define PF0_SB_CPM_ATQH_PAGE_ATQH_S		0
 #define PF0_SB_CPM_ATQH_PAGE_ATQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_SB_CPM_ATQLEN_PAGE			0x02D80220 /* Reset Source: CORER */
+#define PF0_SB_CPM_ATQLEN_PAGE			0x02D80220 /* Reset Source: PFR */
 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_S		0
 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_S		28
@@ -346,7 +346,7 @@
 #define PF0_SB_HLP_ARQH_PAGE			0x02D003A0 /* Reset Source: CORER */
 #define PF0_SB_HLP_ARQH_PAGE_ARQH_S		0
 #define PF0_SB_HLP_ARQH_PAGE_ARQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_SB_HLP_ARQLEN_PAGE			0x02D002A0 /* Reset Source: CORER */
+#define PF0_SB_HLP_ARQLEN_PAGE			0x02D002A0 /* Reset Source: PFR */
 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_S		0
 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_S		28
@@ -369,7 +369,7 @@
 #define PF0_SB_HLP_ATQH_PAGE			0x02D00320 /* Reset Source: CORER */
 #define PF0_SB_HLP_ATQH_PAGE_ATQH_S		0
 #define PF0_SB_HLP_ATQH_PAGE_ATQH_M		MAKEMASK(0x3FF, 0)
-#define PF0_SB_HLP_ATQLEN_PAGE			0x02D00220 /* Reset Source: CORER */
+#define PF0_SB_HLP_ATQLEN_PAGE			0x02D00220 /* Reset Source: PFR */
 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_S		0
 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_S		28
@@ -383,7 +383,7 @@
 #define PF0_SB_HLP_ATQT_PAGE			0x02D00420 /* Reset Source: CORER */
 #define PF0_SB_HLP_ATQT_PAGE_ATQT_S		0
 #define PF0_SB_HLP_ATQT_PAGE_ATQT_M		MAKEMASK(0x3FF, 0)
-#define PF0INT_DYN_CTL(_i)			(0x03000000 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: PFR */
+#define PF0INT_DYN_CTL(_i)			(0x03000000 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
 #define PF0INT_DYN_CTL_MAX_INDEX		2047
 #define PF0INT_DYN_CTL_INTENA_S			0
 #define PF0INT_DYN_CTL_INTENA_M			BIT(0)
@@ -403,15 +403,15 @@
 #define PF0INT_DYN_CTL_WB_ON_ITR_M		BIT(30)
 #define PF0INT_DYN_CTL_INTENA_MSK_S		31
 #define PF0INT_DYN_CTL_INTENA_MSK_M		BIT(31)
-#define PF0INT_ITR_0(_i)			(0x03000004 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: PFR */
+#define PF0INT_ITR_0(_i)			(0x03000004 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
 #define PF0INT_ITR_0_MAX_INDEX			2047
 #define PF0INT_ITR_0_INTERVAL_S			0
 #define PF0INT_ITR_0_INTERVAL_M			MAKEMASK(0xFFF, 0)
-#define PF0INT_ITR_1(_i)			(0x03000008 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: PFR */
+#define PF0INT_ITR_1(_i)			(0x03000008 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
 #define PF0INT_ITR_1_MAX_INDEX			2047
 #define PF0INT_ITR_1_INTERVAL_S			0
 #define PF0INT_ITR_1_INTERVAL_M			MAKEMASK(0xFFF, 0)
-#define PF0INT_ITR_2(_i)			(0x0300000C + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: PFR */
+#define PF0INT_ITR_2(_i)			(0x0300000C + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
 #define PF0INT_ITR_2_MAX_INDEX			2047
 #define PF0INT_ITR_2_INTERVAL_S			0
 #define PF0INT_ITR_2_INTERVAL_M			MAKEMASK(0xFFF, 0)
@@ -585,7 +585,7 @@
 #define QTX_COMM_DBELL_PAGE_MAX_INDEX		16383
 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_S	0
 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_M	MAKEMASK(0xFFFFFFFF, 0)
-#define QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ)		(0x02F00000 + ((_DBLQ) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
+#define QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ)		(0x02F00000 + ((_DBLQ) * 4096)) /* _i=0...255 */ /* Reset Source: CORER */
 #define QTX_COMM_DBLQ_DBELL_PAGE_MAX_INDEX	255
 #define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_S		0
 #define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_M		MAKEMASK(0x1FFF, 0)
@@ -603,7 +603,7 @@
 #define VSI_MBX_ARQH_MAX_INDEX			767
 #define VSI_MBX_ARQH_ARQH_S			0
 #define VSI_MBX_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VSI_MBX_ARQLEN(_VSI)			(0x0200001C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
+#define VSI_MBX_ARQLEN(_VSI)			(0x0200001C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */
 #define VSI_MBX_ARQLEN_MAX_INDEX		767
 #define VSI_MBX_ARQLEN_ARQLEN_S			0
 #define VSI_MBX_ARQLEN_ARQLEN_M			MAKEMASK(0x3FF, 0)
@@ -631,7 +631,7 @@
 #define VSI_MBX_ATQH_MAX_INDEX			767
 #define VSI_MBX_ATQH_ATQH_S			0
 #define VSI_MBX_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VSI_MBX_ATQLEN(_VSI)			(0x02000008 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
+#define VSI_MBX_ATQLEN(_VSI)			(0x02000008 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */
 #define VSI_MBX_ATQLEN_MAX_INDEX		767
 #define VSI_MBX_ATQLEN_ATQLEN_S			0
 #define VSI_MBX_ATQLEN_ATQLEN_M			MAKEMASK(0x3FF, 0)
@@ -808,11 +808,6 @@
 #define GL_SWT_L2TAGTXIB_OFFSET_M		MAKEMASK(0xFF, 0)
 #define GL_SWT_L2TAGTXIB_LENGTH_S		8
 #define GL_SWT_L2TAGTXIB_LENGTH_M		MAKEMASK(0x3, 8)
-#define PRT_TDPUL2TAGSEN			0x00040BA0 /* Reset Source: CORER */
-#define PRT_TDPUL2TAGSEN_ENABLE_S		0
-#define PRT_TDPUL2TAGSEN_ENABLE_M		MAKEMASK(0xFF, 0)
-#define PRT_TDPUL2TAGSEN_NONLAST_TAG_S		8
-#define PRT_TDPUL2TAGSEN_NONLAST_TAG_M		MAKEMASK(0xFF, 8)
 #define GLCM_PE_CACHESIZE			0x005046B4 /* Reset Source: CORER */
 #define GLCM_PE_CACHESIZE_WORD_SIZE_S		0
 #define GLCM_PE_CACHESIZE_WORD_SIZE_M		MAKEMASK(0xFFF, 0)
@@ -1104,7 +1099,7 @@
 #define PF_MBX_ARQH				0x0022E500 /* Reset Source: CORER */
 #define PF_MBX_ARQH_ARQH_S			0
 #define PF_MBX_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define PF_MBX_ARQLEN				0x0022E480 /* Reset Source: CORER */
+#define PF_MBX_ARQLEN				0x0022E480 /* Reset Source: PFR */
 #define PF_MBX_ARQLEN_ARQLEN_S			0
 #define PF_MBX_ARQLEN_ARQLEN_M			MAKEMASK(0x3FF, 0)
 #define PF_MBX_ARQLEN_ARQVFE_S			28
@@ -1127,7 +1122,7 @@
 #define PF_MBX_ATQH				0x0022E280 /* Reset Source: CORER */
 #define PF_MBX_ATQH_ATQH_S			0
 #define PF_MBX_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define PF_MBX_ATQLEN				0x0022E200 /* Reset Source: CORER */
+#define PF_MBX_ATQLEN				0x0022E200 /* Reset Source: PFR */
 #define PF_MBX_ATQLEN_ATQLEN_S			0
 #define PF_MBX_ATQLEN_ATQLEN_M			MAKEMASK(0x3FF, 0)
 #define PF_MBX_ATQLEN_ATQVFE_S			28
@@ -1152,7 +1147,7 @@
 #define PF_SB_ARQH				0x00230000 /* Reset Source: CORER */
 #define PF_SB_ARQH_ARQH_S			0
 #define PF_SB_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define PF_SB_ARQLEN				0x0022FF80 /* Reset Source: CORER */
+#define PF_SB_ARQLEN				0x0022FF80 /* Reset Source: PFR */
 #define PF_SB_ARQLEN_ARQLEN_S			0
 #define PF_SB_ARQLEN_ARQLEN_M			MAKEMASK(0x3FF, 0)
 #define PF_SB_ARQLEN_ARQVFE_S			28
@@ -1175,7 +1170,7 @@
 #define PF_SB_ATQH				0x0022FD80 /* Reset Source: CORER */
 #define PF_SB_ATQH_ATQH_S			0
 #define PF_SB_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define PF_SB_ATQLEN				0x0022FD00 /* Reset Source: CORER */
+#define PF_SB_ATQLEN				0x0022FD00 /* Reset Source: PFR */
 #define PF_SB_ATQLEN_ATQLEN_S			0
 #define PF_SB_ATQLEN_ATQLEN_M			MAKEMASK(0x3FF, 0)
 #define PF_SB_ATQLEN_ATQVFE_S			28
@@ -1303,7 +1298,7 @@
 #define PF0_MBX_CPM_ARQH			0x0022E5E0 /* Reset Source: CORER */
 #define PF0_MBX_CPM_ARQH_ARQH_S			0
 #define PF0_MBX_CPM_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_MBX_CPM_ARQLEN			0x0022E5DC /* Reset Source: CORER */
+#define PF0_MBX_CPM_ARQLEN			0x0022E5DC /* Reset Source: PFR */
 #define PF0_MBX_CPM_ARQLEN_ARQLEN_S		0
 #define PF0_MBX_CPM_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_MBX_CPM_ARQLEN_ARQVFE_S		28
@@ -1326,7 +1321,7 @@
 #define PF0_MBX_CPM_ATQH			0x0022E5CC /* Reset Source: CORER */
 #define PF0_MBX_CPM_ATQH_ATQH_S			0
 #define PF0_MBX_CPM_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_MBX_CPM_ATQLEN			0x0022E5C8 /* Reset Source: CORER */
+#define PF0_MBX_CPM_ATQLEN			0x0022E5C8 /* Reset Source: PFR */
 #define PF0_MBX_CPM_ATQLEN_ATQLEN_S		0
 #define PF0_MBX_CPM_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_MBX_CPM_ATQLEN_ATQVFE_S		28
@@ -1351,7 +1346,7 @@
 #define PF0_MBX_HLP_ARQH			0x0022E608 /* Reset Source: CORER */
 #define PF0_MBX_HLP_ARQH_ARQH_S			0
 #define PF0_MBX_HLP_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_MBX_HLP_ARQLEN			0x0022E604 /* Reset Source: CORER */
+#define PF0_MBX_HLP_ARQLEN			0x0022E604 /* Reset Source: PFR */
 #define PF0_MBX_HLP_ARQLEN_ARQLEN_S		0
 #define PF0_MBX_HLP_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_MBX_HLP_ARQLEN_ARQVFE_S		28
@@ -1374,7 +1369,7 @@
 #define PF0_MBX_HLP_ATQH			0x0022E5F4 /* Reset Source: CORER */
 #define PF0_MBX_HLP_ATQH_ATQH_S			0
 #define PF0_MBX_HLP_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_MBX_HLP_ATQLEN			0x0022E5F0 /* Reset Source: CORER */
+#define PF0_MBX_HLP_ATQLEN			0x0022E5F0 /* Reset Source: PFR */
 #define PF0_MBX_HLP_ATQLEN_ATQLEN_S		0
 #define PF0_MBX_HLP_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_MBX_HLP_ATQLEN_ATQVFE_S		28
@@ -1399,7 +1394,7 @@
 #define PF0_MBX_PSM_ARQH			0x0022E630 /* Reset Source: CORER */
 #define PF0_MBX_PSM_ARQH_ARQH_S			0
 #define PF0_MBX_PSM_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_MBX_PSM_ARQLEN			0x0022E62C /* Reset Source: CORER */
+#define PF0_MBX_PSM_ARQLEN			0x0022E62C /* Reset Source: PFR */
 #define PF0_MBX_PSM_ARQLEN_ARQLEN_S		0
 #define PF0_MBX_PSM_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_MBX_PSM_ARQLEN_ARQVFE_S		28
@@ -1422,7 +1417,7 @@
 #define PF0_MBX_PSM_ATQH			0x0022E61C /* Reset Source: CORER */
 #define PF0_MBX_PSM_ATQH_ATQH_S			0
 #define PF0_MBX_PSM_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_MBX_PSM_ATQLEN			0x0022E618 /* Reset Source: CORER */
+#define PF0_MBX_PSM_ATQLEN			0x0022E618 /* Reset Source: PFR */
 #define PF0_MBX_PSM_ATQLEN_ATQLEN_S		0
 #define PF0_MBX_PSM_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_MBX_PSM_ATQLEN_ATQVFE_S		28
@@ -1447,7 +1442,7 @@
 #define PF0_SB_CPM_ARQH				0x0022E658 /* Reset Source: CORER */
 #define PF0_SB_CPM_ARQH_ARQH_S			0
 #define PF0_SB_CPM_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_SB_CPM_ARQLEN			0x0022E654 /* Reset Source: CORER */
+#define PF0_SB_CPM_ARQLEN			0x0022E654 /* Reset Source: PFR */
 #define PF0_SB_CPM_ARQLEN_ARQLEN_S		0
 #define PF0_SB_CPM_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_SB_CPM_ARQLEN_ARQVFE_S		28
@@ -1470,7 +1465,7 @@
 #define PF0_SB_CPM_ATQH				0x0022E644 /* Reset Source: CORER */
 #define PF0_SB_CPM_ATQH_ATQH_S			0
 #define PF0_SB_CPM_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_SB_CPM_ATQLEN			0x0022E640 /* Reset Source: CORER */
+#define PF0_SB_CPM_ATQLEN			0x0022E640 /* Reset Source: PFR */
 #define PF0_SB_CPM_ATQLEN_ATQLEN_S		0
 #define PF0_SB_CPM_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_SB_CPM_ATQLEN_ATQVFE_S		28
@@ -1498,7 +1493,7 @@
 #define PF0_SB_HLP_ARQH				0x002300E0 /* Reset Source: CORER */
 #define PF0_SB_HLP_ARQH_ARQH_S			0
 #define PF0_SB_HLP_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_SB_HLP_ARQLEN			0x002300DC /* Reset Source: CORER */
+#define PF0_SB_HLP_ARQLEN			0x002300DC /* Reset Source: PFR */
 #define PF0_SB_HLP_ARQLEN_ARQLEN_S		0
 #define PF0_SB_HLP_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_SB_HLP_ARQLEN_ARQVFE_S		28
@@ -1521,7 +1516,7 @@
 #define PF0_SB_HLP_ATQH				0x002300CC /* Reset Source: CORER */
 #define PF0_SB_HLP_ATQH_ATQH_S			0
 #define PF0_SB_HLP_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define PF0_SB_HLP_ATQLEN			0x002300C8 /* Reset Source: CORER */
+#define PF0_SB_HLP_ATQLEN			0x002300C8 /* Reset Source: PFR */
 #define PF0_SB_HLP_ATQLEN_ATQLEN_S		0
 #define PF0_SB_HLP_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define PF0_SB_HLP_ATQLEN_ATQVFE_S		28
@@ -1558,7 +1553,7 @@
 #define VF_MBX_ARQH_MAX_INDEX			255
 #define VF_MBX_ARQH_ARQH_S			0
 #define VF_MBX_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_ARQLEN(_VF)			(0x0022BC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
+#define VF_MBX_ARQLEN(_VF)			(0x0022BC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
 #define VF_MBX_ARQLEN_MAX_INDEX			255
 #define VF_MBX_ARQLEN_ARQLEN_S			0
 #define VF_MBX_ARQLEN_ARQLEN_M			MAKEMASK(0x3FF, 0)
@@ -1586,7 +1581,7 @@
 #define VF_MBX_ATQH_MAX_INDEX			255
 #define VF_MBX_ATQH_ATQH_S			0
 #define VF_MBX_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_ATQLEN(_VF)			(0x0022A800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
+#define VF_MBX_ATQLEN(_VF)			(0x0022A800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
 #define VF_MBX_ATQLEN_MAX_INDEX			255
 #define VF_MBX_ATQLEN_ATQLEN_S			0
 #define VF_MBX_ATQLEN_ATQLEN_M			MAKEMASK(0x3FF, 0)
@@ -1616,7 +1611,7 @@
 #define VF_MBX_CPM_ARQH_MAX_INDEX		127
 #define VF_MBX_CPM_ARQH_ARQH_S			0
 #define VF_MBX_CPM_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_CPM_ARQLEN(_VF128)		(0x0022D600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
+#define VF_MBX_CPM_ARQLEN(_VF128)		(0x0022D600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
 #define VF_MBX_CPM_ARQLEN_MAX_INDEX		127
 #define VF_MBX_CPM_ARQLEN_ARQLEN_S		0
 #define VF_MBX_CPM_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
@@ -1644,7 +1639,7 @@
 #define VF_MBX_CPM_ATQH_MAX_INDEX		127
 #define VF_MBX_CPM_ATQH_ATQH_S			0
 #define VF_MBX_CPM_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_CPM_ATQLEN(_VF128)		(0x0022CC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
+#define VF_MBX_CPM_ATQLEN(_VF128)		(0x0022CC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
 #define VF_MBX_CPM_ATQLEN_MAX_INDEX		127
 #define VF_MBX_CPM_ATQLEN_ATQLEN_S		0
 #define VF_MBX_CPM_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
@@ -1674,7 +1669,7 @@
 #define VF_MBX_HLP_ARQH_MAX_INDEX		15
 #define VF_MBX_HLP_ARQH_ARQH_S			0
 #define VF_MBX_HLP_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_HLP_ARQLEN(_VF16)		(0x0022DDC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
+#define VF_MBX_HLP_ARQLEN(_VF16)		(0x0022DDC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
 #define VF_MBX_HLP_ARQLEN_MAX_INDEX		15
 #define VF_MBX_HLP_ARQLEN_ARQLEN_S		0
 #define VF_MBX_HLP_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
@@ -1702,7 +1697,7 @@
 #define VF_MBX_HLP_ATQH_MAX_INDEX		15
 #define VF_MBX_HLP_ATQH_ATQH_S			0
 #define VF_MBX_HLP_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_HLP_ATQLEN(_VF16)		(0x0022DC80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
+#define VF_MBX_HLP_ATQLEN(_VF16)		(0x0022DC80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
 #define VF_MBX_HLP_ATQLEN_MAX_INDEX		15
 #define VF_MBX_HLP_ATQLEN_ATQLEN_S		0
 #define VF_MBX_HLP_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
@@ -1732,7 +1727,7 @@
 #define VF_MBX_PSM_ARQH_MAX_INDEX		15
 #define VF_MBX_PSM_ARQH_ARQH_S			0
 #define VF_MBX_PSM_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_PSM_ARQLEN(_VF16)		(0x0022E040 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
+#define VF_MBX_PSM_ARQLEN(_VF16)		(0x0022E040 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
 #define VF_MBX_PSM_ARQLEN_MAX_INDEX		15
 #define VF_MBX_PSM_ARQLEN_ARQLEN_S		0
 #define VF_MBX_PSM_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
@@ -1760,7 +1755,7 @@
 #define VF_MBX_PSM_ATQH_MAX_INDEX		15
 #define VF_MBX_PSM_ATQH_ATQH_S			0
 #define VF_MBX_PSM_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_PSM_ATQLEN(_VF16)		(0x0022DF00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
+#define VF_MBX_PSM_ATQLEN(_VF16)		(0x0022DF00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
 #define VF_MBX_PSM_ATQLEN_MAX_INDEX		15
 #define VF_MBX_PSM_ATQLEN_ATQLEN_S		0
 #define VF_MBX_PSM_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
@@ -1790,7 +1785,7 @@
 #define VF_SB_CPM_ARQH_MAX_INDEX		127
 #define VF_SB_CPM_ARQH_ARQH_S			0
 #define VF_SB_CPM_ARQH_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_SB_CPM_ARQLEN(_VF128)		(0x0022F600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
+#define VF_SB_CPM_ARQLEN(_VF128)		(0x0022F600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
 #define VF_SB_CPM_ARQLEN_MAX_INDEX		127
 #define VF_SB_CPM_ARQLEN_ARQLEN_S		0
 #define VF_SB_CPM_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, 0)
@@ -1818,7 +1813,7 @@
 #define VF_SB_CPM_ATQH_MAX_INDEX		127
 #define VF_SB_CPM_ATQH_ATQH_S			0
 #define VF_SB_CPM_ATQH_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_SB_CPM_ATQLEN(_VF128)		(0x0022EC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
+#define VF_SB_CPM_ATQLEN(_VF128)		(0x0022EC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
 #define VF_SB_CPM_ATQLEN_MAX_INDEX		127
 #define VF_SB_CPM_ATQLEN_ATQLEN_S		0
 #define VF_SB_CPM_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, 0)
@@ -3019,7 +3014,7 @@
 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_MAX_INDEX	63
 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_S 0
 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_M MAKEMASK(0xF, 0)
-#define GLFLXP_RXDID_FLX_WRD_0(_i)		(0x0045c800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define GLFLXP_RXDID_FLX_WRD_0(_i)		(0x0045C800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
 #define GLFLXP_RXDID_FLX_WRD_0_MAX_INDEX	63
 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S	0
 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M	MAKEMASK(0xFF, 0)
@@ -3027,7 +3022,7 @@
 #define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S	30
 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M	MAKEMASK(0x3, 30)
-#define GLFLXP_RXDID_FLX_WRD_1(_i)		(0x0045c900 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define GLFLXP_RXDID_FLX_WRD_1(_i)		(0x0045C900 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
 #define GLFLXP_RXDID_FLX_WRD_1_MAX_INDEX	63
 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S	0
 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M	MAKEMASK(0xFF, 0)
@@ -3035,7 +3030,7 @@
 #define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S	30
 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M	MAKEMASK(0x3, 30)
-#define GLFLXP_RXDID_FLX_WRD_2(_i)		(0x0045ca00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define GLFLXP_RXDID_FLX_WRD_2(_i)		(0x0045CA00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
 #define GLFLXP_RXDID_FLX_WRD_2_MAX_INDEX	63
 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S	0
 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M	MAKEMASK(0xFF, 0)
@@ -3043,7 +3038,7 @@
 #define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S	30
 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M	MAKEMASK(0x3, 30)
-#define GLFLXP_RXDID_FLX_WRD_3(_i)		(0x0045cb00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define GLFLXP_RXDID_FLX_WRD_3(_i)		(0x0045CB00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
 #define GLFLXP_RXDID_FLX_WRD_3_MAX_INDEX	63
 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S	0
 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M	MAKEMASK(0xFF, 0)
@@ -3051,7 +3046,7 @@
 #define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S	30
 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M	MAKEMASK(0x3, 30)
-#define GLFLXP_RXDID_FLX_WRD_4(_i)		(0x0045cc00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define GLFLXP_RXDID_FLX_WRD_4(_i)		(0x0045CC00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
 #define GLFLXP_RXDID_FLX_WRD_4_MAX_INDEX	63
 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_S	0
 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_M	MAKEMASK(0xFF, 0)
@@ -3059,7 +3054,7 @@
 #define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_S	30
 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_M	MAKEMASK(0x3, 30)
-#define GLFLXP_RXDID_FLX_WRD_5(_i)		(0x0045cd00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define GLFLXP_RXDID_FLX_WRD_5(_i)		(0x0045CD00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
 #define GLFLXP_RXDID_FLX_WRD_5_MAX_INDEX	63
 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_S	0
 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_M	MAKEMASK(0xFF, 0)
@@ -3233,127 +3228,6 @@
 #define GLGEN_ANA_DEF_PTYPE			0x0020C100 /* Reset Source: CORER */
 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_S		0
 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_M		MAKEMASK(0x3FF, 0)
-#define GLGEN_ANA_DFD_FIFO_0			0x0020C398 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_FIFO_0_PC_NXT_S		0
-#define GLGEN_ANA_DFD_FIFO_0_PC_NXT_M		BIT(0)
-#define GLGEN_ANA_DFD_FIFO_0_HO_NXT_S		1
-#define GLGEN_ANA_DFD_FIFO_0_HO_NXT_M		BIT(1)
-#define GLGEN_ANA_DFD_FIFO_0_NID_NXT_S		2
-#define GLGEN_ANA_DFD_FIFO_0_NID_NXT_M		BIT(2)
-#define GLGEN_ANA_DFD_FIFO_0_PG_KEY_SEL_S	8
-#define GLGEN_ANA_DFD_FIFO_0_PG_KEY_SEL_M	BIT(8)
-#define GLGEN_ANA_DFD_FIFO_PTR			0x0020C43C /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_FIFO_PTR_HEAD_S		0
-#define GLGEN_ANA_DFD_FIFO_PTR_HEAD_M		MAKEMASK(0x1FF, 0)
-#define GLGEN_ANA_DFD_FIFO_PTR_USED_SPACE_S	16
-#define GLGEN_ANA_DFD_FIFO_PTR_USED_SPACE_M	MAKEMASK(0x3FF, 16)
-#define GLGEN_ANA_DFD_GEN_CTRL			0x0020C38C /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_GEN_CTRL_ENABLE_S		0
-#define GLGEN_ANA_DFD_GEN_CTRL_ENABLE_M		BIT(0)
-#define GLGEN_ANA_DFD_GEN_CTRL_BLK_INPUT_S	1
-#define GLGEN_ANA_DFD_GEN_CTRL_BLK_INPUT_M	BIT(1)
-#define GLGEN_ANA_DFD_LOG_0			0x0020C3A8 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_0_SOURCE_S		0
-#define GLGEN_ANA_DFD_LOG_0_SOURCE_M		MAKEMASK(0x7, 0)
-#define GLGEN_ANA_DFD_LOG_0_LVL_OR_EDGE_S	3
-#define GLGEN_ANA_DFD_LOG_0_LVL_OR_EDGE_M	BIT(3)
-#define GLGEN_ANA_DFD_LOG_0_RC_DISP_TRIG_S	4
-#define GLGEN_ANA_DFD_LOG_0_RC_DISP_TRIG_M	MAKEMASK(0x7, 4)
-#define GLGEN_ANA_DFD_LOG_0_FLD_MODE_S		8
-#define GLGEN_ANA_DFD_LOG_0_FLD_MODE_M		BIT(8)
-#define GLGEN_ANA_DFD_LOG_0_DLY_CYCL_S		16
-#define GLGEN_ANA_DFD_LOG_0_DLY_CYCL_M		MAKEMASK(0x3FF, 16)
-#define GLGEN_ANA_DFD_LOG_1			0x0020C3AC /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_1_NUM_EVENTS_S	0
-#define GLGEN_ANA_DFD_LOG_1_NUM_EVENTS_M	MAKEMASK(0x3FF, 0)
-#define GLGEN_ANA_DFD_LOG_1_NUM_TRIGS_S		16
-#define GLGEN_ANA_DFD_LOG_1_NUM_TRIGS_M		MAKEMASK(0x3FF, 16)
-#define GLGEN_ANA_DFD_LOG_ACTN_EN		0x0020C3F8 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_PH_ARB_S	0
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_PH_ARB_M	BIT(0)
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_PH_FB_S	1
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_PH_FB_M	BIT(1)
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_INPUT_S	2
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_INPUT_M	BIT(2)
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_STP_OUTPUT_S	3
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_STP_OUTPUT_M	BIT(3)
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_S 4
-#define GLGEN_ANA_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_M BIT(4)
-#define GLGEN_ANA_DFD_LOG_ACTN_RST		0x0020C3FC /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_PH_ARB_S 0
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_PH_ARB_M BIT(0)
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_PH_FB_S	1
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_PH_FB_M	BIT(1)
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_INPUT_S	2
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_INPUT_M	BIT(2)
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_STP_OUTPUT_S 3
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_STP_OUTPUT_M BIT(3)
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_S 4
-#define GLGEN_ANA_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_M BIT(4)
-#define GLGEN_ANA_DFD_LOG_DATA(_i)		(0x0020C3B0 + ((_i) * 4)) /* _i=0...8 */ /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_DATA_MAX_INDEX	8
-#define GLGEN_ANA_DFD_LOG_DATA_DATA_S		0
-#define GLGEN_ANA_DFD_LOG_DATA_DATA_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLGEN_ANA_DFD_LOG_MASK(_i)		(0x0020C3D4 + ((_i) * 4)) /* _i=0...8 */ /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_MASK_MAX_INDEX	8
-#define GLGEN_ANA_DFD_LOG_MASK_MASK_S		0
-#define GLGEN_ANA_DFD_LOG_MASK_MASK_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLGEN_ANA_DFD_LOG_RST_ALL		0x0020C400 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_RST_ALL_RST_S		0
-#define GLGEN_ANA_DFD_LOG_RST_ALL_RST_M		BIT(0)
-#define GLGEN_ANA_DFD_LOG_RST_ALL_GEN_RST_S	1
-#define GLGEN_ANA_DFD_LOG_RST_ALL_GEN_RST_M	BIT(1)
-#define GLGEN_ANA_DFD_LOG_TRG_0			0x0020C404 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_TRG_0_TAGID_S		0
-#define GLGEN_ANA_DFD_LOG_TRG_0_TAGID_M		MAKEMASK(0x3F, 0)
-#define GLGEN_ANA_DFD_LOG_TRG_0_ACT_TRIGGED_S	16
-#define GLGEN_ANA_DFD_LOG_TRG_0_ACT_TRIGGED_M	BIT(16)
-#define GLGEN_ANA_DFD_LOG_TRG_0_MAX_NUM_RND_S	24
-#define GLGEN_ANA_DFD_LOG_TRG_0_MAX_NUM_RND_M	MAKEMASK(0x7F, 24)
-#define GLGEN_ANA_DFD_LOG_TRG_0_TRIGGED_S	31
-#define GLGEN_ANA_DFD_LOG_TRG_0_TRIGGED_M	BIT(31)
-#define GLGEN_ANA_DFD_LOG_TRG_DATA(_i)		(0x0020C408 + ((_i) * 4)) /* _i=0...8 */ /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_LOG_TRG_DATA_MAX_INDEX	8
-#define GLGEN_ANA_DFD_LOG_TRG_DATA_DATA_S	0
-#define GLGEN_ANA_DFD_LOG_TRG_DATA_DATA_M	MAKEMASK(0xFFFFFFFF, 0)
-#define GLGEN_ANA_DFD_PACE_OUT			0x0020C4CC /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_PACE_OUT_PUSH_S		0
-#define GLGEN_ANA_DFD_PACE_OUT_PUSH_M		BIT(0)
-#define GLGEN_ANA_DFD_PACING_0			0x0020C390 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_PACING_0_STOP_FEEDBK_S	0
-#define GLGEN_ANA_DFD_PACING_0_STOP_FEEDBK_M	BIT(0)
-#define GLGEN_ANA_DFD_PACING_0_STOP_ARB_S	1
-#define GLGEN_ANA_DFD_PACING_0_STOP_ARB_M	BIT(1)
-#define GLGEN_ANA_DFD_PACING_0_NUM_CHUNKS_S	2
-#define GLGEN_ANA_DFD_PACING_0_NUM_CHUNKS_M	MAKEMASK(0x1F, 2)
-#define GLGEN_ANA_DFD_PACING_1			0x0020C394 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_PACING_1_PUSH_S		0
-#define GLGEN_ANA_DFD_PACING_1_PUSH_M		BIT(0)
-#define GLGEN_ANA_DFD_REG_FILE_ACC_0		0x0020C39C /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_REG_FILE_ACC_0_SLOT_ID_S	0
-#define GLGEN_ANA_DFD_REG_FILE_ACC_0_SLOT_ID_M	MAKEMASK(0xF, 0)
-#define GLGEN_ANA_DFD_REG_FILE_ACC_1		0x0020C3A0 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_REG_FILE_ACC_1_REGID_S	0
-#define GLGEN_ANA_DFD_REG_FILE_ACC_1_REGID_M	MAKEMASK(0xFF, 0)
-#define GLGEN_ANA_DFD_REG_FILE_ACC_RES		0x0020C3A4 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_REG_FILE_ACC_RES_REG_VAL_S 0
-#define GLGEN_ANA_DFD_REG_FILE_ACC_RES_REG_VAL_M MAKEMASK(0xFFFF, 0)
-#define GLGEN_ANA_DFD_REG_FILE_ACC_RES_EXCEPTIONS_S 16
-#define GLGEN_ANA_DFD_REG_FILE_ACC_RES_EXCEPTIONS_M MAKEMASK(0x7FFF, 16)
-#define GLGEN_ANA_DFD_TAGIDS			0x0020C438 /* Reset Source: CORER */
-#define GLGEN_ANA_DFD_TAGIDS_TAGID_IN_DFD_FIFO_S 0
-#define GLGEN_ANA_DFD_TAGIDS_TAGID_IN_DFD_FIFO_M MAKEMASK(0x3F, 0)
-#define GLGEN_ANA_DFD_TAGIDS_TAGID_NXT_ANA_S	8
-#define GLGEN_ANA_DFD_TAGIDS_TAGID_NXT_ANA_M	MAKEMASK(0x3F, 8)
-#define GLGEN_ANA_DFD_TAGIDS_TAGID_OUT_S	16
-#define GLGEN_ANA_DFD_TAGIDS_TAGID_OUT_M	MAKEMASK(0x3F, 16)
-#define GLGEN_ANA_DFD_TAGIDS_SLOTID_IN_DFD_FIFO_S 24
-#define GLGEN_ANA_DFD_TAGIDS_SLOTID_IN_DFD_FIFO_M MAKEMASK(0xF, 24)
-#define GLGEN_ANA_DFD_TAGIDS_SLOTID_NXT_ANA_S	28
-#define GLGEN_ANA_DFD_TAGIDS_SLOTID_NXT_ANA_M	MAKEMASK(0xF, 28)
-#define GLGEN_ANA_ERR_AUX			0x0020C228 /* Reset Source: CORER */
-#define GLGEN_ANA_ERR_AUX_IPLEN_GPREG_S		0
-#define GLGEN_ANA_ERR_AUX_IPLEN_GPREG_M		MAKEMASK(0xF, 0)
 #define GLGEN_ANA_ERR_CTRL			0x0020C220 /* Reset Source: CORER */
 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_S	0
 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_M	MAKEMASK(0xFFFFFFFF, 0)
@@ -3363,25 +3237,9 @@
 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_M		BIT(0)
 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_S	1
 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_M	MAKEMASK(0x3F, 1)
-#define GLGEN_ANA_GEN_DFD_RO			0x0020C4C8 /* Reset Source: CORER */
-#define GLGEN_ANA_GEN_DFD_RO_GEN_VAL_S		0
-#define GLGEN_ANA_GEN_DFD_RO_GEN_VAL_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLGEN_ANA_GIGO_FIFO_PTR			0x0020C448 /* Reset Source: CORER */
-#define GLGEN_ANA_GIGO_FIFO_PTR_HEAD_S		0
-#define GLGEN_ANA_GIGO_FIFO_PTR_HEAD_M		MAKEMASK(0x1FF, 0)
-#define GLGEN_ANA_GIGO_FIFO_PTR_USED_SPACE_S	16
-#define GLGEN_ANA_GIGO_FIFO_PTR_USED_SPACE_M	MAKEMASK(0x3FF, 16)
-#define GLGEN_ANA_HDR_FIFO_FIFO_PTR		0x0020C44C /* Reset Source: CORER */
-#define GLGEN_ANA_HDR_FIFO_FIFO_PTR_HEAD_S	0
-#define GLGEN_ANA_HDR_FIFO_FIFO_PTR_HEAD_M	MAKEMASK(0x1FF, 0)
-#define GLGEN_ANA_HDR_FIFO_FIFO_PTR_USED_SPACE_S 16
-#define GLGEN_ANA_HDR_FIFO_FIFO_PTR_USED_SPACE_M MAKEMASK(0x3FF, 16)
 #define GLGEN_ANA_INV_NODE_PTYPE		0x0020C210 /* Reset Source: CORER */
 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0
 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)
-#define GLGEN_ANA_INV_PROT_ID			0x0020C214 /* Reset Source: CORER */
-#define GLGEN_ANA_INV_PROT_ID_INV_PROT_ID_S	0
-#define GLGEN_ANA_INV_PROT_ID_INV_PROT_ID_M	MAKEMASK(0xFF, 0)
 #define GLGEN_ANA_INV_PTYPE_MARKER		0x0020C218 /* Reset Source: CORER */
 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0
 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)
@@ -3391,20 +3249,6 @@
 #define GLGEN_ANA_LAST_PROT_ID_EN_M		BIT(0)
 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_S	1
 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_M	MAKEMASK(0xFF, 1)
-#define GLGEN_ANA_MAX_HDRLEN			0x0020C1E0 /* Reset Source: CORER */
-#define GLGEN_ANA_MAX_HDRLEN_NPC_S		0
-#define GLGEN_ANA_MAX_HDRLEN_NPC_M		MAKEMASK(0xFF, 0)
-#define GLGEN_ANA_MAX_HDRLEN_MAX_HDR_LEN_S	8
-#define GLGEN_ANA_MAX_HDRLEN_MAX_HDR_LEN_M	MAKEMASK(0x1FF, 8)
-#define GLGEN_ANA_MAX_PROT			0x0020C224 /* Reset Source: CORER */
-#define GLGEN_ANA_MAX_PROT_MAX_PRTS_S		0
-#define GLGEN_ANA_MAX_PROT_MAX_PRTS_M		MAKEMASK(0x7F, 0)
-#define GLGEN_ANA_MAX_ROUND			0x0020C20C /* Reset Source: CORER */
-#define GLGEN_ANA_MAX_ROUND_MAX_ROUND_ABS_S	0
-#define GLGEN_ANA_MAX_ROUND_MAX_ROUND_ABS_M	MAKEMASK(0x7F, 0)
-#define GLGEN_ANA_MIN_PKT			0x0020C42C /* Reset Source: CORER */
-#define GLGEN_ANA_MIN_PKT_MIN_LEN_S		0
-#define GLGEN_ANA_MIN_PKT_MIN_LEN_M		MAKEMASK(0x3FFF, 0)
 #define GLGEN_ANA_NMPG_KEYMASK(_i)		(0x0020C1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
 #define GLGEN_ANA_NMPG_KEYMASK_MAX_INDEX	3
 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_S	0
@@ -3444,37 +3288,106 @@
 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M	MAKEMASK(0xF, 16)
 #define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
 #define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
-#define GLGEN_ANA_PSTAT_FIFO_PTR		0x0020C444 /* Reset Source: CORER */
-#define GLGEN_ANA_PSTAT_FIFO_PTR_HEAD_S		0
-#define GLGEN_ANA_PSTAT_FIFO_PTR_HEAD_M		MAKEMASK(0x1FF, 0)
-#define GLGEN_ANA_PSTAT_FIFO_PTR_USED_SPACE_S	16
-#define GLGEN_ANA_PSTAT_FIFO_PTR_USED_SPACE_M	MAKEMASK(0x3FF, 16)
-#define GLGEN_ANA_STAT_FIFO_PTR			0x0020C440 /* Reset Source: CORER */
-#define GLGEN_ANA_STAT_FIFO_PTR_HEAD_S		0
-#define GLGEN_ANA_STAT_FIFO_PTR_HEAD_M		MAKEMASK(0x1FF, 0)
-#define GLGEN_ANA_STAT_FIFO_PTR_USED_SPACE_S	16
-#define GLGEN_ANA_STAT_FIFO_PTR_USED_SPACE_M	MAKEMASK(0x3FF, 16)
-#define GLGEN_ANA_TX_DFD_LOG_0			0x0020D3A8 /* Reset Source: CORER */
-#define GLGEN_ANA_TX_DFD_LOG_0_SOURCE_S		0
-#define GLGEN_ANA_TX_DFD_LOG_0_SOURCE_M		MAKEMASK(0x7, 0)
-#define GLGEN_ANA_TX_DFD_LOG_0_LVL_OR_EDGE_S	3
-#define GLGEN_ANA_TX_DFD_LOG_0_LVL_OR_EDGE_M	BIT(3)
-#define GLGEN_ANA_TX_DFD_LOG_0_RC_DISP_TRIG_S	4
-#define GLGEN_ANA_TX_DFD_LOG_0_RC_DISP_TRIG_M	MAKEMASK(0x7, 4)
-#define GLGEN_ANA_TX_DFD_LOG_0_FLD_MODE_S	8
-#define GLGEN_ANA_TX_DFD_LOG_0_FLD_MODE_M	BIT(8)
-#define GLGEN_ANA_TX_DFD_LOG_0_DLY_CYCL_S	16
-#define GLGEN_ANA_TX_DFD_LOG_0_DLY_CYCL_M	MAKEMASK(0x3FF, 16)
+#define GLGEN_ANA_TX_ABORT_PTYPE		0x0020D21C /* Reset Source: CORER */
+#define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S	0
+#define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M	MAKEMASK(0x3FF, 0)
+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT	0x0020D208 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
+#define GLGEN_ANA_TX_CFG_CTRL			0x0020D104 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S	0
+#define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M	MAKEMASK(0x3FFFF, 0)
+#define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_S	18
+#define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_M	MAKEMASK(0xFF, 18)
+#define GLGEN_ANA_TX_CFG_CTRL_RESRVED_S		26
+#define GLGEN_ANA_TX_CFG_CTRL_RESRVED_M		MAKEMASK(0x7, 26)
+#define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_S	29
+#define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_M	MAKEMASK(0x7, 29)
+#define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT		0x0020D158 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_S	0
+#define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_M	BIT(0)
+#define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_S 1
+#define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1)
+#define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_S	4
+#define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_M	MAKEMASK(0x1FF, 4)
+#define GLGEN_ANA_TX_CFG_LU_KEY(_i)		(0x0020D14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define GLGEN_ANA_TX_CFG_LU_KEY_MAX_INDEX	2
+#define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_S	0
+#define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_CFG_RDDATA(_i)		(0x0020D10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
+#define GLGEN_ANA_TX_CFG_RDDATA_MAX_INDEX	15
+#define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S	0
+#define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT	0x0020D15C /* Reset Source: CORER */
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
+#define GLGEN_ANA_TX_CFG_WRDATA			0x0020D108 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_S	0
+#define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_DEF_PTYPE			0x0020D100 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_S	0
+#define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_M	MAKEMASK(0x3FF, 0)
 #define GLGEN_ANA_TX_DFD_PACE_OUT		0x0020D4CC /* Reset Source: CORER */
 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_S	0
 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_M	BIT(0)
-#define GLGEN_ANA_TX_GEN_DFD_RO			0x0020D4C8 /* Reset Source: CORER */
-#define GLGEN_ANA_TX_GEN_DFD_RO_GEN_VAL_S	0
-#define GLGEN_ANA_TX_GEN_DFD_RO_GEN_VAL_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_ERR_CTRL			0x0020D220 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_S	0
+#define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_FLAG_MAP(_i)		(0x0020D000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define GLGEN_ANA_TX_FLAG_MAP_MAX_INDEX		63
+#define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_S		0
+#define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_M		BIT(0)
+#define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_S	1
+#define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_M	MAKEMASK(0x3F, 1)
+#define GLGEN_ANA_TX_INV_NODE_PTYPE		0x0020D210 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0
+#define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)
+#define GLGEN_ANA_TX_INV_PROT_ID		0x0020D214 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_S	0
+#define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_M	MAKEMASK(0xFF, 0)
+#define GLGEN_ANA_TX_INV_PTYPE_MARKER		0x0020D218 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0
+#define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)
+#define GLGEN_ANA_TX_NMPG_KEYMASK(_i)		(0x0020D1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
+#define GLGEN_ANA_TX_NMPG_KEYMASK_MAX_INDEX	3
+#define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_S	0
+#define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_NMPG0_HASHKEY(_i)		(0x0020D1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
+#define GLGEN_ANA_TX_NMPG0_HASHKEY_MAX_INDEX	3
+#define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_S	0
+#define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_NO_HIT_PG_NM_PG		0x0020D204 /* Reset Source: CORER */
+#define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_S	0
+#define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_M	MAKEMASK(0xFF, 0)
 #define GLGEN_ANA_TX_P2P(_i)			(0x0020D160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
 #define GLGEN_ANA_TX_P2P_MAX_INDEX		15
 #define GLGEN_ANA_TX_P2P_TARGET_PROF_S		0
 #define GLGEN_ANA_TX_P2P_TARGET_PROF_M		MAKEMASK(0xF, 0)
+#define GLGEN_ANA_TX_PG_KEYMASK(_i)		(0x0020D1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
+#define GLGEN_ANA_TX_PG_KEYMASK_MAX_INDEX	3
+#define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_S	0
+#define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_PG0_HASHKEY(_i)		(0x0020D1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
+#define GLGEN_ANA_TX_PG0_HASHKEY_MAX_INDEX	3
+#define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_S	0
+#define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_M	MAKEMASK(0xFFFFFFFF, 0)
+#define GLGEN_ANA_TX_PROFIL_CTRL		0x0020D1FC /* Reset Source: CORER */
+#define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0
+#define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)
+#define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5
+#define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
+#define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9
+#define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
+#define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
+#define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
+#define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_S	16
+#define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_M	MAKEMASK(0xF, 16)
+#define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
+#define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
 #define GLGEN_ASSERT_HLP			0x000B81E4 /* Reset Source: POR */
 #define GLGEN_ASSERT_HLP_CORE_ON_RST_S		0
 #define GLGEN_ASSERT_HLP_CORE_ON_RST_M		BIT(0)
@@ -3558,6 +3471,15 @@
 #define GLGEN_RSTAT_RTRIG_ECC_M			BIT(17)
 #define GLGEN_RSTAT_RTRIG_FW_AUX_S		18
 #define GLGEN_RSTAT_RTRIG_FW_AUX_M		BIT(18)
+#define GLGEN_RSTCTL				0x000B8180 /* Reset Source: POR */
+#define GLGEN_RSTCTL_GRSTDEL_S			0
+#define GLGEN_RSTCTL_GRSTDEL_M			MAKEMASK(0x3F, 0)
+#define GLGEN_RSTCTL_ECC_RST_ENA_S		8
+#define GLGEN_RSTCTL_ECC_RST_ENA_M		BIT(8)
+#define GLGEN_RSTCTL_ECC_RT_EN_S		30
+#define GLGEN_RSTCTL_ECC_RT_EN_M		BIT(30)
+#define GLGEN_RSTCTL_FLR_RT_EN_S		31
+#define GLGEN_RSTCTL_FLR_RT_EN_M		BIT(31)
 #define GLGEN_RTRIG				0x000B8190 /* Reset Source: CORER */
 #define GLGEN_RTRIG_CORER_S			0
 #define GLGEN_RTRIG_CORER_M			BIT(0)
@@ -3580,238 +3502,6 @@
 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_M MAKEMASK(0x1F, 0)
 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_S 8
 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_M MAKEMASK(0xFF, 8)
-#define GLQDC_DFD_CAM_ACC			0x002D2E24 /* Reset Source: CORER */
-#define GLQDC_DFD_CAM_ACC_CLNUM_S		0
-#define GLQDC_DFD_CAM_ACC_CLNUM_M		MAKEMASK(0x7F, 0)
-#define GLQDC_DFD_CAM_ACC_RES_0			0x002D2E28 /* Reset Source: CORER */
-#define GLQDC_DFD_CAM_ACC_RES_0_QID_S		0
-#define GLQDC_DFD_CAM_ACC_RES_0_QID_M		MAKEMASK(0x3FFF, 0)
-#define GLQDC_DFD_CAM_ACC_RES_0_CAM_V_S		16
-#define GLQDC_DFD_CAM_ACC_RES_0_CAM_V_M		BIT(16)
-#define GLQDC_DFD_CAM_ACC_RES_0_CAM_E_S		31
-#define GLQDC_DFD_CAM_ACC_RES_0_CAM_E_M		BIT(31)
-#define GLQDC_DFD_CAM_ACC_RES_1			0x002D2E2C /* Reset Source: CORER */
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_HEAD_S	0
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_HEAD_M	MAKEMASK(0x3F, 0)
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_TAIL_S	8
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_TAIL_M	MAKEMASK(0x3F, 8)
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_EMPTY_S	16
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_EMPTY_M	BIT(16)
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_MALC_S	24
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_MALC_M	MAKEMASK(0x3F, 24)
-#define GLQDC_DFD_FIFO_CFG_0			0x002D2E34 /* Reset Source: CORER */
-#define GLQDC_DFD_FIFO_CFG_0_QID_S		0
-#define GLQDC_DFD_FIFO_CFG_0_QID_M		MAKEMASK(0x3FFF, 0)
-#define GLQDC_DFD_FIFO_CFG_0_SMPL_PT_S		16
-#define GLQDC_DFD_FIFO_CFG_0_SMPL_PT_M		MAKEMASK(0xFF, 16)
-#define GLQDC_DFD_FIFO_CFG_0_ALL_QID_S		31
-#define GLQDC_DFD_FIFO_CFG_0_ALL_QID_M		BIT(31)
-#define GLQDC_DFD_FIFO_CFG_1			0x002D2E38 /* Reset Source: CORER */
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_0_S		0
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_0_M		MAKEMASK(0x7, 0)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_1_S		4
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_1_M		MAKEMASK(0x7, 4)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_2_S		8
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_2_M		MAKEMASK(0x7, 8)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_3_S		12
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_3_M		MAKEMASK(0x7, 12)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_4_S		16
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_4_M		MAKEMASK(0x7, 16)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_5_S		20
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_5_M		MAKEMASK(0x7, 20)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_6_S		24
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_6_M		MAKEMASK(0x7, 24)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_7_S		28
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_7_M		MAKEMASK(0x7, 28)
-#define GLQDC_DFD_FIFO_SZ_CFG			0x002D30AC /* Reset Source: CORER */
-#define GLQDC_DFD_FIFO_SZ_CFG_COMP_S		0
-#define GLQDC_DFD_FIFO_SZ_CFG_COMP_M		MAKEMASK(0xFF, 0)
-#define GLQDC_DFD_FIFO_SZ_CFG_MISS_S		8
-#define GLQDC_DFD_FIFO_SZ_CFG_MISS_M		MAKEMASK(0xFF, 8)
-#define GLQDC_DFD_FIFO_SZ_CFG_MISS_COMP_S	16
-#define GLQDC_DFD_FIFO_SZ_CFG_MISS_COMP_M	MAKEMASK(0xFF, 16)
-#define GLQDC_DFD_GEN_CHKN			0x002D30A0 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_CHKN_GEN_BITS_S		0
-#define GLQDC_DFD_GEN_CHKN_GEN_BITS_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_CHKN_2			0x002D30A4 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_CHKN_2_GEN_BITS_S		0
-#define GLQDC_DFD_GEN_CHKN_2_GEN_BITS_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_CTRL			0x002D2E20 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_CTRL_ENABLE_S		0
-#define GLQDC_DFD_GEN_CTRL_ENABLE_M		BIT(0)
-#define GLQDC_DFD_GEN_CTRL_BLK_INJECT_M1_S	1
-#define GLQDC_DFD_GEN_CTRL_BLK_INJECT_M1_M	BIT(1)
-#define GLQDC_DFD_GEN_CTRL_NUM_PAUSE_M1_S	16
-#define GLQDC_DFD_GEN_CTRL_NUM_PAUSE_M1_M	MAKEMASK(0x3FF, 16)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0		0x002D2EE8 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_ACK_S 0
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_ACK_M MAKEMASK(0x7F, 0)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_S 7
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_M MAKEMASK(0x7F, 7)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_DATA_S 14
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_DATA_M MAKEMASK(0x3, 14)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_S	16
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_M	MAKEMASK(0x7F, 16)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_PCIE_OUT_S	23
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_PCIE_OUT_M	MAKEMASK(0x7, 23)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1		0x002D2EEC /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_MISS_FSM_S	0
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_MISS_FSM_M	MAKEMASK(0x7F, 0)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_DFD_S	7
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_DFD_M	MAKEMASK(0xFF, 7)
-#define GLQDC_DFD_GEN_LOG_FSM			0x002D2EF0 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOG_FSM_FTSTATE_S		0
-#define GLQDC_DFD_GEN_LOG_FSM_FTSTATE_M		MAKEMASK(0x3, 0)
-#define GLQDC_DFD_GEN_LOG_FSM_MISS_FIFO_FSM_ST_S 2
-#define GLQDC_DFD_GEN_LOG_FSM_MISS_FIFO_FSM_ST_M MAKEMASK(0x7, 2)
-#define GLQDC_DFD_GEN_LOG_FSM_IN_MISS_FIFO_S	5
-#define GLQDC_DFD_GEN_LOG_FSM_IN_MISS_FIFO_M	MAKEMASK(0x3, 5)
-#define GLQDC_DFD_GEN_LOG_FSM_CPSTATE_S		7
-#define GLQDC_DFD_GEN_LOG_FSM_CPSTATE_M		MAKEMASK(0x7, 7)
-#define GLQDC_DFD_GEN_LOGGNG_0			0x002D2EE0 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_0_RINGH_WR_RD_S	0
-#define GLQDC_DFD_GEN_LOGGNG_0_RINGH_WR_RD_M	BIT(0)
-#define GLQDC_DFD_GEN_LOGGNG_0_QD_WR_RD_S	1
-#define GLQDC_DFD_GEN_LOGGNG_0_QD_WR_RD_M	BIT(1)
-#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_RD_REQ_VLD_S 2
-#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_RD_REQ_VLD_M BIT(2)
-#define GLQDC_DFD_GEN_LOGGNG_0_NXT_SQ_VLD_S	3
-#define GLQDC_DFD_GEN_LOGGNG_0_NXT_SQ_VLD_M	BIT(3)
-#define GLQDC_DFD_GEN_LOGGNG_0_SQ_VLD_TO_DONE_S 4
-#define GLQDC_DFD_GEN_LOGGNG_0_SQ_VLD_TO_DONE_M BIT(4)
-#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_COMP_VLD_S	5
-#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_COMP_VLD_M	BIT(5)
-#define GLQDC_DFD_GEN_LOGGNG_0_FETCH_NXT_SQ_VLD_S 6
-#define GLQDC_DFD_GEN_LOGGNG_0_FETCH_NXT_SQ_VLD_M BIT(6)
-#define GLQDC_DFD_GEN_LOGGNG_0_MALC_RPT_S	8
-#define GLQDC_DFD_GEN_LOGGNG_0_MALC_RPT_M	MAKEMASK(0xF, 8)
-#define GLQDC_DFD_GEN_LOGGNG_0_DFD_FIFO_ADD_S	16
-#define GLQDC_DFD_GEN_LOGGNG_0_DFD_FIFO_ADD_M	MAKEMASK(0x7F, 16)
-#define GLQDC_DFD_GEN_LOGGNG_1			0x002D2EE4 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_WM_S	0
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_WM_M	MAKEMASK(0x3, 0)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_S	2
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_M	MAKEMASK(0x3, 2)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_WM_S	4
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_WM_M	MAKEMASK(0x3, 4)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_S	6
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_M	MAKEMASK(0x3, 6)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_WM_S	8
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_WM_M	MAKEMASK(0x3, 8)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_S		10
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_M		MAKEMASK(0x3, 10)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_WM_S 12
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_WM_M MAKEMASK(0x3, 12)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_S	14
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_M	MAKEMASK(0x3, 14)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_WM_S 16
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_WM_M MAKEMASK(0x3, 16)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_S 18
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_M MAKEMASK(0x3, 18)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_WM_S	20
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_WM_M	MAKEMASK(0x3, 20)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_S	22
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_M	MAKEMASK(0x3, 22)
-#define GLQDC_DFD_GEN_LOGGNG_2			0x002D2FFC /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_S	0
-#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_M	MAKEMASK(0x3F, 0)
-#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_LT_S 6
-#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_LT_M MAKEMASK(0x3F, 6)
-#define GLQDC_DFD_GEN_LOGGNG_2_TEST_S		24
-#define GLQDC_DFD_GEN_LOGGNG_2_TEST_M		MAKEMASK(0xFF, 24)
-#define GLQDC_DFD_GEN_LOGGNG_3			0x002D3008 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_3_GEN_S		0
-#define GLQDC_DFD_GEN_LOGGNG_3_GEN_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_LOGGNG_4			0x002D300C /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_4_GEN_S		0
-#define GLQDC_DFD_GEN_LOGGNG_4_GEN_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_LOGGNG_5			0x002D3010 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_5_GEN_S		0
-#define GLQDC_DFD_GEN_LOGGNG_5_GEN_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_LOGGNG_6			0x002D3014 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_6_GEN_S		0
-#define GLQDC_DFD_GEN_LOGGNG_6_GEN_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_STAT_REGS(_i)		(0x002D3018 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_STAT_REGS_MAX_INDEX	15
-#define GLQDC_DFD_GEN_STAT_REGS_COUNT_S		0
-#define GLQDC_DFD_GEN_STAT_REGS_COUNT_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_LOG_0				0x002D2E3C /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_0_SOURCE_S		0
-#define GLQDC_DFD_LOG_0_SOURCE_M		MAKEMASK(0x3, 0)
-#define GLQDC_DFD_LOG_0_LVL_OR_EDGE_S		4
-#define GLQDC_DFD_LOG_0_LVL_OR_EDGE_M		BIT(4)
-#define GLQDC_DFD_LOG_0_DLY_CYCL_S		16
-#define GLQDC_DFD_LOG_0_DLY_CYCL_M		MAKEMASK(0x3FF, 16)
-#define GLQDC_DFD_LOG_1				0x002D2E40 /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_1_NUM_EVENTS_S		0
-#define GLQDC_DFD_LOG_1_NUM_EVENTS_M		MAKEMASK(0x3FF, 0)
-#define GLQDC_DFD_LOG_1_NUM_TRIGS_S		16
-#define GLQDC_DFD_LOG_1_NUM_TRIGS_M		MAKEMASK(0x3FF, 16)
-#define GLQDC_DFD_LOG_1_TRIG_B2B_S		31
-#define GLQDC_DFD_LOG_1_TRIG_B2B_M		BIT(31)
-#define GLQDC_DFD_LOG_ACTN_EN			0x002D2EA4 /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_ACTN_EN_BLK_INJECT_M1_S	0
-#define GLQDC_DFD_LOG_ACTN_EN_BLK_INJECT_M1_M	BIT(0)
-#define GLQDC_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_S 1
-#define GLQDC_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_M BIT(1)
-#define GLQDC_DFD_LOG_ACTN_EN_STP_UPDT_MALC_RPT_CSR_S 2
-#define GLQDC_DFD_LOG_ACTN_EN_STP_UPDT_MALC_RPT_CSR_M BIT(2)
-#define GLQDC_DFD_LOG_ACTN_RST			0x002D2EA8 /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_ACTN_RST_BLK_INJECT_M1_S	0
-#define GLQDC_DFD_LOG_ACTN_RST_BLK_INJECT_M1_M	BIT(0)
-#define GLQDC_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_S 1
-#define GLQDC_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_M BIT(1)
-#define GLQDC_DFD_LOG_ACTN_RST_STP_UPDT_MALC_RPT_CSR_S 2
-#define GLQDC_DFD_LOG_ACTN_RST_STP_UPDT_MALC_RPT_CSR_M BIT(2)
-#define GLQDC_DFD_LOG_DATA(_i)			(0x002D2E44 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_DATA_MAX_INDEX		11
-#define GLQDC_DFD_LOG_DATA_DATA_S		0
-#define GLQDC_DFD_LOG_DATA_DATA_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_LOG_MASK(_i)			(0x002D2E74 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_MASK_MAX_INDEX		11
-#define GLQDC_DFD_LOG_MASK_MASK_S		0
-#define GLQDC_DFD_LOG_MASK_MASK_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_LOG_TRG_0			0x002D2EAC /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_TRG_0_QID_S		0
-#define GLQDC_DFD_LOG_TRG_0_QID_M		MAKEMASK(0x3FFF, 0)
-#define GLQDC_DFD_LOG_TRG_0_ACT_TRIGGED_S	16
-#define GLQDC_DFD_LOG_TRG_0_ACT_TRIGGED_M	BIT(16)
-#define GLQDC_DFD_LOG_TRG_0_TRIGGED_S		31
-#define GLQDC_DFD_LOG_TRG_0_TRIGGED_M		BIT(31)
-#define GLQDC_DFD_LOG_TRG_DATA(_i)		(0x002D2EB0 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_TRG_DATA_MAX_INDEX	11
-#define GLQDC_DFD_LOG_TRG_DATA_DATA_S		0
-#define GLQDC_DFD_LOG_TRG_DATA_DATA_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_PACE				0x002D3000 /* Reset Source: CORER */
-#define GLQDC_DFD_PACE_PUSH_S			0
-#define GLQDC_DFD_PACE_PUSH_M			BIT(0)
-#define GLQDC_DFD_RST				0x002D2E30 /* Reset Source: CORER */
-#define GLQDC_DFD_RST_RST_S			0
-#define GLQDC_DFD_RST_RST_M			BIT(0)
-#define GLQDC_DFD_RST_CLR_MALC_RPT_S		1
-#define GLQDC_DFD_RST_CLR_MALC_RPT_M		BIT(1)
-#define GLQDC_DFD_RST_LOG_RST_S			2
-#define GLQDC_DFD_RST_LOG_RST_M			BIT(2)
-#define GLQDC_DFD_SAMPLE_RO_CSR			0x002D3004 /* Reset Source: CORER */
-#define GLQDC_DFD_SAMPLE_RO_CSR_SMPL_S		0
-#define GLQDC_DFD_SAMPLE_RO_CSR_SMPL_M		BIT(0)
-#define GLQDC_DFD_STATS_CFG_0			0x002D3058 /* Reset Source: CORER */
-#define GLQDC_DFD_STATS_CFG_0_CLR_S		0
-#define GLQDC_DFD_STATS_CFG_0_CLR_M		BIT(0)
-#define GLQDC_DFD_STATS_CFG_1			0x002D305C /* Reset Source: CORER */
-#define GLQDC_DFD_STATS_CFG_1_QID_S		0
-#define GLQDC_DFD_STATS_CFG_1_QID_M		MAKEMASK(0x3FFF, 0)
-#define GLQDC_DFD_STATS_CFG_1_GEN_CFG_S		16
-#define GLQDC_DFD_STATS_CFG_1_GEN_CFG_M		MAKEMASK(0x1F, 16)
-#define GLQDC_DFD_STATS_CFG_EVNT(_i)		(0x002D3060 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
-#define GLQDC_DFD_STATS_CFG_EVNT_MAX_INDEX	15
-#define GLQDC_DFD_STATS_CFG_EVNT_EVNT_ID_S	0
-#define GLQDC_DFD_STATS_CFG_EVNT_EVNT_ID_M	MAKEMASK(0x1F, 0)
-#define GLQDC_DFD_STATS_CFG_EVNT_WRAP_EN_S	31
-#define GLQDC_DFD_STATS_CFG_EVNT_WRAP_EN_M	BIT(31)
-#define GLQDC_DFD_TEST_MNG			0x002D30A8 /* Reset Source: CORER */
-#define GLQDC_DFD_TEST_MNG_TST_S		2
-#define GLQDC_DFD_TEST_MNG_TST_M		BIT(2)
 #define GLVFGEN_TIMER				0x000B8214 /* Reset Source: POR */
 #define GLVFGEN_TIMER_GTIME_S			0
 #define GLVFGEN_TIMER_GTIME_M			MAKEMASK(0xFFFFFFFF, 0)
@@ -3915,7 +3605,7 @@
 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_M		MAKEMASK(0x1FFFFFFF, 0)
 #define GLHMC_FSIAVMAX				0x00522068 /* Reset Source: CORER */
 #define GLHMC_FSIAVMAX_PMFSIAVMAX_S		0
-#define GLHMC_FSIAVMAX_PMFSIAVMAX_M		MAKEMASK(0x1FFFF, 0)
+#define GLHMC_FSIAVMAX_PMFSIAVMAX_M		MAKEMASK(0x3FFFF, 0)
 #define GLHMC_FSIAVOBJSZ			0x00522064 /* Reset Source: CORER */
 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_S		0
 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_M		MAKEMASK(0xF, 0)
@@ -3940,7 +3630,7 @@
 #define GLHMC_FWPDINV_PMSDPARTSEL_M		BIT(15)
 #define GLHMC_FWPDINV_PMPDIDX_S			16
 #define GLHMC_FWPDINV_PMPDIDX_M			MAKEMASK(0x1FF, 16)
-#define GLHMC_FWPDINV_FPMAT			0x0010207c /* Reset Source: CORER */
+#define GLHMC_FWPDINV_FPMAT			0x0010207C /* Reset Source: CORER */
 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_S		0
 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_M		MAKEMASK(0xFFF, 0)
 #define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_S	15
@@ -4033,7 +3723,7 @@
 #define GLHMC_PEHTEOBJSZ			0x0052202C /* Reset Source: CORER */
 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_S		0
 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_M		MAKEMASK(0xF, 0)
-#define GLHMC_PEHTEOBJSZ_FPMAT			0x0010202c /* Reset Source: CORER */
+#define GLHMC_PEHTEOBJSZ_FPMAT			0x0010202C /* Reset Source: CORER */
 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_S	0
 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_M	MAKEMASK(0xF, 0)
 #define GLHMC_PEHTMAX				0x00522030 /* Reset Source: CORER */
@@ -4071,7 +3761,7 @@
 #define GLHMC_PEMRMAX				0x00522040 /* Reset Source: CORER */
 #define GLHMC_PEMRMAX_PMPEMRMAX_S		0
 #define GLHMC_PEMRMAX_PMPEMRMAX_M		MAKEMASK(0x7FFFFF, 0)
-#define GLHMC_PEMROBJSZ				0x0052203c /* Reset Source: CORER */
+#define GLHMC_PEMROBJSZ				0x0052203C /* Reset Source: CORER */
 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_S		0
 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_M		MAKEMASK(0xF, 0)
 #define GLHMC_PEOOISCBASE(_i)			(0x00526600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
@@ -4207,7 +3897,7 @@
 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_M	MAKEMASK(0xFFFFFF, 0)
 #define GLHMC_PEXFFLMAX				0x0052204C /* Reset Source: CORER */
 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_S		0
-#define GLHMC_PEXFFLMAX_PMPEXFFLMAX_M		MAKEMASK(0x3FFFFFF, 0)
+#define GLHMC_PEXFFLMAX_PMPEXFFLMAX_M		MAKEMASK(0xFFFFFFF, 0)
 #define GLHMC_PEXFMAX				0x00522048 /* Reset Source: CORER */
 #define GLHMC_PEXFMAX_PMPEXFMAX_S		0
 #define GLHMC_PEXFMAX_PMPEXFMAX_M		MAKEMASK(0xFFFFFFF, 0)
@@ -4320,7 +4010,7 @@
 #define GLHMC_VFPEHTCNT_MAX_INDEX		31
 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_S		0
 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_M		MAKEMASK(0x1FFFFFFF, 0)
-#define GLHMC_VFPEHTCNT_FPMAT(_i)		(0x0010c700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
+#define GLHMC_VFPEHTCNT_FPMAT(_i)		(0x0010C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
 #define GLHMC_VFPEHTCNT_FPMAT_MAX_INDEX		31
 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_S	0
 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_M	MAKEMASK(0x1FFFFFFF, 0)
@@ -4589,9 +4279,6 @@
 #define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_M	MAKEMASK(0x3FF, 2)
 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_S	12
 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_M	MAKEMASK(0xFFFFF, 12)
-#define GL_DSI_RDPC				0x00294204 /* Reset Source: CORER */
-#define GL_DSI_RDPC_RDPC_S			0
-#define GL_DSI_RDPC_RDPC_M			MAKEMASK(0xFFFFFFFF, 0)
 #define GL_DSI_REPC				0x00294208 /* Reset Source: CORER */
 #define GL_DSI_REPC_NO_DESC_CNT_S		0
 #define GL_DSI_REPC_NO_DESC_CNT_M		MAKEMASK(0xFFFF, 0)
@@ -4640,18 +4327,6 @@
 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_M BIT(19)
 #define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_S 20
 #define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_M BIT(20)
-#define GL_PPRS_SPARE_0				0x000841A8 /* Reset Source: CORER */
-#define GL_PPRS_SPARE_0_GL_PPRS_SPARE_S		0
-#define GL_PPRS_SPARE_0_GL_PPRS_SPARE_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GL_PPRS_SPARE_1				0x000851A8 /* Reset Source: CORER */
-#define GL_PPRS_SPARE_1_GL_PPRS_SPARE_S		0
-#define GL_PPRS_SPARE_1_GL_PPRS_SPARE_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GL_PPRS_SPARE_2				0x000861A8 /* Reset Source: CORER */
-#define GL_PPRS_SPARE_2_GL_PPRS_SPARE_S		0
-#define GL_PPRS_SPARE_2_GL_PPRS_SPARE_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GL_PPRS_SPARE_3				0x000871A8 /* Reset Source: CORER */
-#define GL_PPRS_SPARE_3_GL_PPRS_SPARE_S		0
-#define GL_PPRS_SPARE_3_GL_PPRS_SPARE_M		MAKEMASK(0xFFFFFFFF, 0)
 #define GLCORE_CLKCTL_H				0x000B81E8 /* Reset Source: POR */
 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_S	0
 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_M	MAKEMASK(0x3, 0)
@@ -4692,44 +4367,6 @@
 #define GLFOC_CACHESIZE_SETS_M			MAKEMASK(0xFFF, 8)
 #define GLFOC_CACHESIZE_WAYS_S			20
 #define GLFOC_CACHESIZE_WAYS_M			MAKEMASK(0xF, 20)
-#define GLGEN_CAR_DEBUG				0x000B81C0 /* Reset Source: POR */
-#define GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_S 0
-#define GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_M BIT(0)
-#define GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_S	1
-#define GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_M	BIT(1)
-#define GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_S		2
-#define GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_M		BIT(2)
-#define GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_S 3
-#define GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_M BIT(3)
-#define GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_S		4
-#define GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_M		BIT(4)
-#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_S 5
-#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_M BIT(5)
-#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_S 6
-#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_M BIT(6)
-#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_S 7
-#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_M BIT(7)
-#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_S 8
-#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_M BIT(8)
-#define GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_S	9
-#define GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_M	BIT(9)
-#define GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_S 10
-#define GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_M BIT(10)
-#define GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_S 11
-#define GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_M BIT(11)
-#define GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_S 12
-#define GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_M BIT(12)
-#define GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_S	13
-#define GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_M	BIT(13)
-#define GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_S	14
-#define GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_M	BIT(14)
-#define GLGEN_CAR_DEBUG_CAR_RST_STATE_S		15
-#define GLGEN_CAR_DEBUG_CAR_RST_STATE_M		MAKEMASK(0xF, 15)
-#define GLGEN_CAR_SPARE				0x000B81C4 /* Reset Source: POR */
-#define GLGEN_CAR_SPARE_SPARE_CLEAR_S		0
-#define GLGEN_CAR_SPARE_SPARE_CLEAR_M		MAKEMASK(0xFFFF, 0)
-#define GLGEN_CAR_SPARE_SPARE_SET_S		16
-#define GLGEN_CAR_SPARE_SPARE_SET_M		MAKEMASK(0xFFFF, 16)
 #define GLMAC_CLKSTAT				0x000B8210 /* Reset Source: POR */
 #define GLMAC_CLKSTAT_P0_CLK_SPEED_S		0
 #define GLMAC_CLKSTAT_P0_CLK_SPEED_M		MAKEMASK(0xF, 0)
@@ -4747,15 +4384,6 @@
 #define GLMAC_CLKSTAT_P6_CLK_SPEED_M		MAKEMASK(0xF, 24)
 #define GLMAC_CLKSTAT_P7_CLK_SPEED_S		28
 #define GLMAC_CLKSTAT_P7_CLK_SPEED_M		MAKEMASK(0xF, 28)
-#define GLRCB_DCB_LAN_PMS			0x001223F8 /* Reset Source: CORER */
-#define GLRCB_DCB_LAN_PMS_PSM_LAN_S		0
-#define GLRCB_DCB_LAN_PMS_PSM_LAN_M		MAKEMASK(0x3FFF, 0)
-#define GLRCB_DCB_RDMA_PMS			0x001223FC /* Reset Source: CORER */
-#define GLRCB_DCB_RDMA_PMS_PSM_RDMA_S		0
-#define GLRCB_DCB_RDMA_PMS_PSM_RDMA_M		MAKEMASK(0x3FFF, 0)
-#define GLRLAN_MDET				0x00294200 /* Reset Source: CORER */
-#define GLRLAN_MDET_PCKT_EXTRCT_ERR_S		0
-#define GLRLAN_MDET_PCKT_EXTRCT_ERR_M		BIT(0)
 #define GLTPB_100G_MAC_FC_THRESH		0x00099510 /* Reset Source: CORER */
 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_S 0
 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
@@ -4797,11 +4425,6 @@
 #define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_M	BIT(6)
 #define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_S	7
 #define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_M	BIT(7)
-#define GLTSYN_HH_DBG				0x000889F0 /* Reset Source: CORER */
-#define GLTSYN_HH_DBG_HH_SYNC_S			0
-#define GLTSYN_HH_DBG_HH_SYNC_M			BIT(0)
-#define GLTSYN_HH_DBG_HH_LATCH_EN_S		1
-#define GLTSYN_HH_DBG_HH_LATCH_EN_M		BIT(1)
 #define TPB_CFG_SCHEDULED_BC_THRESHOLD		0x00099494 /* Reset Source: CORER */
 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_S 0
 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_M MAKEMASK(0x7FFF, 0)
@@ -4843,12 +4466,6 @@
 #define EMPINT_GPIO_ENA_GPIO5_ENA_M		BIT(5)
 #define EMPINT_GPIO_ENA_GPIO6_ENA_S		6
 #define EMPINT_GPIO_ENA_GPIO6_ENA_M		BIT(6)
-#define GL_CLKGEN_DEBUG				0x000B8268 /* Reset Source: POR */
-#define GL_CLKGEN_DEBUG_PROBE_S			0
-#define GL_CLKGEN_DEBUG_PROBE_M			MAKEMASK(0xFFFFFFFF, 0)
-#define GL_CLKGEN_DEBUG_SEL			0x000B8264 /* Reset Source: POR */
-#define GL_CLKGEN_DEBUG_SEL_GL_CLKGEN_DEBUG_SEL_S 0
-#define GL_CLKGEN_DEBUG_SEL_GL_CLKGEN_DEBUG_SEL_M MAKEMASK(0xFFFF, 0)
 #define GLGEN_MAC_LINK_TOPO			0x000B81DC /* Reset Source: GLOBR */
 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_S		0
 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M		MAKEMASK(0x3, 0)
@@ -4875,7 +4492,7 @@
 #define GLINT_CTL_ITR_GRAN_50_M			MAKEMASK(0xF, 24)
 #define GLINT_CTL_ITR_GRAN_25_S			28
 #define GLINT_CTL_ITR_GRAN_25_M			MAKEMASK(0xF, 28)
-#define GLINT_DYN_CTL(_INT)			(0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */
+#define GLINT_DYN_CTL(_INT)			(0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
 #define GLINT_DYN_CTL_MAX_INDEX			2047
 #define GLINT_DYN_CTL_INTENA_S			0
 #define GLINT_DYN_CTL_INTENA_M			BIT(0)
@@ -4904,11 +4521,11 @@
 #define GLINT_FW_TOOL_CTL_CAUSE_ENA_M		BIT(30)
 #define GLINT_FW_TOOL_CTL_INTEVENT_S		31
 #define GLINT_FW_TOOL_CTL_INTEVENT_M		BIT(31)
-#define GLINT_ITR(_i, _INT)			(0x00154000 + ((_i) * 8192 + (_INT) * 4)) /* _i=0...2, _INT=0...2047 */ /* Reset Source: PFR */
+#define GLINT_ITR(_i, _INT)			(0x00154000 + ((_i) * 8192 + (_INT) * 4)) /* _i=0...2, _INT=0...2047 */ /* Reset Source: CORER */
 #define GLINT_ITR_MAX_INDEX			2
 #define GLINT_ITR_INTERVAL_S			0
 #define GLINT_ITR_INTERVAL_M			MAKEMASK(0xFFF, 0)
-#define GLINT_RATE(_INT)			(0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */
+#define GLINT_RATE(_INT)			(0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
 #define GLINT_RATE_MAX_INDEX			2047
 #define GLINT_RATE_INTERVAL_S			0
 #define GLINT_RATE_INTERVAL_M			MAKEMASK(0x3F, 0)
@@ -5477,6 +5094,11 @@
 #define PFLAN_TX_QALLOC_LASTQ_M			MAKEMASK(0x3FFF, 16)
 #define PFLAN_TX_QALLOC_VALID_S			31
 #define PFLAN_TX_QALLOC_VALID_M			BIT(31)
+#define PRT_TDPUL2TAGSEN			0x00040BA0 /* Reset Source: CORER */
+#define PRT_TDPUL2TAGSEN_ENABLE_S		0
+#define PRT_TDPUL2TAGSEN_ENABLE_M		MAKEMASK(0xFF, 0)
+#define PRT_TDPUL2TAGSEN_NONLAST_TAG_S		8
+#define PRT_TDPUL2TAGSEN_NONLAST_TAG_M		MAKEMASK(0xFF, 8)
 #define QRX_CONTEXT(_i, _QRX)			(0x00280000 + ((_i) * 8192 + (_QRX) * 4)) /* _i=0...7, _QRX=0...2047 */ /* Reset Source: CORER */
 #define QRX_CONTEXT_MAX_INDEX			7
 #define QRX_CONTEXT_RXQ_CONTEXT_S		0
@@ -5561,7 +5183,7 @@
 #define VPLAN_TXQ_MAPENA_MAX_INDEX		255
 #define VPLAN_TXQ_MAPENA_TX_ENA_S		0
 #define VPLAN_TXQ_MAPENA_TX_ENA_M		BIT(0)
-#define VSILAN_QBASE(_VSI)			(0x0044c000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSILAN_QBASE(_VSI)			(0x0044C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
 #define VSILAN_QBASE_MAX_INDEX			767
 #define VSILAN_QBASE_VSIBASE_S			0
 #define VSILAN_QBASE_VSIBASE_M			MAKEMASK(0x7FF, 0)
@@ -5741,6 +5363,9 @@
 #define GL_MDET_TX_TCLAN_MAL_TYPE_M		MAKEMASK(0x1F, 26)
 #define GL_MDET_TX_TCLAN_VALID_S		31
 #define GL_MDET_TX_TCLAN_VALID_M		BIT(31)
+#define GLRLAN_MDET				0x00294200 /* Reset Source: CORER */
+#define GLRLAN_MDET_PCKT_EXTRCT_ERR_S		0
+#define GLRLAN_MDET_PCKT_EXTRCT_ERR_M		BIT(0)
 #define PF_MDET_RX				0x00294280 /* Reset Source: CORER */
 #define PF_MDET_RX_VALID_S			0
 #define PF_MDET_RX_VALID_M			BIT(0)
@@ -5783,9 +5408,9 @@
 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M	BIT(1)
 #define GL_MNG_FWSM				0x000B6134 /* Reset Source: POR */
 #define GL_MNG_FWSM_FW_MODES_S			0
-#define GL_MNG_FWSM_FW_MODES_M			MAKEMASK(0x3, 0)
-#define GL_MNG_FWSM_RSV0_S			2
-#define GL_MNG_FWSM_RSV0_M			MAKEMASK(0xFF, 2)
+#define GL_MNG_FWSM_FW_MODES_M			MAKEMASK(0x7, 0)
+#define GL_MNG_FWSM_RSV0_S			3
+#define GL_MNG_FWSM_RSV0_M			MAKEMASK(0x7F, 3)
 #define GL_MNG_FWSM_EEP_RELOAD_IND_S		10
 #define GL_MNG_FWSM_EEP_RELOAD_IND_M		BIT(10)
 #define GL_MNG_FWSM_RSV1_S			11
@@ -8561,7 +8186,7 @@
 #define EMP_SWT_PRUNIND_VSI_NUM_M		MAKEMASK(0x3FF, 16)
 #define EMP_SWT_PRUNIND_BIT_VALUE_S		31
 #define EMP_SWT_PRUNIND_BIT_VALUE_M		BIT(31)
-#define EMP_SWT_REPIND				0x0020401c /* Reset Source: CORER */
+#define EMP_SWT_REPIND				0x0020401C /* Reset Source: CORER */
 #define EMP_SWT_REPIND_OPCODE_S			0
 #define EMP_SWT_REPIND_OPCODE_M			MAKEMASK(0xF, 0)
 #define EMP_SWT_REPIND_LIST_INDEX_NUMBER_S	4
@@ -8570,7 +8195,7 @@
 #define EMP_SWT_REPIND_VSI_NUM_M		MAKEMASK(0x3FF, 16)
 #define EMP_SWT_REPIND_BIT_VALUE_S		31
 #define EMP_SWT_REPIND_BIT_VALUE_M		BIT(31)
-#define GL_OVERRIDEC				0x002040a4 /* Reset Source: CORER */
+#define GL_OVERRIDEC				0x002040A4 /* Reset Source: CORER */
 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_S	0
 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_M	MAKEMASK(0xFFFF, 0)
 #define GL_OVERRIDEC_LAST_VSI_S			16
@@ -8622,7 +8247,7 @@
 #define GL_SWT_LAT_SINGLE_BASE_M		MAKEMASK(0x7FF, 0)
 #define GL_SWT_LAT_SINGLE_SIZE_S		16
 #define GL_SWT_LAT_SINGLE_SIZE_M		MAKEMASK(0x7FF, 16)
-#define GL_SWT_MD_PRI				0x002040ac /* Reset Source: CORER */
+#define GL_SWT_MD_PRI				0x002040AC /* Reset Source: CORER */
 #define GL_SWT_MD_PRI_VSI_PRI_S			0
 #define GL_SWT_MD_PRI_VSI_PRI_M			MAKEMASK(0x7, 0)
 #define GL_SWT_MD_PRI_LB_PRI_S			4
@@ -8645,12 +8270,6 @@
 #define GL_SWT_MIRTARVSI_TARGETVSI_M		MAKEMASK(0x3FF, 20)
 #define GL_SWT_MIRTARVSI_RULEENABLE_S		31
 #define GL_SWT_MIRTARVSI_RULEENABLE_M		BIT(31)
-#define GL_SWT_NOMDEF_FLGS_H			0x0021411C /* Reset Source: CORER */
-#define GL_SWT_NOMDEF_FLGS_H_FLGS_S		0
-#define GL_SWT_NOMDEF_FLGS_H_FLGS_M		MAKEMASK(0xFFFFFFFF, 0)
-#define GL_SWT_NOMDEF_FLGS_L			0x00214118 /* Reset Source: CORER */
-#define GL_SWT_NOMDEF_FLGS_L_FLGS_S		0
-#define GL_SWT_NOMDEF_FLGS_L_FLGS_M		MAKEMASK(0xFFFFFFFF, 0)
 #define GL_SWT_SWIDFVIDX			0x00214114 /* Reset Source: CORER */
 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_S		0
 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_M		MAKEMASK(0x3F, 0)
@@ -8660,7 +8279,7 @@
 #define GL_VP_SWITCHID_MAX_INDEX		31
 #define GL_VP_SWITCHID_SWITCHID_S		0
 #define GL_VP_SWITCHID_SWITCHID_M		MAKEMASK(0xFF, 0)
-#define GLSWID_STAT_BLOCK(_i)			(0x0020A1A4 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
+#define GLSWID_STAT_BLOCK(_i)			(0x0020A1A4 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
 #define GLSWID_STAT_BLOCK_MAX_INDEX		255
 #define GLSWID_STAT_BLOCK_VEBID_S		0
 #define GLSWID_STAT_BLOCK_VEBID_M		MAKEMASK(0x1F, 0)
@@ -8710,10 +8329,10 @@
 #define PRT_SWT_MSCCNT				0x00204100 /* Reset Source: CORER */
 #define PRT_SWT_MSCCNT_CCOUNT_S			0
 #define PRT_SWT_MSCCNT_CCOUNT_M			MAKEMASK(0x1FFFFFF, 0)
-#define PRT_SWT_MSCTRH				0x002041c0 /* Reset Source: CORER */
+#define PRT_SWT_MSCTRH				0x002041C0 /* Reset Source: CORER */
 #define PRT_SWT_MSCTRH_UTRESH_S			0
 #define PRT_SWT_MSCTRH_UTRESH_M			MAKEMASK(0x7FFFF, 0)
-#define PRT_SWT_SCBI				0x002041e0 /* Reset Source: CORER */
+#define PRT_SWT_SCBI				0x002041E0 /* Reset Source: CORER */
 #define PRT_SWT_SCBI_BI_S			0
 #define PRT_SWT_SCBI_BI_M			MAKEMASK(0x1FFFFFF, 0)
 #define PRT_SWT_SCCRL				0x00204200 /* Reset Source: CORER */
@@ -8998,7 +8617,7 @@
 #define PFTSYN_SEM_BUSY_M			BIT(0)
 #define PFTSYN_SEM_PF_OWNER_S			4
 #define PFTSYN_SEM_PF_OWNER_M			MAKEMASK(0x7, 4)
-#define GLPE_TSCD_FLR(_i)			(0x0051E24c + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
+#define GLPE_TSCD_FLR(_i)			(0x0051E24C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
 #define GLPE_TSCD_FLR_MAX_INDEX			3
 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_S		0
 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_M		MAKEMASK(0x3, 0)
@@ -9043,7 +8662,7 @@
 #define PF_VT_PFALLOC_PCIE_LASTVF_M		MAKEMASK(0xFF, 8)
 #define PF_VT_PFALLOC_PCIE_VALID_S		31
 #define PF_VT_PFALLOC_PCIE_VALID_M		BIT(31)
-#define VSI_L2TAGSTXVALID(_VSI)			(0x00046000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_L2TAGSTXVALID(_VSI)			(0x00046000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_L2TAGSTXVALID_MAX_INDEX		767
 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_S	0
 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_M	MAKEMASK(0x7, 0)
@@ -9071,7 +8690,7 @@
 #define VSI_PASID_PASID_M			MAKEMASK(0xFFFFF, 0)
 #define VSI_PASID_EN_S				31
 #define VSI_PASID_EN_M				BIT(31)
-#define VSI_RUPR(_VSI)				(0x00050000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_RUPR(_VSI)				(0x00050000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_RUPR_MAX_INDEX			767
 #define VSI_RUPR_UP0_S				0
 #define VSI_RUPR_UP0_M				MAKEMASK(0x7, 0)
@@ -9089,7 +8708,7 @@
 #define VSI_RUPR_UP6_M				MAKEMASK(0x7, 18)
 #define VSI_RUPR_UP7_S				21
 #define VSI_RUPR_UP7_M				MAKEMASK(0x7, 21)
-#define VSI_RXSWCTRL(_VSI)			(0x00205000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_RXSWCTRL(_VSI)			(0x00205000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_RXSWCTRL_MAX_INDEX			767
 #define VSI_RXSWCTRL_MACVSIPRUNEENABLE_S	8
 #define VSI_RXSWCTRL_MACVSIPRUNEENABLE_M	BIT(8)
@@ -9097,7 +8716,7 @@
 #define VSI_RXSWCTRL_PRUNEENABLE_M		MAKEMASK(0xF, 9)
 #define VSI_RXSWCTRL_SRCPRUNEENABLE_S		13
 #define VSI_RXSWCTRL_SRCPRUNEENABLE_M		BIT(13)
-#define VSI_SRCSWCTRL(_VSI)			(0x00209000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_SRCSWCTRL(_VSI)			(0x00209000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_SRCSWCTRL_MAX_INDEX			767
 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_S	0
 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_M	BIT(0)
@@ -9129,25 +8748,25 @@
 #define VSI_TAIR_MAX_INDEX			767
 #define VSI_TAIR_PORT_TAG_ID_S			0
 #define VSI_TAIR_PORT_TAG_ID_M			MAKEMASK(0xFFFF, 0)
-#define VSI_TAR(_VSI)				(0x00045000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_TAR(_VSI)				(0x00045000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_TAR_MAX_INDEX			767
 #define VSI_TAR_ACCEPTTAGGED_S			0
 #define VSI_TAR_ACCEPTTAGGED_M			MAKEMASK(0x3FF, 0)
 #define VSI_TAR_ACCEPTUNTAGGED_S		16
 #define VSI_TAR_ACCEPTUNTAGGED_M		MAKEMASK(0x3FF, 16)
-#define VSI_TIR_0(_VSI)				(0x00041000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_TIR_0(_VSI)				(0x00041000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_TIR_0_MAX_INDEX			767
 #define VSI_TIR_0_PORT_TAG_ID_S			0
 #define VSI_TIR_0_PORT_TAG_ID_M			MAKEMASK(0xFFFF, 0)
-#define VSI_TIR_1(_VSI)				(0x00042000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_TIR_1(_VSI)				(0x00042000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_TIR_1_MAX_INDEX			767
 #define VSI_TIR_1_PORT_TAG_ID_S			0
 #define VSI_TIR_1_PORT_TAG_ID_M			MAKEMASK(0xFFFFFFFF, 0)
-#define VSI_TIR_2(_VSI)				(0x00043000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_TIR_2(_VSI)				(0x00043000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_TIR_2_MAX_INDEX			767
 #define VSI_TIR_2_PORT_TAG_ID_S			0
 #define VSI_TIR_2_PORT_TAG_ID_M			MAKEMASK(0xFFFF, 0)
-#define VSI_TSR(_VSI)				(0x00051000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_TSR(_VSI)				(0x00051000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_TSR_MAX_INDEX			767
 #define VSI_TSR_STRIPTAG_S			0
 #define VSI_TSR_STRIPTAG_M			MAKEMASK(0x3FF, 0)
@@ -9155,7 +8774,7 @@
 #define VSI_TSR_SHOWTAG_M			MAKEMASK(0x3FF, 10)
 #define VSI_TSR_SHOWPRIONLY_S			20
 #define VSI_TSR_SHOWPRIONLY_M			MAKEMASK(0x3FF, 20)
-#define VSI_TUPIOM(_VSI)			(0x00048000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_TUPIOM(_VSI)			(0x00048000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_TUPIOM_MAX_INDEX			767
 #define VSI_TUPIOM_UP0_S			0
 #define VSI_TUPIOM_UP0_M			MAKEMASK(0x7, 0)
@@ -9173,7 +8792,7 @@
 #define VSI_TUPIOM_UP6_M			MAKEMASK(0x7, 18)
 #define VSI_TUPIOM_UP7_S			21
 #define VSI_TUPIOM_UP7_M			MAKEMASK(0x7, 21)
-#define VSI_TUPR(_VSI)				(0x00047000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSI_TUPR(_VSI)				(0x00047000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSI_TUPR_MAX_INDEX			767
 #define VSI_TUPR_UP0_S				0
 #define VSI_TUPR_UP0_M				MAKEMASK(0x7, 0)
@@ -9205,27 +8824,13 @@
 #define VSI_VSI2F_VSI_NUMBER_M			MAKEMASK(0x3FF, 20)
 #define VSI_VSI2F_VSI_ENABLE_S			31
 #define VSI_VSI2F_VSI_ENABLE_M			BIT(31)
-#define VSI_VSI2F_MBX(_VSI)			(0x00232000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
-#define VSI_VSI2F_MBX_MAX_INDEX			767
-#define VSI_VSI2F_MBX_VFVMNUMBER_S		0
-#define VSI_VSI2F_MBX_VFVMNUMBER_M		MAKEMASK(0x3FF, 0)
-#define VSI_VSI2F_MBX_FUNCTIONTYPE_S		10
-#define VSI_VSI2F_MBX_FUNCTIONTYPE_M		MAKEMASK(0x3, 10)
-#define VSI_VSI2F_MBX_PFNUMBER_S		12
-#define VSI_VSI2F_MBX_PFNUMBER_M		MAKEMASK(0x7, 12)
-#define VSI_VSI2F_MBX_BUFFERNUMBER_S		16
-#define VSI_VSI2F_MBX_BUFFERNUMBER_M		MAKEMASK(0x7, 16)
-#define VSI_VSI2F_MBX_VSI_NUMBER_S		20
-#define VSI_VSI2F_MBX_VSI_NUMBER_M		MAKEMASK(0x3FF, 20)
-#define VSI_VSI2F_MBX_VSI_ENABLE_S		31
-#define VSI_VSI2F_MBX_VSI_ENABLE_M		BIT(31)
 #define VSIQF_FD_CNT(_VSI)			(0x00464000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
 #define VSIQF_FD_CNT_MAX_INDEX			767
 #define VSIQF_FD_CNT_FD_GCNT_S			0
 #define VSIQF_FD_CNT_FD_GCNT_M			MAKEMASK(0x3FFF, 0)
 #define VSIQF_FD_CNT_FD_BCNT_S			16
 #define VSIQF_FD_CNT_FD_BCNT_M			MAKEMASK(0x3FFF, 16)
-#define VSIQF_FD_CTL1(_VSI)			(0x00411000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSIQF_FD_CTL1(_VSI)			(0x00411000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSIQF_FD_CTL1_MAX_INDEX			767
 #define VSIQF_FD_CTL1_FLT_ENA_S			0
 #define VSIQF_FD_CTL1_FLT_ENA_M			BIT(0)
@@ -9233,7 +8838,7 @@
 #define VSIQF_FD_CTL1_CFG_ENA_M			BIT(1)
 #define VSIQF_FD_CTL1_EVICT_ENA_S		2
 #define VSIQF_FD_CTL1_EVICT_ENA_M		BIT(2)
-#define VSIQF_FD_DFLT(_VSI)			(0x00457000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSIQF_FD_DFLT(_VSI)			(0x00457000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSIQF_FD_DFLT_MAX_INDEX			767
 #define VSIQF_FD_DFLT_DEFLT_QINDX_S		0
 #define VSIQF_FD_DFLT_DEFLT_QINDX_M		MAKEMASK(0x7FF, 0)
@@ -9251,7 +8856,7 @@
 #define VSIQF_FD_SIZE_FD_GSIZE_M		MAKEMASK(0x3FFF, 0)
 #define VSIQF_FD_SIZE_FD_BSIZE_S		16
 #define VSIQF_FD_SIZE_FD_BSIZE_M		MAKEMASK(0x3FFF, 16)
-#define VSIQF_HASH_CTL(_VSI)			(0x0040D000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSIQF_HASH_CTL(_VSI)			(0x0040D000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSIQF_HASH_CTL_MAX_INDEX		767
 #define VSIQF_HASH_CTL_HASH_LUT_SEL_S		0
 #define VSIQF_HASH_CTL_HASH_LUT_SEL_M		MAKEMASK(0x3, 0)
@@ -9283,11 +8888,11 @@
 #define VSIQF_HLUT_LUT2_M			MAKEMASK(0xF, 16)
 #define VSIQF_HLUT_LUT3_S			24
 #define VSIQF_HLUT_LUT3_M			MAKEMASK(0xF, 24)
-#define VSIQF_PE_CTL1(_VSI)			(0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define VSIQF_PE_CTL1(_VSI)			(0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
 #define VSIQF_PE_CTL1_MAX_INDEX			767
 #define VSIQF_PE_CTL1_PE_FLTENA_S		0
 #define VSIQF_PE_CTL1_PE_FLTENA_M		BIT(0)
-#define VSIQF_TC_REGION(_i, _VSI)		(0x00448000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...3, _VSI=0...767 */ /* Reset Source: PFR */
+#define VSIQF_TC_REGION(_i, _VSI)		(0x00448000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...3, _VSI=0...767 */ /* Reset Source: CORER */
 #define VSIQF_TC_REGION_MAX_INDEX		3
 #define VSIQF_TC_REGION_TC_BASE0_S		0
 #define VSIQF_TC_REGION_TC_BASE0_M		MAKEMASK(0x7FF, 0)
@@ -9414,7 +9019,7 @@
 #define VF_MBX_ARQH1				0x00007400 /* Reset Source: CORER */
 #define VF_MBX_ARQH1_ARQH_S			0
 #define VF_MBX_ARQH1_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_ARQLEN1				0x00008000 /* Reset Source: CORER */
+#define VF_MBX_ARQLEN1				0x00008000 /* Reset Source: PFR */
 #define VF_MBX_ARQLEN1_ARQLEN_S			0
 #define VF_MBX_ARQLEN1_ARQLEN_M			MAKEMASK(0x3FF, 0)
 #define VF_MBX_ARQLEN1_ARQVFE_S			28
@@ -9437,7 +9042,7 @@
 #define VF_MBX_ATQH1				0x00006400 /* Reset Source: CORER */
 #define VF_MBX_ATQH1_ATQH_S			0
 #define VF_MBX_ATQH1_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_ATQLEN1				0x00006800 /* Reset Source: CORER */
+#define VF_MBX_ATQLEN1				0x00006800 /* Reset Source: PFR */
 #define VF_MBX_ATQLEN1_ATQLEN_S			0
 #define VF_MBX_ATQLEN1_ATQLEN_M			MAKEMASK(0x3FF, 0)
 #define VF_MBX_ATQLEN1_ATQVFE_S			28
@@ -9457,7 +9062,7 @@
 #define VFGEN_RSTAT1				0x00008800 /* Reset Source: VFR */
 #define VFGEN_RSTAT1_VFR_STATE_S		0
 #define VFGEN_RSTAT1_VFR_STATE_M		MAKEMASK(0x3, 0)
-#define VFINT_DYN_CTL0				0x00005C00 /* Reset Source: PFR */
+#define VFINT_DYN_CTL0				0x00005C00 /* Reset Source: CORER */
 #define VFINT_DYN_CTL0_INTENA_S			0
 #define VFINT_DYN_CTL0_INTENA_M			BIT(0)
 #define VFINT_DYN_CTL0_CLEARPBA_S		1
@@ -9476,7 +9081,7 @@
 #define VFINT_DYN_CTL0_WB_ON_ITR_M		BIT(30)
 #define VFINT_DYN_CTL0_INTENA_MSK_S		31
 #define VFINT_DYN_CTL0_INTENA_MSK_M		BIT(31)
-#define VFINT_DYN_CTLN(_i)			(0x00003800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: PFR */
+#define VFINT_DYN_CTLN(_i)			(0x00003800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
 #define VFINT_DYN_CTLN_MAX_INDEX		63
 #define VFINT_DYN_CTLN_INTENA_S			0
 #define VFINT_DYN_CTLN_INTENA_M			BIT(0)
@@ -9496,11 +9101,11 @@
 #define VFINT_DYN_CTLN_WB_ON_ITR_M		BIT(30)
 #define VFINT_DYN_CTLN_INTENA_MSK_S		31
 #define VFINT_DYN_CTLN_INTENA_MSK_M		BIT(31)
-#define VFINT_ITR0(_i)				(0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: PFR */
+#define VFINT_ITR0(_i)				(0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
 #define VFINT_ITR0_MAX_INDEX			2
 #define VFINT_ITR0_INTERVAL_S			0
 #define VFINT_ITR0_INTERVAL_M			MAKEMASK(0xFFF, 0)
-#define VFINT_ITRN(_i, _j)			(0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: PFR */
+#define VFINT_ITRN(_i, _j)			(0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: CORER */
 #define VFINT_ITRN_MAX_INDEX			2
 #define VFINT_ITRN_INTERVAL_S			0
 #define VFINT_ITRN_INTERVAL_M			MAKEMASK(0xFFF, 0)
@@ -9512,69 +9117,6 @@
 #define QTX_TAIL_MAX_INDEX			255
 #define QTX_TAIL_QTX_COMM_DBELL_S		0
 #define QTX_TAIL_QTX_COMM_DBELL_M		MAKEMASK(0xFFFFFFFF, 0)
-#define MSIX_TMSG1(_i)				(0x00000008 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
-#define MSIX_TMSG1_MAX_INDEX			64
-#define MSIX_TMSG1_MSIXTMSG_S			0
-#define MSIX_TMSG1_MSIXTMSG_M			MAKEMASK(0xFFFFFFFF, 0)
-#define VFPE_AEQALLOC1				0x0000A400 /* Reset Source: VFR */
-#define VFPE_AEQALLOC1_AECOUNT_S		0
-#define VFPE_AEQALLOC1_AECOUNT_M		MAKEMASK(0xFFFFFFFF, 0)
-#define VFPE_CCQPHIGH1				0x00009800 /* Reset Source: VFR */
-#define VFPE_CCQPHIGH1_PECCQPHIGH_S		0
-#define VFPE_CCQPHIGH1_PECCQPHIGH_M		MAKEMASK(0xFFFFFFFF, 0)
-#define VFPE_CCQPLOW1				0x0000AC00 /* Reset Source: VFR */
-#define VFPE_CCQPLOW1_PECCQPLOW_S		0
-#define VFPE_CCQPLOW1_PECCQPLOW_M		MAKEMASK(0xFFFFFFFF, 0)
-#define VFPE_CCQPSTATUS1			0x0000B800 /* Reset Source: VFR */
-#define VFPE_CCQPSTATUS1_CCQP_DONE_S		0
-#define VFPE_CCQPSTATUS1_CCQP_DONE_M		BIT(0)
-#define VFPE_CCQPSTATUS1_HMC_PROFILE_S		4
-#define VFPE_CCQPSTATUS1_HMC_PROFILE_M		MAKEMASK(0x7, 4)
-#define VFPE_CCQPSTATUS1_RDMA_EN_VFS_S		16
-#define VFPE_CCQPSTATUS1_RDMA_EN_VFS_M		MAKEMASK(0x3F, 16)
-#define VFPE_CCQPSTATUS1_CCQP_ERR_S		31
-#define VFPE_CCQPSTATUS1_CCQP_ERR_M		BIT(31)
-#define VFPE_CQACK1				0x0000B000 /* Reset Source: VFR */
-#define VFPE_CQACK1_PECQID_S			0
-#define VFPE_CQACK1_PECQID_M			MAKEMASK(0x7FFFF, 0)
-#define VFPE_CQARM1				0x0000B400 /* Reset Source: VFR */
-#define VFPE_CQARM1_PECQID_S			0
-#define VFPE_CQARM1_PECQID_M			MAKEMASK(0x7FFFF, 0)
-#define VFPE_CQPDB1				0x0000BC00 /* Reset Source: VFR */
-#define VFPE_CQPDB1_WQHEAD_S			0
-#define VFPE_CQPDB1_WQHEAD_M			MAKEMASK(0x7FF, 0)
-#define VFPE_CQPERRCODES1			0x00009C00 /* Reset Source: VFR */
-#define VFPE_CQPERRCODES1_CQP_MINOR_CODE_S	0
-#define VFPE_CQPERRCODES1_CQP_MINOR_CODE_M	MAKEMASK(0xFFFF, 0)
-#define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_S	16
-#define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_M	MAKEMASK(0xFFFF, 16)
-#define VFPE_CQPTAIL1				0x0000A000 /* Reset Source: VFR */
-#define VFPE_CQPTAIL1_WQTAIL_S			0
-#define VFPE_CQPTAIL1_WQTAIL_M			MAKEMASK(0x7FF, 0)
-#define VFPE_CQPTAIL1_CQP_OP_ERR_S		31
-#define VFPE_CQPTAIL1_CQP_OP_ERR_M		BIT(31)
-#define VFPE_IPCONFIG01				0x00008C00 /* Reset Source: VFR */
-#define VFPE_IPCONFIG01_PEIPID_S		0
-#define VFPE_IPCONFIG01_PEIPID_M		MAKEMASK(0xFFFF, 0)
-#define VFPE_IPCONFIG01_USEENTIREIDRANGE_S	16
-#define VFPE_IPCONFIG01_USEENTIREIDRANGE_M	BIT(16)
-#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_S	17
-#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_M	BIT(17)
-#define VFPE_MRTEIDXMASK1(_VF)			(0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
-#define VFPE_MRTEIDXMASK1_MAX_INDEX		255
-#define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S	0
-#define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M	MAKEMASK(0x1F, 0)
-#define VFPE_RCVUNEXPECTEDERROR1		0x00009400 /* Reset Source: VFR */
-#define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0
-#define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
-#define VFPE_TCPNOWTIMER1			0x0000A800 /* Reset Source: VFR */
-#define VFPE_TCPNOWTIMER1_TCP_NOW_S		0
-#define VFPE_TCPNOWTIMER1_TCP_NOW_M		MAKEMASK(0xFFFFFFFF, 0)
-#define VFPE_WQEALLOC1				0x0000C000 /* Reset Source: VFR */
-#define VFPE_WQEALLOC1_PEQPID_S			0
-#define VFPE_WQEALLOC1_PEQPID_M			MAKEMASK(0x3FFFF, 0)
-#define VFPE_WQEALLOC1_WQE_DESC_INDEX_S		20
-#define VFPE_WQEALLOC1_WQE_DESC_INDEX_M		MAKEMASK(0xFFF, 20)
 #define VF_MBX_CPM_ARQBAH1			0x0000F060 /* Reset Source: CORER */
 #define VF_MBX_CPM_ARQBAH1_ARQBAH_S		0
 #define VF_MBX_CPM_ARQBAH1_ARQBAH_M		MAKEMASK(0xFFFFFFFF, 0)
@@ -9586,7 +9128,7 @@
 #define VF_MBX_CPM_ARQH1			0x0000F080 /* Reset Source: CORER */
 #define VF_MBX_CPM_ARQH1_ARQH_S			0
 #define VF_MBX_CPM_ARQH1_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_CPM_ARQLEN1			0x0000F070 /* Reset Source: CORER */
+#define VF_MBX_CPM_ARQLEN1			0x0000F070 /* Reset Source: PFR */
 #define VF_MBX_CPM_ARQLEN1_ARQLEN_S		0
 #define VF_MBX_CPM_ARQLEN1_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define VF_MBX_CPM_ARQLEN1_ARQVFE_S		28
@@ -9609,7 +9151,7 @@
 #define VF_MBX_CPM_ATQH1			0x0000F030 /* Reset Source: CORER */
 #define VF_MBX_CPM_ATQH1_ATQH_S			0
 #define VF_MBX_CPM_ATQH1_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_CPM_ATQLEN1			0x0000F020 /* Reset Source: CORER */
+#define VF_MBX_CPM_ATQLEN1			0x0000F020 /* Reset Source: PFR */
 #define VF_MBX_CPM_ATQLEN1_ATQLEN_S		0
 #define VF_MBX_CPM_ATQLEN1_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define VF_MBX_CPM_ATQLEN1_ATQVFE_S		28
@@ -9634,7 +9176,7 @@
 #define VF_MBX_HLP_ARQH1			0x00020080 /* Reset Source: CORER */
 #define VF_MBX_HLP_ARQH1_ARQH_S			0
 #define VF_MBX_HLP_ARQH1_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_HLP_ARQLEN1			0x00020070 /* Reset Source: CORER */
+#define VF_MBX_HLP_ARQLEN1			0x00020070 /* Reset Source: PFR */
 #define VF_MBX_HLP_ARQLEN1_ARQLEN_S		0
 #define VF_MBX_HLP_ARQLEN1_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define VF_MBX_HLP_ARQLEN1_ARQVFE_S		28
@@ -9657,7 +9199,7 @@
 #define VF_MBX_HLP_ATQH1			0x00020030 /* Reset Source: CORER */
 #define VF_MBX_HLP_ATQH1_ATQH_S			0
 #define VF_MBX_HLP_ATQH1_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_HLP_ATQLEN1			0x00020020 /* Reset Source: CORER */
+#define VF_MBX_HLP_ATQLEN1			0x00020020 /* Reset Source: PFR */
 #define VF_MBX_HLP_ATQLEN1_ATQLEN_S		0
 #define VF_MBX_HLP_ATQLEN1_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define VF_MBX_HLP_ATQLEN1_ATQVFE_S		28
@@ -9682,7 +9224,7 @@
 #define VF_MBX_PSM_ARQH1			0x00021080 /* Reset Source: CORER */
 #define VF_MBX_PSM_ARQH1_ARQH_S			0
 #define VF_MBX_PSM_ARQH1_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_PSM_ARQLEN1			0x00021070 /* Reset Source: CORER */
+#define VF_MBX_PSM_ARQLEN1			0x00021070 /* Reset Source: PFR */
 #define VF_MBX_PSM_ARQLEN1_ARQLEN_S		0
 #define VF_MBX_PSM_ARQLEN1_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define VF_MBX_PSM_ARQLEN1_ARQVFE_S		28
@@ -9705,7 +9247,7 @@
 #define VF_MBX_PSM_ATQH1			0x00021030 /* Reset Source: CORER */
 #define VF_MBX_PSM_ATQH1_ATQH_S			0
 #define VF_MBX_PSM_ATQH1_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_MBX_PSM_ATQLEN1			0x00021020 /* Reset Source: CORER */
+#define VF_MBX_PSM_ATQLEN1			0x00021020 /* Reset Source: PFR */
 #define VF_MBX_PSM_ATQLEN1_ATQLEN_S		0
 #define VF_MBX_PSM_ATQLEN1_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define VF_MBX_PSM_ATQLEN1_ATQVFE_S		28
@@ -9730,7 +9272,7 @@
 #define VF_SB_CPM_ARQH1				0x0000F180 /* Reset Source: CORER */
 #define VF_SB_CPM_ARQH1_ARQH_S			0
 #define VF_SB_CPM_ARQH1_ARQH_M			MAKEMASK(0x3FF, 0)
-#define VF_SB_CPM_ARQLEN1			0x0000F170 /* Reset Source: CORER */
+#define VF_SB_CPM_ARQLEN1			0x0000F170 /* Reset Source: PFR */
 #define VF_SB_CPM_ARQLEN1_ARQLEN_S		0
 #define VF_SB_CPM_ARQLEN1_ARQLEN_M		MAKEMASK(0x3FF, 0)
 #define VF_SB_CPM_ARQLEN1_ARQVFE_S		28
@@ -9753,7 +9295,7 @@
 #define VF_SB_CPM_ATQH1				0x0000F130 /* Reset Source: CORER */
 #define VF_SB_CPM_ATQH1_ATQH_S			0
 #define VF_SB_CPM_ATQH1_ATQH_M			MAKEMASK(0x3FF, 0)
-#define VF_SB_CPM_ATQLEN1			0x0000F120 /* Reset Source: CORER */
+#define VF_SB_CPM_ATQLEN1			0x0000F120 /* Reset Source: PFR */
 #define VF_SB_CPM_ATQLEN1_ATQLEN_S		0
 #define VF_SB_CPM_ATQLEN1_ATQLEN_M		MAKEMASK(0x3FF, 0)
 #define VF_SB_CPM_ATQLEN1_ATQVFE_S		28
@@ -9767,7 +9309,7 @@
 #define VF_SB_CPM_ATQT1				0x0000F140 /* Reset Source: CORER */
 #define VF_SB_CPM_ATQT1_ATQT_S			0
 #define VF_SB_CPM_ATQT1_ATQT_M			MAKEMASK(0x3FF, 0)
-#define VFINT_DYN_CTL(_i)			(0x00023000 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: PFR */
+#define VFINT_DYN_CTL(_i)			(0x00023000 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
 #define VFINT_DYN_CTL_MAX_INDEX			7
 #define VFINT_DYN_CTL_INTENA_S			0
 #define VFINT_DYN_CTL_INTENA_M			BIT(0)
@@ -9787,15 +9329,15 @@
 #define VFINT_DYN_CTL_WB_ON_ITR_M		BIT(30)
 #define VFINT_DYN_CTL_INTENA_MSK_S		31
 #define VFINT_DYN_CTL_INTENA_MSK_M		BIT(31)
-#define VFINT_ITR_0(_i)				(0x00023004 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: PFR */
+#define VFINT_ITR_0(_i)				(0x00023004 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
 #define VFINT_ITR_0_MAX_INDEX			7
 #define VFINT_ITR_0_INTERVAL_S			0
 #define VFINT_ITR_0_INTERVAL_M			MAKEMASK(0xFFF, 0)
-#define VFINT_ITR_1(_i)				(0x00023008 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: PFR */
+#define VFINT_ITR_1(_i)				(0x00023008 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
 #define VFINT_ITR_1_MAX_INDEX			7
 #define VFINT_ITR_1_INTERVAL_S			0
 #define VFINT_ITR_1_INTERVAL_M			MAKEMASK(0xFFF, 0)
-#define VFINT_ITR_2(_i)				(0x0002300C + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: PFR */
+#define VFINT_ITR_2(_i)				(0x0002300C + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
 #define VFINT_ITR_2_MAX_INDEX			7
 #define VFINT_ITR_2_INTERVAL_S			0
 #define VFINT_ITR_2_INTERVAL_M			MAKEMASK(0xFFF, 0)
@@ -9811,5 +9353,68 @@
 #define VFQTX_COMM_DBLQ_DBELL_MAX_INDEX		3
 #define VFQTX_COMM_DBLQ_DBELL_TAIL_S		0
 #define VFQTX_COMM_DBLQ_DBELL_TAIL_M		MAKEMASK(0x1FFF, 0)
+#define MSIX_TMSG1(_i)				(0x00000008 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
+#define MSIX_TMSG1_MAX_INDEX			64
+#define MSIX_TMSG1_MSIXTMSG_S			0
+#define MSIX_TMSG1_MSIXTMSG_M			MAKEMASK(0xFFFFFFFF, 0)
+#define VFPE_AEQALLOC1				0x0000A400 /* Reset Source: VFR */
+#define VFPE_AEQALLOC1_AECOUNT_S		0
+#define VFPE_AEQALLOC1_AECOUNT_M		MAKEMASK(0xFFFFFFFF, 0)
+#define VFPE_CCQPHIGH1				0x00009800 /* Reset Source: VFR */
+#define VFPE_CCQPHIGH1_PECCQPHIGH_S		0
+#define VFPE_CCQPHIGH1_PECCQPHIGH_M		MAKEMASK(0xFFFFFFFF, 0)
+#define VFPE_CCQPLOW1				0x0000AC00 /* Reset Source: VFR */
+#define VFPE_CCQPLOW1_PECCQPLOW_S		0
+#define VFPE_CCQPLOW1_PECCQPLOW_M		MAKEMASK(0xFFFFFFFF, 0)
+#define VFPE_CCQPSTATUS1			0x0000B800 /* Reset Source: VFR */
+#define VFPE_CCQPSTATUS1_CCQP_DONE_S		0
+#define VFPE_CCQPSTATUS1_CCQP_DONE_M		BIT(0)
+#define VFPE_CCQPSTATUS1_HMC_PROFILE_S		4
+#define VFPE_CCQPSTATUS1_HMC_PROFILE_M		MAKEMASK(0x7, 4)
+#define VFPE_CCQPSTATUS1_RDMA_EN_VFS_S		16
+#define VFPE_CCQPSTATUS1_RDMA_EN_VFS_M		MAKEMASK(0x3F, 16)
+#define VFPE_CCQPSTATUS1_CCQP_ERR_S		31
+#define VFPE_CCQPSTATUS1_CCQP_ERR_M		BIT(31)
+#define VFPE_CQACK1				0x0000B000 /* Reset Source: VFR */
+#define VFPE_CQACK1_PECQID_S			0
+#define VFPE_CQACK1_PECQID_M			MAKEMASK(0x7FFFF, 0)
+#define VFPE_CQARM1				0x0000B400 /* Reset Source: VFR */
+#define VFPE_CQARM1_PECQID_S			0
+#define VFPE_CQARM1_PECQID_M			MAKEMASK(0x7FFFF, 0)
+#define VFPE_CQPDB1				0x0000BC00 /* Reset Source: VFR */
+#define VFPE_CQPDB1_WQHEAD_S			0
+#define VFPE_CQPDB1_WQHEAD_M			MAKEMASK(0x7FF, 0)
+#define VFPE_CQPERRCODES1			0x00009C00 /* Reset Source: VFR */
+#define VFPE_CQPERRCODES1_CQP_MINOR_CODE_S	0
+#define VFPE_CQPERRCODES1_CQP_MINOR_CODE_M	MAKEMASK(0xFFFF, 0)
+#define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_S	16
+#define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_M	MAKEMASK(0xFFFF, 16)
+#define VFPE_CQPTAIL1				0x0000A000 /* Reset Source: VFR */
+#define VFPE_CQPTAIL1_WQTAIL_S			0
+#define VFPE_CQPTAIL1_WQTAIL_M			MAKEMASK(0x7FF, 0)
+#define VFPE_CQPTAIL1_CQP_OP_ERR_S		31
+#define VFPE_CQPTAIL1_CQP_OP_ERR_M		BIT(31)
+#define VFPE_IPCONFIG01				0x00008C00 /* Reset Source: VFR */
+#define VFPE_IPCONFIG01_PEIPID_S		0
+#define VFPE_IPCONFIG01_PEIPID_M		MAKEMASK(0xFFFF, 0)
+#define VFPE_IPCONFIG01_USEENTIREIDRANGE_S	16
+#define VFPE_IPCONFIG01_USEENTIREIDRANGE_M	BIT(16)
+#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_S	17
+#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_M	BIT(17)
+#define VFPE_MRTEIDXMASK1(_VF)			(0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
+#define VFPE_MRTEIDXMASK1_MAX_INDEX		255
+#define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S	0
+#define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M	MAKEMASK(0x1F, 0)
+#define VFPE_RCVUNEXPECTEDERROR1		0x00009400 /* Reset Source: VFR */
+#define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0
+#define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
+#define VFPE_TCPNOWTIMER1			0x0000A800 /* Reset Source: VFR */
+#define VFPE_TCPNOWTIMER1_TCP_NOW_S		0
+#define VFPE_TCPNOWTIMER1_TCP_NOW_M		MAKEMASK(0xFFFFFFFF, 0)
+#define VFPE_WQEALLOC1				0x0000C000 /* Reset Source: VFR */
+#define VFPE_WQEALLOC1_PEQPID_S			0
+#define VFPE_WQEALLOC1_PEQPID_M			MAKEMASK(0x3FFFF, 0)
+#define VFPE_WQEALLOC1_WQE_DESC_INDEX_S		20
+#define VFPE_WQEALLOC1_WQE_DESC_INDEX_M		MAKEMASK(0xFFF, 20)
 
 #endif
