From patchwork Fri Jun 28 18:23:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 55612 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D00531B996; Fri, 28 Jun 2019 20:24:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A49681B952 for ; Fri, 28 Jun 2019 20:24:15 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5SIMM3m012139; Fri, 28 Jun 2019 11:24:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=8oEf/C/4SuAfjbvCHSz+1XITJSqJN/oovviYwip9lL4=; b=axzZqrj2yOaJGkH48JrUrVqAjBepAshfUxyhf3U1e3SOAOmIKEdMzFxuusW5GUZ+qy3b Q/FJTcvwMKXL9cWvrzI0mncKsk0undVxhZXLuLzKDXcG7P3XAtz2/5uVNd98ID0NU6UQ ims4BcroBR5Tl7idIwocfNmPLrXFBSAkTfVVKDkjM8Fjhe/UcI9TffkE0bWXLCpXZrS7 suRdd8EvR5C4AefFLt8CT1gpQ8SZ+8C0miO68AOee+gVPR7bTCurzuBCcy8dzweZ7Rbt apR7RL+HYodFkFTapWR3XTSWhjGvuQN0uah77ztHopi2zPauGY8qxKDdxhpWNAEeiqnQ XA== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agj0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2019 11:24:14 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 28 Jun 2019 11:24:13 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 28 Jun 2019 11:24:13 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.12]) by maili.marvell.com (Postfix) with ESMTP id 18B983F7041; Fri, 28 Jun 2019 11:24:11 -0700 (PDT) From: To: , Pavan Nikhilesh , "John McNamara" , Marko Kovacevic CC: Date: Fri, 28 Jun 2019 23:53:18 +0530 Message-ID: <20190628182354.228-8-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628182354.228-1-pbhagavatula@marvell.com> References: <20190628182354.228-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-28_08:, , signatures=0 Subject: [dpdk-dev] [PATCH v3 07/42] event/octeontx2: add devargs for inflight buffer count X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh The number of events for a *open system* event device is specified as -1 as per the eventdev specification. Since, Octeontx2 SSO inflight events are only limited by DRAM size, the xae_cnt devargs parameter is introduced to provide upper limit for in-flight events. Example: --dev "0002:0e:00.0,xae_cnt=8192" Signed-off-by: Pavan Nikhilesh Acked-by: Jerin Jacob --- doc/guides/eventdevs/octeontx2.rst | 12 ++++++++++++ drivers/event/octeontx2/Makefile | 2 +- drivers/event/octeontx2/otx2_evdev.c | 28 +++++++++++++++++++++++++++- drivers/event/octeontx2/otx2_evdev.h | 11 +++++++++++ 4 files changed, 51 insertions(+), 2 deletions(-) diff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst index 341c5b21d..f83cf1e9d 100644 --- a/doc/guides/eventdevs/octeontx2.rst +++ b/doc/guides/eventdevs/octeontx2.rst @@ -46,6 +46,18 @@ The following option can be modified in the ``config`` file. Toggle compilation of the ``librte_pmd_octeontx2_event`` driver. +Runtime Config Options +~~~~~~~~~~~~~~~~~~~~~~ + +- ``Maximum number of in-flight events`` (default ``8192``) + + In **Marvell OCTEON TX2** the max number of in-flight events are only limited + by DRAM size, the ``xae_cnt`` devargs parameter is introduced to provide + upper limit for in-flight events. + For example:: + + --dev "0002:0e:00.0,xae_cnt=16384" + Debugging Options ~~~~~~~~~~~~~~~~~ diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile index b3c3beccb..58853e1b9 100644 --- a/drivers/event/octeontx2/Makefile +++ b/drivers/event/octeontx2/Makefile @@ -32,7 +32,7 @@ LIBABIVER := 1 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c -LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci +LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci -lrte_kvargs LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2 diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index fc4dbda0a..94c97fc9e 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -245,7 +246,10 @@ sso_xaq_allocate(struct otx2_sso_evdev *dev) /* Taken from HRM 14.3.3(4) */ xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT; - xaq_cnt += (dev->iue / dev->xae_waes) + + if (dev->xae_cnt) + xaq_cnt += dev->xae_cnt / dev->xae_waes; + else + xaq_cnt += (dev->iue / dev->xae_waes) + (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues); otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt); @@ -464,6 +468,25 @@ static struct rte_eventdev_ops otx2_sso_ops = { .queue_release = otx2_sso_queue_release, }; +#define OTX2_SSO_XAE_CNT "xae_cnt" + +static void +sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs) +{ + struct rte_kvargs *kvlist; + + if (devargs == NULL) + return; + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) + return; + + rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value, + &dev->xae_cnt); + + rte_kvargs_free(kvlist); +} + static int otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) { @@ -553,6 +576,8 @@ otx2_sso_init(struct rte_eventdev *event_dev) goto otx2_npa_lf_uninit; } + sso_parse_devargs(dev, pci_dev->device.devargs); + otx2_sso_pf_func_set(dev->pf_func); otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d", event_dev->data->name, dev->max_event_queues, @@ -601,3 +626,4 @@ otx2_sso_fini(struct rte_eventdev *event_dev) RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "="); diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 375640bca..acc8b6b3e 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -62,6 +62,8 @@ struct otx2_sso_evdev { uint64_t nb_xaq_cfg; rte_iova_t fc_iova; struct rte_mempool *xaq_pool; + /* Dev args */ + uint32_t xae_cnt; /* HW const */ uint32_t xae_waes; uint32_t xaq_buf_size; @@ -74,6 +76,15 @@ sso_pmd_priv(const struct rte_eventdev *event_dev) return event_dev->data->dev_private; } +static inline int +parse_kvargs_value(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + *(uint32_t *)opaque = (uint32_t)atoi(value); + return 0; +} + /* Init and Fini API's */ int otx2_sso_init(struct rte_eventdev *event_dev); int otx2_sso_fini(struct rte_eventdev *event_dev);