From patchwork Fri Jun 28 18:23:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 55614 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4B4665B34; Fri, 28 Jun 2019 20:24:31 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 59C4B1B952 for ; Fri, 28 Jun 2019 20:24:20 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5SILBYl011342 for ; Fri, 28 Jun 2019 11:24:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=ZoSLcc9zIitQGS/1B1rMShfsy044h9up2LKYtmenP/s=; b=yQVlQC+keTMr6Gs4Aiyif6Cs96ZMfVaT/KWJX0HZ2wSivb6lX54Q4Cf9xBL5sdJmIgvE JDXOM6nToKXM/EbKgAbMH7RzgP1BGWyqH34YlpPoCMrdgVkPngGX8e+W9mitdu8NTESr +sWqQD5hAH5k8NDzLnu77Yb4zqo7rUOK3nlmMzKmvbVLkf3cuE2C1NyqfKAuH+Y1fytJ DdhoPaTqLy+wbpgLIzFSW3hfcWwP0LcnkRFuFh7+8sePkTDxMM8/P8/rtaCjzB0jHcBe /m8rNcLZgzLavWwgOWDcN+08bWHr9F7B+gtoAKnKsa/Wiy43BLp8U6dtIqyUet4SeT1t TQ== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agjg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 28 Jun 2019 11:24:19 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 28 Jun 2019 11:24:18 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 28 Jun 2019 11:24:18 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.12]) by maili.marvell.com (Postfix) with ESMTP id 3643E3F7041; Fri, 28 Jun 2019 11:24:16 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Fri, 28 Jun 2019 23:53:20 +0530 Message-ID: <20190628182354.228-10-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628182354.228-1-pbhagavatula@marvell.com> References: <20190628182354.228-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-28_08:, , signatures=0 Subject: [dpdk-dev] [PATCH v3 09/42] event/octeontx2: support linking queues to ports X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Links between queues and ports are controlled by setting/clearing GGRP membership in SSOW_LF_GWS_GRPMSK_CHG. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev.c | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index a6bf861fb..53e68902a 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -39,6 +39,60 @@ otx2_sso_info_get(struct rte_eventdev *event_dev, RTE_EVENT_DEV_CAP_NONSEQ_MODE; } +static void +sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable) +{ + uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op); + uint64_t val; + + val = queue; + val |= 0ULL << 12; /* SET 0 */ + val |= 0x8000800080000000; /* Dont modify rest of the masks */ + val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */ + + otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG); +} + +static int +otx2_sso_port_link(struct rte_eventdev *event_dev, void *port, + const uint8_t queues[], const uint8_t priorities[], + uint16_t nb_links) +{ + uint8_t port_id = 0; + uint16_t link; + + RTE_SET_USED(event_dev); + RTE_SET_USED(priorities); + for (link = 0; link < nb_links; link++) { + struct otx2_ssogws *ws = port; + + port_id = ws->port; + sso_port_link_modify(ws, queues[link], true); + } + sso_func_trace("Port=%d nb_links=%d", port_id, nb_links); + + return (int)nb_links; +} + +static int +otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port, + uint8_t queues[], uint16_t nb_unlinks) +{ + uint8_t port_id = 0; + uint16_t unlink; + + RTE_SET_USED(event_dev); + for (unlink = 0; unlink < nb_unlinks; unlink++) { + struct otx2_ssogws *ws = port; + + port_id = ws->port; + sso_port_link_modify(ws, queues[unlink], false); + } + sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks); + + return (int)nb_unlinks; +} + static int sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t attach) @@ -157,6 +211,21 @@ otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id) RTE_SET_USED(queue_id); } +static void +sso_clr_links(const struct rte_eventdev *event_dev) +{ + struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev); + int i, j; + + for (i = 0; i < dev->nb_event_ports; i++) { + struct otx2_ssogws *ws; + + ws = event_dev->data->ports[i]; + for (j = 0; j < dev->nb_event_queues; j++) + sso_port_link_modify(ws, j, false); + } +} + static void sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base) { @@ -450,6 +519,8 @@ otx2_sso_configure(const struct rte_eventdev *event_dev) goto teardown_hwggrp; } + /* Clear any prior port-queue mapping. */ + sso_clr_links(event_dev); rc = sso_ggrp_alloc_xaq(dev); if (rc < 0) { otx2_err("Failed to alloc xaq to ggrp %d", rc); @@ -574,6 +645,8 @@ static struct rte_eventdev_ops otx2_sso_ops = { .port_def_conf = otx2_sso_port_def_conf, .port_setup = otx2_sso_port_setup, .port_release = otx2_sso_port_release, + .port_link = otx2_sso_port_link, + .port_unlink = otx2_sso_port_unlink, }; #define OTX2_SSO_XAE_CNT "xae_cnt"