diff mbox series

[v2,11/44] event/octeontx2: add SSO GWS and GGRP IRQ handlers

Message ID 20190628075024.404-12-pbhagavatula@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Jerin Jacob
Headers show
Series OCTEONTX2 event device driver | expand

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues

Commit Message

Pavan Nikhilesh Bhagavatula June 28, 2019, 7:49 a.m. UTC
From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Register and implement SSO GWS and GGRP IRQ handlers for error
interrupts.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/event/octeontx2/Makefile         |   1 +
 drivers/event/octeontx2/meson.build      |   4 +-
 drivers/event/octeontx2/otx2_evdev.c     |  38 +++++
 drivers/event/octeontx2/otx2_evdev.h     |   6 +
 drivers/event/octeontx2/otx2_evdev_irq.c | 175 +++++++++++++++++++++++
 5 files changed, 223 insertions(+), 1 deletion(-)
 create mode 100644 drivers/event/octeontx2/otx2_evdev_irq.c
diff mbox series

Patch

diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile
index 58853e1b9..4f09c1fc8 100644
--- a/drivers/event/octeontx2/Makefile
+++ b/drivers/event/octeontx2/Makefile
@@ -31,6 +31,7 @@  LIBABIVER := 1
 #
 
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_irq.c
 
 LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci -lrte_kvargs
 LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf
diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build
index 3fc96421d..5aa8113bd 100644
--- a/drivers/event/octeontx2/meson.build
+++ b/drivers/event/octeontx2/meson.build
@@ -2,7 +2,9 @@ 
 # Copyright(C) 2019 Marvell International Ltd.
 #
 
-sources = files('otx2_evdev.c')
+sources = files('otx2_evdev.c',
+		'otx2_evdev_irq.c',
+		)
 
 allow_experimental_apis = true
 
diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c
index ef6693bc5..b92bf0407 100644
--- a/drivers/event/octeontx2/otx2_evdev.c
+++ b/drivers/event/octeontx2/otx2_evdev.c
@@ -13,6 +13,29 @@ 
 #include <rte_pci.h>
 
 #include "otx2_evdev.h"
+#include "otx2_irq.h"
+
+static inline int
+sso_get_msix_offsets(const struct rte_eventdev *event_dev)
+{
+	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+	uint8_t nb_ports = dev->nb_event_ports;
+	struct otx2_mbox *mbox = dev->mbox;
+	struct msix_offset_rsp *msix_rsp;
+	int i, rc;
+
+	/* Get SSO and SSOW MSIX vector offsets */
+	otx2_mbox_alloc_msg_msix_offset(mbox);
+	rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
+
+	for (i = 0; i < nb_ports; i++)
+		dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
+
+	for (i = 0; i < dev->nb_event_queues; i++)
+		dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
+
+	return rc;
+}
 
 static void
 otx2_sso_info_get(struct rte_eventdev *event_dev,
@@ -491,6 +514,9 @@  otx2_sso_configure(const struct rte_eventdev *event_dev)
 		return -EINVAL;
 	}
 
+	if (dev->configured)
+		sso_unregister_irqs(event_dev);
+
 	if (dev->nb_event_queues) {
 		/* Finit any previous queues. */
 		sso_lf_teardown(dev, SSO_LF_GGRP);
@@ -527,6 +553,18 @@  otx2_sso_configure(const struct rte_eventdev *event_dev)
 		goto teardown_hwggrp;
 	}
 
+	rc = sso_get_msix_offsets(event_dev);
+	if (rc < 0) {
+		otx2_err("Failed to get msix offsets %d", rc);
+		goto teardown_hwggrp;
+	}
+
+	rc = sso_register_irqs(event_dev);
+	if (rc < 0) {
+		otx2_err("Failed to register irq %d", rc);
+		goto teardown_hwggrp;
+	}
+
 	dev->configured = 1;
 	rte_mb();
 
diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h
index 1a9de1b86..e1d2dcc69 100644
--- a/drivers/event/octeontx2/otx2_evdev.h
+++ b/drivers/event/octeontx2/otx2_evdev.h
@@ -105,6 +105,9 @@  struct otx2_sso_evdev {
 	uint32_t xae_waes;
 	uint32_t xaq_buf_size;
 	uint32_t iue;
+	/* MSIX offsets */
+	uint16_t sso_msixoff[OTX2_SSO_MAX_VHGRP];
+	uint16_t ssow_msixoff[OTX2_SSO_MAX_VHWS];
 } __rte_cache_aligned;
 
 #define OTX2_SSOGWS_OPS \
@@ -148,5 +151,8 @@  parse_kvargs_value(const char *key, const char *value, void *opaque)
 /* Init and Fini API's */
 int otx2_sso_init(struct rte_eventdev *event_dev);
 int otx2_sso_fini(struct rte_eventdev *event_dev);
+/* IRQ handlers */
+int sso_register_irqs(const struct rte_eventdev *event_dev);
+void sso_unregister_irqs(const struct rte_eventdev *event_dev);
 
 #endif /* __OTX2_EVDEV_H__ */
diff --git a/drivers/event/octeontx2/otx2_evdev_irq.c b/drivers/event/octeontx2/otx2_evdev_irq.c
new file mode 100644
index 000000000..7df21cc24
--- /dev/null
+++ b/drivers/event/octeontx2/otx2_evdev_irq.c
@@ -0,0 +1,175 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include "otx2_evdev.h"
+
+static void
+sso_lf_irq(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint64_t intr;
+	uint8_t ggrp;
+
+	ggrp = (base >> 12) & 0xFF;
+
+	intr = otx2_read64(base + SSO_LF_GGRP_INT);
+	if (intr == 0)
+		return;
+
+	otx2_err("GGRP %d GGRP_INT=0x%" PRIx64 "", ggrp, intr);
+
+	/* Clear interrupt */
+	otx2_write64(intr, base + SSO_LF_GGRP_INT);
+}
+
+static int
+sso_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t ggrp_msixoff,
+		    uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int rc, vec;
+
+	vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);
+	/* Set used interrupt vectors */
+	rc = otx2_register_irq(handle, sso_lf_irq, (void *)base, vec);
+	/* Enable hw interrupt */
+	otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1S);
+
+	return rc;
+}
+
+static void
+ssow_lf_irq(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint8_t gws = (base >> 12) & 0xFF;
+	uint64_t intr;
+
+	intr = otx2_read64(base + SSOW_LF_GWS_INT);
+	if (intr == 0)
+		return;
+
+	otx2_err("GWS %d GWS_INT=0x%" PRIx64 "", gws, intr);
+
+	/* Clear interrupt */
+	otx2_write64(intr, base + SSOW_LF_GWS_INT);
+}
+
+static int
+ssow_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t gws_msixoff,
+		     uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int rc, vec;
+
+	vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);
+	/* Set used interrupt vectors */
+	rc = otx2_register_irq(handle, ssow_lf_irq, (void *)base, vec);
+	/* Enable hw interrupt */
+	otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1S);
+
+	return rc;
+}
+
+static void
+sso_lf_unregister_irq(const struct rte_eventdev *event_dev,
+		      uint16_t ggrp_msixoff, uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int vec;
+
+	vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);
+	otx2_unregister_irq(handle, sso_lf_irq, (void *)base, vec);
+}
+
+static void
+ssow_lf_unregister_irq(const struct rte_eventdev *event_dev,
+		       uint16_t gws_msixoff, uintptr_t base)
+{
+	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int vec;
+
+	vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);
+	otx2_unregister_irq(handle, ssow_lf_irq, (void *)base, vec);
+}
+
+int
+sso_register_irqs(const struct rte_eventdev *event_dev)
+{
+	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+	int i, rc = -EINVAL;
+	uint8_t nb_ports;
+
+	nb_ports = dev->nb_event_ports;
+
+	for (i = 0; i < dev->nb_event_queues; i++) {
+		if (dev->sso_msixoff[i] == MSIX_VECTOR_INVALID) {
+			otx2_err("Invalid SSOLF MSIX offset[%d] vector: 0x%x",
+				 i, dev->sso_msixoff[i]);
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < nb_ports; i++) {
+		if (dev->ssow_msixoff[i] == MSIX_VECTOR_INVALID) {
+			otx2_err("Invalid SSOWLF MSIX offset[%d] vector: 0x%x",
+				 i, dev->ssow_msixoff[i]);
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < dev->nb_event_queues; i++) {
+		uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |
+					      i << 12);
+		rc = sso_lf_register_irq(event_dev, dev->sso_msixoff[i], base);
+	}
+
+	for (i = 0; i < nb_ports; i++) {
+		uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |
+					      i << 12);
+		rc = ssow_lf_register_irq(event_dev, dev->ssow_msixoff[i],
+					  base);
+	}
+
+fail:
+	return rc;
+}
+
+void
+sso_unregister_irqs(const struct rte_eventdev *event_dev)
+{
+	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+	uint8_t nb_ports;
+	int i;
+
+	nb_ports = dev->nb_event_ports;
+
+	for (i = 0; i < dev->nb_event_queues; i++) {
+		uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |
+					      i << 12);
+		sso_lf_unregister_irq(event_dev, dev->sso_msixoff[i], base);
+	}
+
+	for (i = 0; i < nb_ports; i++) {
+		uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |
+					      i << 12);
+		ssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base);
+	}
+}