From patchwork Sat Jun 1 18:53:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 54053 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9D6891BBB4; Sat, 1 Jun 2019 20:57:19 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id B08941B955 for ; Sat, 1 Jun 2019 20:56:48 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51It682029402 for ; Sat, 1 Jun 2019 11:56:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=rh7rP1zBU2U0KmD5lx05/RvxUV01y5rWHyBert6Cvyo=; b=K+UtVNd/C2Mc1aw9uUmp8Zx+v8pnvpsG41eJ5c9Kd3/CtTSHkTPFJ0BaKSbgwCipkWqc syY+gp+mVe+b7ei9IryQMEVW3DyOzry6zeKvj1wxmJnh6EgMMbqDzKazjnZVfN2liItq OK4sWmnOOAXNSWcW/AK2Rb0/1RIvjpmn5FE8C7FXYuDvonJ+kusuZCBfKUI4gbe9FJRe SBXXlU8lPmKQnj6mvYQJKnkEWE2K7h6UGcjtN2Z7NU/uyclbYaXh9gMbR6qcQnUZbrmo Q7wR/02ENe6ty2mRsNil56i0Q4tl1wY4lYuOByrA/dALuFNACiS1Z4IksQdil7ZOxF8d UA== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2supqksg1f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:56:47 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:56:47 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:56:47 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id AB5A93F7040; Sat, 1 Jun 2019 11:56:45 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 2 Jun 2019 00:23:52 +0530 Message-ID: <20190601185355.370-43-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 42/44] event/octeontx2: add devargs to limit timer adapters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add devargs to limit the max number of TIM rings reserved on probe. Since, TIM rings are HW resources we can avoid starving other applications by not grabbing all the rings. Example: --dev "0002:0e:00.0,tim_rings_lmt=2" Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 6 +++++- drivers/event/octeontx2/otx2_tim_evdev.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index 2849b8858..c4fd2271e 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -527,6 +527,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, #define OTX2_TIM_DISABLE_NPA "tim_disable_npa" #define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots" #define OTX2_TIM_STATS_ENA "tim_stats_ena" +#define OTX2_TIM_RINGS_LMT "tim_rings_lmt" static void tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) @@ -546,6 +547,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) &parse_kvargs_value, &dev->chunk_slots); rte_kvargs_process(kvlist, OTX2_TIM_STATS_ENA, &parse_kvargs_flag, &dev->enable_stats); + rte_kvargs_process(kvlist, OTX2_TIM_RINGS_LMT, &parse_kvargs_value, + &dev->min_ring_cnt); } void @@ -583,7 +586,8 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev) goto mz_free; } - dev->nb_rings = rsrc_cnt->tim; + dev->nb_rings = dev->min_ring_cnt ? + RTE_MIN(dev->min_ring_cnt, rsrc_cnt->tim) : rsrc_cnt->tim; if (!dev->nb_rings) { otx2_tim_dbg("No TIM Logical functions provisioned."); diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index 79be046f0..ef3c8b50e 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -111,6 +111,7 @@ struct otx2_tim_evdev { /* Dev args */ uint8_t disable_npa; uint16_t chunk_slots; + uint16_t min_ring_cnt; uint8_t enable_stats; /* MSIX offsets */ uint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];